[llvm] [ARM] preferIncOfAddToSubOfNot to handle hasMVEIntegerOps (PR #196316)
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Thu May 7 09:10:06 PDT 2026
https://github.com/LumioseSil updated https://github.com/llvm/llvm-project/pull/196316
>From eccb765f8209bd9db301ee59ce6fe0bd19738383 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Thu, 7 May 2026 09:36:32 -0400
Subject: [PATCH] [ARM] preferIncOfAddToSubOfNot to handle hasMVEIntegerOps
We want to do the vector check for vectors when there is support for them.
---
llvm/lib/Target/ARM/ARMISelLowering.cpp | 4 +-
llvm/test/CodeGen/ARM/inc-of-add.ll | 10 ++---
llvm/test/CodeGen/ARM/sub-of-not.ll | 10 ++---
llvm/test/CodeGen/Thumb2/mve-halving.ll | 60 ++++++++++---------------
llvm/test/CodeGen/Thumb2/mve-vhadd.ll | 23 +++++-----
5 files changed, 46 insertions(+), 61 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index cbff40f697b9b..ef89bf972ac49 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -13781,8 +13781,8 @@ bool ARMTargetLowering::shouldFoldSelectWithIdentityConstant(
}
bool ARMTargetLowering::preferIncOfAddToSubOfNot(EVT VT) const {
- if (!Subtarget->hasNEON()) {
- if (Subtarget->isThumb1Only())
+ if (!Subtarget->hasNEON() && !Subtarget->hasMVEIntegerOps()) {
+ if (VT.isVector() && Subtarget->isThumb1Only())
return VT.getScalarSizeInBits() <= 32;
return true;
}
diff --git a/llvm/test/CodeGen/ARM/inc-of-add.ll b/llvm/test/CodeGen/ARM/inc-of-add.ll
index 3079dbceb9844..e0756d5f90764 100644
--- a/llvm/test/CodeGen/ARM/inc-of-add.ll
+++ b/llvm/test/CodeGen/ARM/inc-of-add.ll
@@ -91,11 +91,11 @@ define i64 @scalar_i64(i64 %x, i64 %y) nounwind {
;
; THUMB6-LABEL: scalar_i64:
; THUMB6: @ %bb.0:
-; THUMB6-NEXT: mvns r1, r1
-; THUMB6-NEXT: mvns r0, r0
-; THUMB6-NEXT: subs r0, r2, r0
-; THUMB6-NEXT: sbcs r3, r1
-; THUMB6-NEXT: mov r1, r3
+; THUMB6-NEXT: adds r0, r0, r2
+; THUMB6-NEXT: adcs r1, r3
+; THUMB6-NEXT: movs r2, #0
+; THUMB6-NEXT: adds r0, r0, #1
+; THUMB6-NEXT: adcs r1, r2
; THUMB6-NEXT: bx lr
;
; THUMB78-LABEL: scalar_i64:
diff --git a/llvm/test/CodeGen/ARM/sub-of-not.ll b/llvm/test/CodeGen/ARM/sub-of-not.ll
index 97c6f8f25a3bb..502e3aa684a50 100644
--- a/llvm/test/CodeGen/ARM/sub-of-not.ll
+++ b/llvm/test/CodeGen/ARM/sub-of-not.ll
@@ -91,11 +91,11 @@ define i64 @scalar_i64(i64 %x, i64 %y) nounwind {
;
; THUMB6-LABEL: scalar_i64:
; THUMB6: @ %bb.0:
-; THUMB6-NEXT: mvns r1, r1
-; THUMB6-NEXT: mvns r0, r0
-; THUMB6-NEXT: subs r0, r2, r0
-; THUMB6-NEXT: sbcs r3, r1
-; THUMB6-NEXT: mov r1, r3
+; THUMB6-NEXT: adds r0, r2, r0
+; THUMB6-NEXT: adcs r1, r3
+; THUMB6-NEXT: movs r2, #0
+; THUMB6-NEXT: adds r0, r0, #1
+; THUMB6-NEXT: adcs r1, r2
; THUMB6-NEXT: bx lr
;
; THUMB78-LABEL: scalar_i64:
diff --git a/llvm/test/CodeGen/Thumb2/mve-halving.ll b/llvm/test/CodeGen/Thumb2/mve-halving.ll
index b4dc97cf13311..524818e8d210d 100644
--- a/llvm/test/CodeGen/Thumb2/mve-halving.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-halving.ll
@@ -233,9 +233,8 @@ define arm_aapcs_vfpcc <4 x i32> @vhsubu_v4i32_nw(<4 x i32> %x, <4 x i32> %y) {
define arm_aapcs_vfpcc <16 x i8> @vrhadds_v16i8(<16 x i8> %x, <16 x i8> %y) {
; CHECK-LABEL: vrhadds_v16i8:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vadd.i8 q0, q0, q1
-; CHECK-NEXT: movs r0, #1
-; CHECK-NEXT: vadd.i8 q0, q0, r0
+; CHECK-NEXT: vmvn q0, q0
+; CHECK-NEXT: vsub.i8 q0, q1, q0
; CHECK-NEXT: vshr.s8 q0, q0, #1
; CHECK-NEXT: bx lr
%add = add <16 x i8> %x, %y
@@ -246,9 +245,8 @@ define arm_aapcs_vfpcc <16 x i8> @vrhadds_v16i8(<16 x i8> %x, <16 x i8> %y) {
define arm_aapcs_vfpcc <16 x i8> @vrhaddu_v16i8(<16 x i8> %x, <16 x i8> %y) {
; CHECK-LABEL: vrhaddu_v16i8:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vadd.i8 q0, q0, q1
-; CHECK-NEXT: movs r0, #1
-; CHECK-NEXT: vadd.i8 q0, q0, r0
+; CHECK-NEXT: vmvn q0, q0
+; CHECK-NEXT: vsub.i8 q0, q1, q0
; CHECK-NEXT: vshr.u8 q0, q0, #1
; CHECK-NEXT: bx lr
%add = add <16 x i8> %x, %y
@@ -259,9 +257,8 @@ define arm_aapcs_vfpcc <16 x i8> @vrhaddu_v16i8(<16 x i8> %x, <16 x i8> %y) {
define arm_aapcs_vfpcc <8 x i16> @vrhadds_v8i16(<8 x i16> %x, <8 x i16> %y) {
; CHECK-LABEL: vrhadds_v8i16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vadd.i16 q0, q0, q1
-; CHECK-NEXT: movs r0, #1
-; CHECK-NEXT: vadd.i16 q0, q0, r0
+; CHECK-NEXT: vmvn q0, q0
+; CHECK-NEXT: vsub.i16 q0, q1, q0
; CHECK-NEXT: vshr.s16 q0, q0, #1
; CHECK-NEXT: bx lr
%add = add <8 x i16> %x, %y
@@ -272,9 +269,8 @@ define arm_aapcs_vfpcc <8 x i16> @vrhadds_v8i16(<8 x i16> %x, <8 x i16> %y) {
define arm_aapcs_vfpcc <8 x i16> @vrhaddu_v8i16(<8 x i16> %x, <8 x i16> %y) {
; CHECK-LABEL: vrhaddu_v8i16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vadd.i16 q0, q0, q1
-; CHECK-NEXT: movs r0, #1
-; CHECK-NEXT: vadd.i16 q0, q0, r0
+; CHECK-NEXT: vmvn q0, q0
+; CHECK-NEXT: vsub.i16 q0, q1, q0
; CHECK-NEXT: vshr.u16 q0, q0, #1
; CHECK-NEXT: bx lr
%add = add <8 x i16> %x, %y
@@ -285,9 +281,8 @@ define arm_aapcs_vfpcc <8 x i16> @vrhaddu_v8i16(<8 x i16> %x, <8 x i16> %y) {
define arm_aapcs_vfpcc <4 x i32> @vrhadds_v4i32(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: vrhadds_v4i32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vadd.i32 q0, q0, q1
-; CHECK-NEXT: movs r0, #1
-; CHECK-NEXT: vadd.i32 q0, q0, r0
+; CHECK-NEXT: vmvn q0, q0
+; CHECK-NEXT: vsub.i32 q0, q1, q0
; CHECK-NEXT: vshr.s32 q0, q0, #1
; CHECK-NEXT: bx lr
%add = add <4 x i32> %x, %y
@@ -298,9 +293,8 @@ define arm_aapcs_vfpcc <4 x i32> @vrhadds_v4i32(<4 x i32> %x, <4 x i32> %y) {
define arm_aapcs_vfpcc <4 x i32> @vrhaddu_v4i32(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: vrhaddu_v4i32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vadd.i32 q0, q0, q1
-; CHECK-NEXT: movs r0, #1
-; CHECK-NEXT: vadd.i32 q0, q0, r0
+; CHECK-NEXT: vmvn q0, q0
+; CHECK-NEXT: vsub.i32 q0, q1, q0
; CHECK-NEXT: vshr.u32 q0, q0, #1
; CHECK-NEXT: bx lr
%add = add <4 x i32> %x, %y
@@ -311,9 +305,8 @@ define arm_aapcs_vfpcc <4 x i32> @vrhaddu_v4i32(<4 x i32> %x, <4 x i32> %y) {
define arm_aapcs_vfpcc <16 x i8> @vrhadds_v16i8_nwop(<16 x i8> %x, <16 x i8> %y) {
; CHECK-LABEL: vrhadds_v16i8_nwop:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vadd.i8 q0, q0, q1
-; CHECK-NEXT: movs r0, #1
-; CHECK-NEXT: vadd.i8 q0, q0, r0
+; CHECK-NEXT: vmvn q0, q0
+; CHECK-NEXT: vsub.i8 q0, q1, q0
; CHECK-NEXT: vshr.s8 q0, q0, #1
; CHECK-NEXT: bx lr
%add = add nsw <16 x i8> %x, %y
@@ -324,9 +317,8 @@ define arm_aapcs_vfpcc <16 x i8> @vrhadds_v16i8_nwop(<16 x i8> %x, <16 x i8> %y)
define arm_aapcs_vfpcc <16 x i8> @vrhaddu_v16i8_nwop(<16 x i8> %x, <16 x i8> %y) {
; CHECK-LABEL: vrhaddu_v16i8_nwop:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vadd.i8 q0, q0, q1
-; CHECK-NEXT: movs r0, #1
-; CHECK-NEXT: vadd.i8 q0, q0, r0
+; CHECK-NEXT: vmvn q0, q0
+; CHECK-NEXT: vsub.i8 q0, q1, q0
; CHECK-NEXT: vshr.u8 q0, q0, #1
; CHECK-NEXT: bx lr
%add = add nuw <16 x i8> %x, %y
@@ -337,9 +329,8 @@ define arm_aapcs_vfpcc <16 x i8> @vrhaddu_v16i8_nwop(<16 x i8> %x, <16 x i8> %y)
define arm_aapcs_vfpcc <8 x i16> @vrhadds_v8i16_nwop(<8 x i16> %x, <8 x i16> %y) {
; CHECK-LABEL: vrhadds_v8i16_nwop:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vadd.i16 q0, q0, q1
-; CHECK-NEXT: movs r0, #1
-; CHECK-NEXT: vadd.i16 q0, q0, r0
+; CHECK-NEXT: vmvn q0, q0
+; CHECK-NEXT: vsub.i16 q0, q1, q0
; CHECK-NEXT: vshr.s16 q0, q0, #1
; CHECK-NEXT: bx lr
%add = add nsw <8 x i16> %x, %y
@@ -350,9 +341,8 @@ define arm_aapcs_vfpcc <8 x i16> @vrhadds_v8i16_nwop(<8 x i16> %x, <8 x i16> %y)
define arm_aapcs_vfpcc <8 x i16> @vrhaddu_v8i16_nwop(<8 x i16> %x, <8 x i16> %y) {
; CHECK-LABEL: vrhaddu_v8i16_nwop:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vadd.i16 q0, q0, q1
-; CHECK-NEXT: movs r0, #1
-; CHECK-NEXT: vadd.i16 q0, q0, r0
+; CHECK-NEXT: vmvn q0, q0
+; CHECK-NEXT: vsub.i16 q0, q1, q0
; CHECK-NEXT: vshr.u16 q0, q0, #1
; CHECK-NEXT: bx lr
%add = add nuw <8 x i16> %x, %y
@@ -363,9 +353,8 @@ define arm_aapcs_vfpcc <8 x i16> @vrhaddu_v8i16_nwop(<8 x i16> %x, <8 x i16> %y)
define arm_aapcs_vfpcc <4 x i32> @vrhadds_v4i32_nwop(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: vrhadds_v4i32_nwop:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vadd.i32 q0, q0, q1
-; CHECK-NEXT: movs r0, #1
-; CHECK-NEXT: vadd.i32 q0, q0, r0
+; CHECK-NEXT: vmvn q0, q0
+; CHECK-NEXT: vsub.i32 q0, q1, q0
; CHECK-NEXT: vshr.s32 q0, q0, #1
; CHECK-NEXT: bx lr
%add = add nsw <4 x i32> %x, %y
@@ -376,9 +365,8 @@ define arm_aapcs_vfpcc <4 x i32> @vrhadds_v4i32_nwop(<4 x i32> %x, <4 x i32> %y)
define arm_aapcs_vfpcc <4 x i32> @vrhaddu_v4i32_nwop(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: vrhaddu_v4i32_nwop:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vadd.i32 q0, q0, q1
-; CHECK-NEXT: movs r0, #1
-; CHECK-NEXT: vadd.i32 q0, q0, r0
+; CHECK-NEXT: vmvn q0, q0
+; CHECK-NEXT: vsub.i32 q0, q1, q0
; CHECK-NEXT: vshr.u32 q0, q0, #1
; CHECK-NEXT: bx lr
%add = add nuw <4 x i32> %x, %y
diff --git a/llvm/test/CodeGen/Thumb2/mve-vhadd.ll b/llvm/test/CodeGen/Thumb2/mve-vhadd.ll
index 82a286627a9e5..207c0f377e34a 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vhadd.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vhadd.ll
@@ -221,11 +221,10 @@ entry:
define arm_aapcs_vfpcc <4 x i16> @vrhadds_v4i16(<4 x i16> %s0, <4 x i16> %s1) {
; CHECK-LABEL: vrhadds_v4i16:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmovlb.s16 q1, q1
; CHECK-NEXT: vmovlb.s16 q0, q0
-; CHECK-NEXT: vadd.i32 q0, q0, q1
-; CHECK-NEXT: movs r0, #1
-; CHECK-NEXT: vadd.i32 q0, q0, r0
+; CHECK-NEXT: vmovlb.s16 q1, q1
+; CHECK-NEXT: vmvn q0, q0
+; CHECK-NEXT: vsub.i32 q0, q1, q0
; CHECK-NEXT: vshr.u32 q0, q0, #1
; CHECK-NEXT: bx lr
entry:
@@ -288,13 +287,12 @@ entry:
define arm_aapcs_vfpcc <4 x i8> @vrhadds_v4i8(<4 x i8> %s0, <4 x i8> %s1) {
; CHECK-LABEL: vrhadds_v4i8:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmovlb.s8 q1, q1
; CHECK-NEXT: vmovlb.s8 q0, q0
-; CHECK-NEXT: vmovlb.s16 q1, q1
+; CHECK-NEXT: vmovlb.s8 q1, q1
; CHECK-NEXT: vmovlb.s16 q0, q0
-; CHECK-NEXT: vadd.i32 q0, q0, q1
-; CHECK-NEXT: movs r0, #1
-; CHECK-NEXT: vadd.i32 q0, q0, r0
+; CHECK-NEXT: vmovlb.s16 q1, q1
+; CHECK-NEXT: vmvn q0, q0
+; CHECK-NEXT: vsub.i32 q0, q1, q0
; CHECK-NEXT: vmovlb.u16 q0, q0
; CHECK-NEXT: vshr.u32 q0, q0, #1
; CHECK-NEXT: bx lr
@@ -329,11 +327,10 @@ entry:
define arm_aapcs_vfpcc <8 x i8> @vrhadds_v8i8(<8 x i8> %s0, <8 x i8> %s1) {
; CHECK-LABEL: vrhadds_v8i8:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmovlb.s8 q1, q1
; CHECK-NEXT: vmovlb.s8 q0, q0
-; CHECK-NEXT: vadd.i16 q0, q0, q1
-; CHECK-NEXT: movs r0, #1
-; CHECK-NEXT: vadd.i16 q0, q0, r0
+; CHECK-NEXT: vmovlb.s8 q1, q1
+; CHECK-NEXT: vmvn q0, q0
+; CHECK-NEXT: vsub.i16 q0, q1, q0
; CHECK-NEXT: vshr.u16 q0, q0, #1
; CHECK-NEXT: bx lr
entry:
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