[llvm] [AArch64] Lower i16/f16 bitcast via vector operations. (PR #196341)
David Green via llvm-commits
llvm-commits at lists.llvm.org
Thu May 7 08:05:14 PDT 2026
https://github.com/davemgreen created https://github.com/llvm/llvm-project/pull/196341
This removes one of the uses of getTargetExtractSubreg, that creates a Machine Node during DAG lowering. We instead use a scalar_to_vector to convert to a vector and let the extract element legalize to a legal type.
>From cd302e7adc5a07cfb202cd40f9d13779c59792f7 Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Thu, 7 May 2026 12:59:29 +0100
Subject: [PATCH 1/2] [AArch64] Regenerate concat_vector-scalar-combine.ll. NFC
---
.../AArch64/concat_vector-scalar-combine.ll | 81 ++++++++++---------
1 file changed, 41 insertions(+), 40 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/concat_vector-scalar-combine.ll b/llvm/test/CodeGen/AArch64/concat_vector-scalar-combine.ll
index ce3b1f5e6b7b6..9d58608315a29 100644
--- a/llvm/test/CodeGen/AArch64/concat_vector-scalar-combine.ll
+++ b/llvm/test/CodeGen/AArch64/concat_vector-scalar-combine.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple aarch64-unknown-unknown -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
@@ -5,10 +6,10 @@ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
; Test the (concat_vectors (bitcast (scalar)), ..) pattern.
define <8 x i8> @test_concat_scalar_v2i8_to_v8i8_dup(i32 %x) #0 {
-entry:
; CHECK-LABEL: test_concat_scalar_v2i8_to_v8i8_dup:
-; CHECK-NEXT: dup.4h v0, w0
-; CHECK-NEXT: ret
+; CHECK: dup.4h v0, w0
+; CHECK-NEXT: ret
+entry:
%t = trunc i32 %x to i16
%0 = bitcast i16 %t to <2 x i8>
%1 = shufflevector <2 x i8> %0, <2 x i8> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1>
@@ -16,32 +17,32 @@ entry:
}
define <8 x i8> @test_concat_scalar_v4i8_to_v8i8_dup(i32 %x) #0 {
-entry:
; CHECK-LABEL: test_concat_scalar_v4i8_to_v8i8_dup:
-; CHECK-NEXT: dup.2s v0, w0
-; CHECK-NEXT: ret
+; CHECK: dup.2s v0, w0
+; CHECK-NEXT: ret
+entry:
%0 = bitcast i32 %x to <4 x i8>
%1 = shufflevector <4 x i8> %0, <4 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
ret <8 x i8> %1
}
define <8 x i16> @test_concat_scalar_v2i16_to_v8i16_dup(i32 %x) #0 {
-entry:
; CHECK-LABEL: test_concat_scalar_v2i16_to_v8i16_dup:
-; CHECK-NEXT: dup.4s v0, w0
-; CHECK-NEXT: ret
+; CHECK: dup.4s v0, w0
+; CHECK-NEXT: ret
+entry:
%0 = bitcast i32 %x to <2 x i16>
%1 = shufflevector <2 x i16> %0, <2 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 2, i32 0, i32 1, i32 0, i32 1>
ret <8 x i16> %1
}
define <8 x i8> @test_concat_scalars_2x_v2i8_to_v8i8(i32 %x, i32 %y) #0 {
-entry:
; CHECK-LABEL: test_concat_scalars_2x_v2i8_to_v8i8:
-; CHECK-NEXT: fmov s0, w0
-; CHECK-NEXT: mov.h v0[1], w1
-; CHECK-NEXT: mov.h v0[3], w1
-; CHECK-NEXT: ret
+; CHECK: fmov s0, w0
+; CHECK-NEXT: mov.h v0[1], w1
+; CHECK-NEXT: mov.h v0[3], w1
+; CHECK-NEXT: ret
+entry:
%tx = trunc i32 %x to i16
%ty = trunc i32 %y to i16
%bx = bitcast i16 %tx to <2 x i8>
@@ -51,11 +52,11 @@ entry:
}
define <8 x i8> @test_concat_scalars_2x_v4i8_to_v8i8_dup(i32 %x, i32 %y) #0 {
-entry:
; CHECK-LABEL: test_concat_scalars_2x_v4i8_to_v8i8_dup:
-; CHECK-NEXT: fmov s0, w1
-; CHECK-NEXT: mov.s v0[1], w0
-; CHECK-NEXT: ret
+; CHECK: fmov s0, w1
+; CHECK-NEXT: mov.s v0[1], w0
+; CHECK-NEXT: ret
+entry:
%bx = bitcast i32 %x to <4 x i8>
%by = bitcast i32 %y to <4 x i8>
%r = shufflevector <4 x i8> %bx, <4 x i8> %by, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
@@ -63,13 +64,13 @@ entry:
}
define <8 x i16> @test_concat_scalars_2x_v2i16_to_v8i16_dup(i32 %x, i32 %y) #0 {
-entry:
; CHECK-LABEL: test_concat_scalars_2x_v2i16_to_v8i16_dup:
-; CHECK-NEXT: fmov s0, w0
-; CHECK-NEXT: mov.s v0[1], w1
-; CHECK-NEXT: mov.s v0[2], w1
-; CHECK-NEXT: mov.s v0[3], w0
-; CHECK-NEXT: ret
+; CHECK: fmov s0, w0
+; CHECK-NEXT: mov.s v0[1], w1
+; CHECK-NEXT: mov.s v0[2], w1
+; CHECK-NEXT: mov.s v0[3], w0
+; CHECK-NEXT: ret
+entry:
%bx = bitcast i32 %x to <2 x i16>
%by = bitcast i32 %y to <2 x i16>
%r = shufflevector <2 x i16> %bx, <2 x i16> %by, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 0, i32 1>
@@ -81,14 +82,14 @@ entry:
; This is a pretty artificial testcase: make sure we bitcast to floating-point
; if any of the scalars is floating-point.
define <8 x i8> @test_concat_scalars_mixed_2x_v2i8_to_v8i8(float %dummy, i32 %x, half %y) #0 {
-entry:
; CHECK-LABEL: test_concat_scalars_mixed_2x_v2i8_to_v8i8:
-; CHECK-NEXT: fmov s[[X:[0-9]+]], w0
-; CHECK-NEXT: mov.16b v0, v[[X]]
-; CHECK-NEXT: mov.h v0[1], v1[0]
-; CHECK-NEXT: mov.h v0[2], v[[X]][0]
-; CHECK-NEXT: mov.h v0[3], v1[0]
-; CHECK-NEXT: ret
+; CHECK: fmov s2, w0
+; CHECK-NEXT: mov.16b v0, v2
+; CHECK-NEXT: mov.h v0[1], v1[0]
+; CHECK-NEXT: mov.h v0[2], v2[0]
+; CHECK-NEXT: mov.h v0[3], v1[0]
+; CHECK-NEXT: ret
+entry:
%t = trunc i32 %x to i16
%0 = bitcast i16 %t to <2 x i8>
%y0 = bitcast half %y to <2 x i8>
@@ -97,13 +98,13 @@ entry:
}
define <2 x float> @test_concat_scalars_fp_2x_v2i8_to_v8i8(float %dummy, half %x, half %y) #0 {
-entry:
; CHECK-LABEL: test_concat_scalars_fp_2x_v2i8_to_v8i8:
-; CHECK-NEXT: mov.16b v0, v1
-; CHECK-NEXT: mov.h v0[1], v2[0]
-; CHECK-NEXT: mov.h v0[2], v1[0]
-; CHECK-NEXT: mov.h v0[3], v2[0]
-; CHECK-NEXT: ret
+; CHECK: mov.16b v0, v1
+; CHECK-NEXT: mov.h v0[1], v2[0]
+; CHECK-NEXT: mov.h v0[2], v1[0]
+; CHECK-NEXT: mov.h v0[3], v2[0]
+; CHECK-NEXT: ret
+entry:
%0 = bitcast half %x to <2 x i8>
%y0 = bitcast half %y to <2 x i8>
%1 = shufflevector <2 x i8> %0, <2 x i8> %y0, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
@@ -112,10 +113,10 @@ entry:
}
define <4 x float> @test_concat_scalar_fp_v2i16_to_v16i8_dup(float %x) #0 {
-entry:
; CHECK-LABEL: test_concat_scalar_fp_v2i16_to_v16i8_dup:
-; CHECK-NEXT: dup.4s v0, v0[0]
-; CHECK-NEXT: ret
+; CHECK: dup.4s v0, v0[0]
+; CHECK-NEXT: ret
+entry:
%0 = bitcast float %x to <2 x i16>
%1 = shufflevector <2 x i16> %0, <2 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 2, i32 0, i32 1, i32 0, i32 1>
%2 = bitcast <8 x i16> %1 to <4 x float>
>From f24e6254bb18f454c80162ff2f779adac0db100a Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Thu, 7 May 2026 15:58:51 +0100
Subject: [PATCH 2/2] [AArch64] Lower i16/f16 bitcast via vector operations.
This removes one of the uses of getTargetExtractSubreg, that creates a Machine
Node during DAG lowering. We instead use a scalar_to_vector to convert to a
vector and let the extract element legalize to a legal type.
---
.../Target/AArch64/AArch64ISelLowering.cpp | 18 ++++++++++--
.../aarch64-inline-asm-bitcast-crash.ll | 6 ++--
llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll | 16 +++++------
llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll | 16 +++++------
llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll | 16 +++++------
llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll | 16 +++++------
.../test/CodeGen/AArch64/atomicrmw-xchg-fp.ll | 4 +--
.../test/CodeGen/AArch64/bf16-instructions.ll | 28 +++++++++++++++----
llvm/test/CodeGen/AArch64/f16-instructions.ll | 28 +++++++++++++++----
.../CodeGen/AArch64/fp16-vector-shuffle.ll | 2 --
llvm/test/CodeGen/AArch64/half.ll | 2 +-
.../test/CodeGen/AArch64/load-zext-bitcast.ll | 14 +++++-----
.../AArch64/neon-extractbitcast-mir.ll | 7 ++---
.../CodeGen/AArch64/neon-insextbitcast.ll | 2 --
14 files changed, 108 insertions(+), 67 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 8c53ea0dd94eb..747e90decb274 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -5569,9 +5569,21 @@ SDValue AArch64TargetLowering::LowerBITCAST(SDValue Op,
assert(ArgVT == MVT::i16);
- Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Src);
- Op = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Op);
- return DAG.getTargetExtractSubreg(AArch64::hsub, DL, OpVT, Op);
+ // If the input from a vector, extract directly from it.
+ if (Src.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
+ Op = DAG.getNode(ISD::BITCAST, DL,
+ Src.getOperand(0).getValueType().changeElementType(
+ *DAG.getContext(), OpVT),
+ Src.getOperand(0));
+ return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, OpVT, Op,
+ Src.getOperand(1));
+ }
+
+ Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v8i16, Src);
+ Op = DAG.getNode(ISD::BITCAST, DL,
+ EVT::getVectorVT(*DAG.getContext(), OpVT, 8), Op);
+ return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, OpVT, Op,
+ DAG.getConstant(0, DL, MVT::i64));
}
// Returns lane if Op extracts from a two-element vector and lane is constant
diff --git a/llvm/test/CodeGen/AArch64/aarch64-inline-asm-bitcast-crash.ll b/llvm/test/CodeGen/AArch64/aarch64-inline-asm-bitcast-crash.ll
index fde67d65ddb31..1e62d5e56ac6e 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-inline-asm-bitcast-crash.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-inline-asm-bitcast-crash.ll
@@ -12,8 +12,7 @@ define void @f(<2 x i8> %1) {
; LE-NEXT: mov s1, v0.s[1]
; LE-NEXT: str b0, [sp, #12]
; LE-NEXT: stur b1, [sp, #13]
-; LE-NEXT: ldrh w8, [sp, #12]
-; LE-NEXT: fmov s0, w8
+; LE-NEXT: ldr h0, [sp, #12]
; LE-NEXT: //APP
; LE-NEXT: //NO_APP
; LE-NEXT: add sp, sp, #16
@@ -27,8 +26,7 @@ define void @f(<2 x i8> %1) {
; BE-NEXT: mov s1, v0.s[1]
; BE-NEXT: str b0, [sp, #12]
; BE-NEXT: stur b1, [sp, #13]
-; BE-NEXT: ldrh w8, [sp, #12]
-; BE-NEXT: fmov s0, w8
+; BE-NEXT: ldr h0, [sp, #12]
; BE-NEXT: //APP
; BE-NEXT: //NO_APP
; BE-NEXT: add sp, sp, #16
diff --git a/llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll b/llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll
index c06215204cd76..1a68577fbf91c 100644
--- a/llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll
+++ b/llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll
@@ -18,7 +18,7 @@ define half @test_atomicrmw_fadd_f16_seq_cst_align2(ptr %ptr, half %value) #0 {
; NOLSE-NEXT: stlxrh w9, w8, [x0]
; NOLSE-NEXT: cbnz w9, .LBB0_1
; NOLSE-NEXT: // %bb.2: // %atomicrmw.end
-; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $s0
+; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $q0
; NOLSE-NEXT: ret
;
; LSE-LABEL: test_atomicrmw_fadd_f16_seq_cst_align2:
@@ -38,7 +38,7 @@ define half @test_atomicrmw_fadd_f16_seq_cst_align2(ptr %ptr, half %value) #0 {
; LSE-NEXT: cmp w10, w8, uxth
; LSE-NEXT: b.ne .LBB0_1
; LSE-NEXT: // %bb.2: // %atomicrmw.end
-; LSE-NEXT: // kill: def $h0 killed $h0 killed $s0
+; LSE-NEXT: // kill: def $h0 killed $h0 killed $q0
; LSE-NEXT: ret
;
; SOFTFP-NOLSE-LABEL: test_atomicrmw_fadd_f16_seq_cst_align2:
@@ -106,7 +106,7 @@ define half @test_atomicrmw_fadd_f16_seq_cst_align4(ptr %ptr, half %value) #0 {
; NOLSE-NEXT: stlxrh w9, w8, [x0]
; NOLSE-NEXT: cbnz w9, .LBB1_1
; NOLSE-NEXT: // %bb.2: // %atomicrmw.end
-; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $s0
+; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $q0
; NOLSE-NEXT: ret
;
; LSE-LABEL: test_atomicrmw_fadd_f16_seq_cst_align4:
@@ -126,7 +126,7 @@ define half @test_atomicrmw_fadd_f16_seq_cst_align4(ptr %ptr, half %value) #0 {
; LSE-NEXT: cmp w10, w8, uxth
; LSE-NEXT: b.ne .LBB1_1
; LSE-NEXT: // %bb.2: // %atomicrmw.end
-; LSE-NEXT: // kill: def $h0 killed $h0 killed $s0
+; LSE-NEXT: // kill: def $h0 killed $h0 killed $q0
; LSE-NEXT: ret
;
; SOFTFP-NOLSE-LABEL: test_atomicrmw_fadd_f16_seq_cst_align4:
@@ -199,7 +199,7 @@ define bfloat @test_atomicrmw_fadd_bf16_seq_cst_align2(ptr %ptr, bfloat %value)
; NOLSE-NEXT: stlxrh w10, w9, [x0]
; NOLSE-NEXT: cbnz w10, .LBB2_1
; NOLSE-NEXT: // %bb.2: // %atomicrmw.end
-; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $d0
+; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $q0
; NOLSE-NEXT: ret
;
; LSE-LABEL: test_atomicrmw_fadd_bf16_seq_cst_align2:
@@ -226,7 +226,7 @@ define bfloat @test_atomicrmw_fadd_bf16_seq_cst_align2(ptr %ptr, bfloat %value)
; LSE-NEXT: cmp w11, w9, uxth
; LSE-NEXT: b.ne .LBB2_1
; LSE-NEXT: // %bb.2: // %atomicrmw.end
-; LSE-NEXT: // kill: def $h0 killed $h0 killed $d0
+; LSE-NEXT: // kill: def $h0 killed $h0 killed $q0
; LSE-NEXT: ret
;
; SOFTFP-NOLSE-LABEL: test_atomicrmw_fadd_bf16_seq_cst_align2:
@@ -293,7 +293,7 @@ define bfloat @test_atomicrmw_fadd_bf16_seq_cst_align4(ptr %ptr, bfloat %value)
; NOLSE-NEXT: stlxrh w10, w9, [x0]
; NOLSE-NEXT: cbnz w10, .LBB3_1
; NOLSE-NEXT: // %bb.2: // %atomicrmw.end
-; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $d0
+; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $q0
; NOLSE-NEXT: ret
;
; LSE-LABEL: test_atomicrmw_fadd_bf16_seq_cst_align4:
@@ -320,7 +320,7 @@ define bfloat @test_atomicrmw_fadd_bf16_seq_cst_align4(ptr %ptr, bfloat %value)
; LSE-NEXT: cmp w11, w9, uxth
; LSE-NEXT: b.ne .LBB3_1
; LSE-NEXT: // %bb.2: // %atomicrmw.end
-; LSE-NEXT: // kill: def $h0 killed $h0 killed $d0
+; LSE-NEXT: // kill: def $h0 killed $h0 killed $q0
; LSE-NEXT: ret
;
; SOFTFP-NOLSE-LABEL: test_atomicrmw_fadd_bf16_seq_cst_align4:
diff --git a/llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll b/llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll
index 16825c9dcd178..794ee795528a3 100644
--- a/llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll
+++ b/llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll
@@ -20,7 +20,7 @@ define half @test_atomicrmw_fmax_f16_seq_cst_align2(ptr %ptr, half %value) #0 {
; NOLSE-NEXT: stlxrh w9, w8, [x0]
; NOLSE-NEXT: cbnz w9, .LBB0_1
; NOLSE-NEXT: // %bb.2: // %atomicrmw.end
-; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $s0
+; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $q0
; NOLSE-NEXT: ret
;
; LSE-LABEL: test_atomicrmw_fmax_f16_seq_cst_align2:
@@ -40,7 +40,7 @@ define half @test_atomicrmw_fmax_f16_seq_cst_align2(ptr %ptr, half %value) #0 {
; LSE-NEXT: cmp w10, w8, uxth
; LSE-NEXT: b.ne .LBB0_1
; LSE-NEXT: // %bb.2: // %atomicrmw.end
-; LSE-NEXT: // kill: def $h0 killed $h0 killed $s0
+; LSE-NEXT: // kill: def $h0 killed $h0 killed $q0
; LSE-NEXT: ret
;
; SOFTFP-NOLSE-LABEL: test_atomicrmw_fmax_f16_seq_cst_align2:
@@ -108,7 +108,7 @@ define half @test_atomicrmw_fmax_f16_seq_cst_align4(ptr %ptr, half %value) #0 {
; NOLSE-NEXT: stlxrh w9, w8, [x0]
; NOLSE-NEXT: cbnz w9, .LBB1_1
; NOLSE-NEXT: // %bb.2: // %atomicrmw.end
-; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $s0
+; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $q0
; NOLSE-NEXT: ret
;
; LSE-LABEL: test_atomicrmw_fmax_f16_seq_cst_align4:
@@ -128,7 +128,7 @@ define half @test_atomicrmw_fmax_f16_seq_cst_align4(ptr %ptr, half %value) #0 {
; LSE-NEXT: cmp w10, w8, uxth
; LSE-NEXT: b.ne .LBB1_1
; LSE-NEXT: // %bb.2: // %atomicrmw.end
-; LSE-NEXT: // kill: def $h0 killed $h0 killed $s0
+; LSE-NEXT: // kill: def $h0 killed $h0 killed $q0
; LSE-NEXT: ret
;
; SOFTFP-NOLSE-LABEL: test_atomicrmw_fmax_f16_seq_cst_align4:
@@ -201,7 +201,7 @@ define bfloat @test_atomicrmw_fmax_bf16_seq_cst_align2(ptr %ptr, bfloat %value)
; NOLSE-NEXT: stlxrh w10, w9, [x0]
; NOLSE-NEXT: cbnz w10, .LBB2_1
; NOLSE-NEXT: // %bb.2: // %atomicrmw.end
-; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $d0
+; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $q0
; NOLSE-NEXT: ret
;
; LSE-LABEL: test_atomicrmw_fmax_bf16_seq_cst_align2:
@@ -228,7 +228,7 @@ define bfloat @test_atomicrmw_fmax_bf16_seq_cst_align2(ptr %ptr, bfloat %value)
; LSE-NEXT: cmp w11, w9, uxth
; LSE-NEXT: b.ne .LBB2_1
; LSE-NEXT: // %bb.2: // %atomicrmw.end
-; LSE-NEXT: // kill: def $h0 killed $h0 killed $d0
+; LSE-NEXT: // kill: def $h0 killed $h0 killed $q0
; LSE-NEXT: ret
;
; SOFTFP-NOLSE-LABEL: test_atomicrmw_fmax_bf16_seq_cst_align2:
@@ -295,7 +295,7 @@ define bfloat @test_atomicrmw_fmax_bf16_seq_cst_align4(ptr %ptr, bfloat %value)
; NOLSE-NEXT: stlxrh w10, w9, [x0]
; NOLSE-NEXT: cbnz w10, .LBB3_1
; NOLSE-NEXT: // %bb.2: // %atomicrmw.end
-; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $d0
+; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $q0
; NOLSE-NEXT: ret
;
; LSE-LABEL: test_atomicrmw_fmax_bf16_seq_cst_align4:
@@ -322,7 +322,7 @@ define bfloat @test_atomicrmw_fmax_bf16_seq_cst_align4(ptr %ptr, bfloat %value)
; LSE-NEXT: cmp w11, w9, uxth
; LSE-NEXT: b.ne .LBB3_1
; LSE-NEXT: // %bb.2: // %atomicrmw.end
-; LSE-NEXT: // kill: def $h0 killed $h0 killed $d0
+; LSE-NEXT: // kill: def $h0 killed $h0 killed $q0
; LSE-NEXT: ret
;
; SOFTFP-NOLSE-LABEL: test_atomicrmw_fmax_bf16_seq_cst_align4:
diff --git a/llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll b/llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll
index 314075c619103..60118e3eddd16 100644
--- a/llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll
+++ b/llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll
@@ -20,7 +20,7 @@ define half @test_atomicrmw_fmin_f16_seq_cst_align2(ptr %ptr, half %value) #0 {
; NOLSE-NEXT: stlxrh w9, w8, [x0]
; NOLSE-NEXT: cbnz w9, .LBB0_1
; NOLSE-NEXT: // %bb.2: // %atomicrmw.end
-; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $s0
+; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $q0
; NOLSE-NEXT: ret
;
; LSE-LABEL: test_atomicrmw_fmin_f16_seq_cst_align2:
@@ -40,7 +40,7 @@ define half @test_atomicrmw_fmin_f16_seq_cst_align2(ptr %ptr, half %value) #0 {
; LSE-NEXT: cmp w10, w8, uxth
; LSE-NEXT: b.ne .LBB0_1
; LSE-NEXT: // %bb.2: // %atomicrmw.end
-; LSE-NEXT: // kill: def $h0 killed $h0 killed $s0
+; LSE-NEXT: // kill: def $h0 killed $h0 killed $q0
; LSE-NEXT: ret
;
; SOFTFP-NOLSE-LABEL: test_atomicrmw_fmin_f16_seq_cst_align2:
@@ -108,7 +108,7 @@ define half @test_atomicrmw_fmin_f16_seq_cst_align4(ptr %ptr, half %value) #0 {
; NOLSE-NEXT: stlxrh w9, w8, [x0]
; NOLSE-NEXT: cbnz w9, .LBB1_1
; NOLSE-NEXT: // %bb.2: // %atomicrmw.end
-; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $s0
+; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $q0
; NOLSE-NEXT: ret
;
; LSE-LABEL: test_atomicrmw_fmin_f16_seq_cst_align4:
@@ -128,7 +128,7 @@ define half @test_atomicrmw_fmin_f16_seq_cst_align4(ptr %ptr, half %value) #0 {
; LSE-NEXT: cmp w10, w8, uxth
; LSE-NEXT: b.ne .LBB1_1
; LSE-NEXT: // %bb.2: // %atomicrmw.end
-; LSE-NEXT: // kill: def $h0 killed $h0 killed $s0
+; LSE-NEXT: // kill: def $h0 killed $h0 killed $q0
; LSE-NEXT: ret
;
; SOFTFP-NOLSE-LABEL: test_atomicrmw_fmin_f16_seq_cst_align4:
@@ -201,7 +201,7 @@ define bfloat @test_atomicrmw_fmin_bf16_seq_cst_align2(ptr %ptr, bfloat %value)
; NOLSE-NEXT: stlxrh w10, w9, [x0]
; NOLSE-NEXT: cbnz w10, .LBB2_1
; NOLSE-NEXT: // %bb.2: // %atomicrmw.end
-; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $d0
+; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $q0
; NOLSE-NEXT: ret
;
; LSE-LABEL: test_atomicrmw_fmin_bf16_seq_cst_align2:
@@ -228,7 +228,7 @@ define bfloat @test_atomicrmw_fmin_bf16_seq_cst_align2(ptr %ptr, bfloat %value)
; LSE-NEXT: cmp w11, w9, uxth
; LSE-NEXT: b.ne .LBB2_1
; LSE-NEXT: // %bb.2: // %atomicrmw.end
-; LSE-NEXT: // kill: def $h0 killed $h0 killed $d0
+; LSE-NEXT: // kill: def $h0 killed $h0 killed $q0
; LSE-NEXT: ret
;
; SOFTFP-NOLSE-LABEL: test_atomicrmw_fmin_bf16_seq_cst_align2:
@@ -295,7 +295,7 @@ define bfloat @test_atomicrmw_fmin_bf16_seq_cst_align4(ptr %ptr, bfloat %value)
; NOLSE-NEXT: stlxrh w10, w9, [x0]
; NOLSE-NEXT: cbnz w10, .LBB3_1
; NOLSE-NEXT: // %bb.2: // %atomicrmw.end
-; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $d0
+; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $q0
; NOLSE-NEXT: ret
;
; LSE-LABEL: test_atomicrmw_fmin_bf16_seq_cst_align4:
@@ -322,7 +322,7 @@ define bfloat @test_atomicrmw_fmin_bf16_seq_cst_align4(ptr %ptr, bfloat %value)
; LSE-NEXT: cmp w11, w9, uxth
; LSE-NEXT: b.ne .LBB3_1
; LSE-NEXT: // %bb.2: // %atomicrmw.end
-; LSE-NEXT: // kill: def $h0 killed $h0 killed $d0
+; LSE-NEXT: // kill: def $h0 killed $h0 killed $q0
; LSE-NEXT: ret
;
; SOFTFP-NOLSE-LABEL: test_atomicrmw_fmin_bf16_seq_cst_align4:
diff --git a/llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll b/llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll
index c73909603abb1..18f8cdc79c4a9 100644
--- a/llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll
+++ b/llvm/test/CodeGen/AArch64/atomicrmw-fsub.ll
@@ -18,7 +18,7 @@ define half @test_atomicrmw_fsub_f16_seq_cst_align2(ptr %ptr, half %value) #0 {
; NOLSE-NEXT: stlxrh w9, w8, [x0]
; NOLSE-NEXT: cbnz w9, .LBB0_1
; NOLSE-NEXT: // %bb.2: // %atomicrmw.end
-; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $s0
+; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $q0
; NOLSE-NEXT: ret
;
; LSE-LABEL: test_atomicrmw_fsub_f16_seq_cst_align2:
@@ -38,7 +38,7 @@ define half @test_atomicrmw_fsub_f16_seq_cst_align2(ptr %ptr, half %value) #0 {
; LSE-NEXT: cmp w10, w8, uxth
; LSE-NEXT: b.ne .LBB0_1
; LSE-NEXT: // %bb.2: // %atomicrmw.end
-; LSE-NEXT: // kill: def $h0 killed $h0 killed $s0
+; LSE-NEXT: // kill: def $h0 killed $h0 killed $q0
; LSE-NEXT: ret
;
; SOFTFP-NOLSE-LABEL: test_atomicrmw_fsub_f16_seq_cst_align2:
@@ -106,7 +106,7 @@ define half @test_atomicrmw_fsub_f16_seq_cst_align4(ptr %ptr, half %value) #0 {
; NOLSE-NEXT: stlxrh w9, w8, [x0]
; NOLSE-NEXT: cbnz w9, .LBB1_1
; NOLSE-NEXT: // %bb.2: // %atomicrmw.end
-; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $s0
+; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $q0
; NOLSE-NEXT: ret
;
; LSE-LABEL: test_atomicrmw_fsub_f16_seq_cst_align4:
@@ -126,7 +126,7 @@ define half @test_atomicrmw_fsub_f16_seq_cst_align4(ptr %ptr, half %value) #0 {
; LSE-NEXT: cmp w10, w8, uxth
; LSE-NEXT: b.ne .LBB1_1
; LSE-NEXT: // %bb.2: // %atomicrmw.end
-; LSE-NEXT: // kill: def $h0 killed $h0 killed $s0
+; LSE-NEXT: // kill: def $h0 killed $h0 killed $q0
; LSE-NEXT: ret
;
; SOFTFP-NOLSE-LABEL: test_atomicrmw_fsub_f16_seq_cst_align4:
@@ -199,7 +199,7 @@ define bfloat @test_atomicrmw_fsub_bf16_seq_cst_align2(ptr %ptr, bfloat %value)
; NOLSE-NEXT: stlxrh w10, w9, [x0]
; NOLSE-NEXT: cbnz w10, .LBB2_1
; NOLSE-NEXT: // %bb.2: // %atomicrmw.end
-; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $d0
+; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $q0
; NOLSE-NEXT: ret
;
; LSE-LABEL: test_atomicrmw_fsub_bf16_seq_cst_align2:
@@ -226,7 +226,7 @@ define bfloat @test_atomicrmw_fsub_bf16_seq_cst_align2(ptr %ptr, bfloat %value)
; LSE-NEXT: cmp w11, w9, uxth
; LSE-NEXT: b.ne .LBB2_1
; LSE-NEXT: // %bb.2: // %atomicrmw.end
-; LSE-NEXT: // kill: def $h0 killed $h0 killed $d0
+; LSE-NEXT: // kill: def $h0 killed $h0 killed $q0
; LSE-NEXT: ret
;
; SOFTFP-NOLSE-LABEL: test_atomicrmw_fsub_bf16_seq_cst_align2:
@@ -293,7 +293,7 @@ define bfloat @test_atomicrmw_fsub_bf16_seq_cst_align4(ptr %ptr, bfloat %value)
; NOLSE-NEXT: stlxrh w10, w9, [x0]
; NOLSE-NEXT: cbnz w10, .LBB3_1
; NOLSE-NEXT: // %bb.2: // %atomicrmw.end
-; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $d0
+; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $q0
; NOLSE-NEXT: ret
;
; LSE-LABEL: test_atomicrmw_fsub_bf16_seq_cst_align4:
@@ -320,7 +320,7 @@ define bfloat @test_atomicrmw_fsub_bf16_seq_cst_align4(ptr %ptr, bfloat %value)
; LSE-NEXT: cmp w11, w9, uxth
; LSE-NEXT: b.ne .LBB3_1
; LSE-NEXT: // %bb.2: // %atomicrmw.end
-; LSE-NEXT: // kill: def $h0 killed $h0 killed $d0
+; LSE-NEXT: // kill: def $h0 killed $h0 killed $q0
; LSE-NEXT: ret
;
; SOFTFP-NOLSE-LABEL: test_atomicrmw_fsub_bf16_seq_cst_align4:
diff --git a/llvm/test/CodeGen/AArch64/atomicrmw-xchg-fp.ll b/llvm/test/CodeGen/AArch64/atomicrmw-xchg-fp.ll
index 0e728cdb895ed..3741d8b84d7bf 100644
--- a/llvm/test/CodeGen/AArch64/atomicrmw-xchg-fp.ll
+++ b/llvm/test/CodeGen/AArch64/atomicrmw-xchg-fp.ll
@@ -14,7 +14,7 @@ define half @test_rmw_xchg_f16(ptr %dst, half %new) {
; NOLSE-NEXT: cbnz w10, .LBB0_1
; NOLSE-NEXT: // %bb.2: // %atomicrmw.end
; NOLSE-NEXT: fmov s0, w8
-; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $s0
+; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $q0
; NOLSE-NEXT: ret
;
; LSE-LABEL: test_rmw_xchg_f16:
@@ -23,7 +23,7 @@ define half @test_rmw_xchg_f16(ptr %dst, half %new) {
; LSE-NEXT: fmov w8, s0
; LSE-NEXT: swpalh w8, w8, [x0]
; LSE-NEXT: fmov s0, w8
-; LSE-NEXT: // kill: def $h0 killed $h0 killed $s0
+; LSE-NEXT: // kill: def $h0 killed $h0 killed $q0
; LSE-NEXT: ret
%res = atomicrmw xchg ptr %dst, half %new seq_cst
ret half %res
diff --git a/llvm/test/CodeGen/AArch64/bf16-instructions.ll b/llvm/test/CodeGen/AArch64/bf16-instructions.ll
index 240ac524b90c2..27d07e6c3c6d3 100644
--- a/llvm/test/CodeGen/AArch64/bf16-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/bf16-instructions.ll
@@ -1174,11 +1174,29 @@ define i16 @test_bitcast_bfloattoi16(bfloat %a) #0 {
}
define bfloat @test_bitcast_i16tobfloat(i16 %a) #0 {
-; CHECK-LABEL: test_bitcast_i16tobfloat:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fmov s0, w0
-; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s0
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: test_bitcast_i16tobfloat:
+; CHECK-CVT-SD: // %bb.0:
+; CHECK-CVT-SD-NEXT: fmov s0, w0
+; CHECK-CVT-SD-NEXT: // kill: def $h0 killed $h0 killed $q0
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-BF16-SD-LABEL: test_bitcast_i16tobfloat:
+; CHECK-BF16-SD: // %bb.0:
+; CHECK-BF16-SD-NEXT: fmov s0, w0
+; CHECK-BF16-SD-NEXT: // kill: def $h0 killed $h0 killed $q0
+; CHECK-BF16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: test_bitcast_i16tobfloat:
+; CHECK-CVT-GI: // %bb.0:
+; CHECK-CVT-GI-NEXT: fmov s0, w0
+; CHECK-CVT-GI-NEXT: // kill: def $h0 killed $h0 killed $s0
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-BF16-GI-LABEL: test_bitcast_i16tobfloat:
+; CHECK-BF16-GI: // %bb.0:
+; CHECK-BF16-GI-NEXT: fmov s0, w0
+; CHECK-BF16-GI-NEXT: // kill: def $h0 killed $h0 killed $s0
+; CHECK-BF16-GI-NEXT: ret
%r = bitcast i16 %a to bfloat
ret bfloat %r
}
diff --git a/llvm/test/CodeGen/AArch64/f16-instructions.ll b/llvm/test/CodeGen/AArch64/f16-instructions.ll
index f6d701b518699..7ffe5ae10f838 100644
--- a/llvm/test/CodeGen/AArch64/f16-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/f16-instructions.ll
@@ -1093,11 +1093,29 @@ define i16 @test_bitcast_halftoi16(half %a) #0 {
}
define half @test_bitcast_i16tohalf(i16 %a) #0 {
-; CHECK-LABEL: test_bitcast_i16tohalf:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fmov s0, w0
-; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s0
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: test_bitcast_i16tohalf:
+; CHECK-CVT-SD: // %bb.0:
+; CHECK-CVT-SD-NEXT: fmov s0, w0
+; CHECK-CVT-SD-NEXT: // kill: def $h0 killed $h0 killed $q0
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: test_bitcast_i16tohalf:
+; CHECK-FP16-SD: // %bb.0:
+; CHECK-FP16-SD-NEXT: fmov s0, w0
+; CHECK-FP16-SD-NEXT: // kill: def $h0 killed $h0 killed $q0
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: test_bitcast_i16tohalf:
+; CHECK-CVT-GI: // %bb.0:
+; CHECK-CVT-GI-NEXT: fmov s0, w0
+; CHECK-CVT-GI-NEXT: // kill: def $h0 killed $h0 killed $s0
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: test_bitcast_i16tohalf:
+; CHECK-FP16-GI: // %bb.0:
+; CHECK-FP16-GI-NEXT: fmov s0, w0
+; CHECK-FP16-GI-NEXT: // kill: def $h0 killed $h0 killed $s0
+; CHECK-FP16-GI-NEXT: ret
%r = bitcast i16 %a to half
ret half %r
}
diff --git a/llvm/test/CodeGen/AArch64/fp16-vector-shuffle.ll b/llvm/test/CodeGen/AArch64/fp16-vector-shuffle.ll
index 05422d3cc6051..fb672a0eee2eb 100644
--- a/llvm/test/CodeGen/AArch64/fp16-vector-shuffle.ll
+++ b/llvm/test/CodeGen/AArch64/fp16-vector-shuffle.ll
@@ -348,7 +348,6 @@ define half @get_lane_64(<4 x half> %a) #0 {
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov h0, v0.h[2]
-; CHECK-NEXT: // kill: def $h0 killed $h0 killed $q0
; CHECK-NEXT: ret
entry:
%0 = bitcast <4 x half> %a to <4 x i16>
@@ -362,7 +361,6 @@ define half @get_lane_128(<8 x half> %a) #0 {
; CHECK-LABEL: get_lane_128:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov h0, v0.h[2]
-; CHECK-NEXT: // kill: def $h0 killed $h0 killed $q0
; CHECK-NEXT: ret
entry:
%0 = bitcast <8 x half> %a to <8 x i16>
diff --git a/llvm/test/CodeGen/AArch64/half.ll b/llvm/test/CodeGen/AArch64/half.ll
index bb802033e05fc..74a487727d25d 100644
--- a/llvm/test/CodeGen/AArch64/half.ll
+++ b/llvm/test/CodeGen/AArch64/half.ll
@@ -46,7 +46,7 @@ define half @test_reg_bitcast_to_half(i16 %in) {
; CHECK-LABEL: test_reg_bitcast_to_half:
; CHECK: // %bb.0:
; CHECK-NEXT: fmov s0, w0
-; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s0
+; CHECK-NEXT: // kill: def $h0 killed $h0 killed $q0
; CHECK-NEXT: ret
%val = bitcast i16 %in to half
ret half %val
diff --git a/llvm/test/CodeGen/AArch64/load-zext-bitcast.ll b/llvm/test/CodeGen/AArch64/load-zext-bitcast.ll
index 628506b6d55ef..992cc82f9f3b0 100644
--- a/llvm/test/CodeGen/AArch64/load-zext-bitcast.ll
+++ b/llvm/test/CodeGen/AArch64/load-zext-bitcast.ll
@@ -71,7 +71,7 @@ define half @load_u16_from_u8(ptr %n){
; CHECK-LABEL: load_u16_from_u8:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr b0, [x0]
-; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s0
+; CHECK-NEXT: // kill: def $h0 killed $h0 killed $q0
; CHECK-NEXT: ret
entry:
%0 = load i8, ptr %n, align 1
@@ -150,7 +150,7 @@ define half @load_u16_from_u8_off1(ptr %n){
; CHECK-LABEL: load_u16_from_u8_off1:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr b0, [x0, #1]
-; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s0
+; CHECK-NEXT: // kill: def $h0 killed $h0 killed $q0
; CHECK-NEXT: ret
entry:
%p = getelementptr i8, ptr %n, i64 1
@@ -231,7 +231,7 @@ define half @load_u16_from_u8_off2(ptr %n){
; CHECK-LABEL: load_u16_from_u8_off2:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr b0, [x0, #2]
-; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s0
+; CHECK-NEXT: // kill: def $h0 killed $h0 killed $q0
; CHECK-NEXT: ret
entry:
%p = getelementptr i8, ptr %n, i64 2
@@ -312,7 +312,7 @@ define half @load_u16_from_u8_off255(ptr %n){
; CHECK-LABEL: load_u16_from_u8_off255:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr b0, [x0, #255]
-; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s0
+; CHECK-NEXT: // kill: def $h0 killed $h0 killed $q0
; CHECK-NEXT: ret
entry:
%p = getelementptr i8, ptr %n, i64 255
@@ -392,7 +392,7 @@ define half @load_u16_from_u8_off256(ptr %n){
; CHECK-LABEL: load_u16_from_u8_off256:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr b0, [x0, #256]
-; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s0
+; CHECK-NEXT: // kill: def $h0 killed $h0 killed $q0
; CHECK-NEXT: ret
entry:
%p = getelementptr i8, ptr %n, i64 256
@@ -473,7 +473,7 @@ define half @load_u16_from_u8_offn(ptr %n){
; CHECK-LABEL: load_u16_from_u8_offn:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr b0, [x0, #4095]
-; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s0
+; CHECK-NEXT: // kill: def $h0 killed $h0 killed $q0
; CHECK-NEXT: ret
entry:
%p = getelementptr i8, ptr %n, i64 4095
@@ -559,7 +559,7 @@ define half @load_u16_from_u8_offnp1(ptr %n){
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov w8, #4096 // =0x1000
; CHECK-NEXT: ldr b0, [x0, x8]
-; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s0
+; CHECK-NEXT: // kill: def $h0 killed $h0 killed $q0
; CHECK-NEXT: ret
entry:
%p = getelementptr i8, ptr %n, i64 4096
diff --git a/llvm/test/CodeGen/AArch64/neon-extractbitcast-mir.ll b/llvm/test/CodeGen/AArch64/neon-extractbitcast-mir.ll
index 7e55a28d04df8..d9970c91019cc 100644
--- a/llvm/test/CodeGen/AArch64/neon-extractbitcast-mir.ll
+++ b/llvm/test/CodeGen/AArch64/neon-extractbitcast-mir.ll
@@ -7,12 +7,11 @@ define half @test_vext_v8i16_0(<8 x i16> %a) {
; CHECK-NEXT: liveins: $q0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]].ssub
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr16 = COPY [[COPY1]].hsub
- ; CHECK-NEXT: $h0 = COPY [[COPY2]]
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY [[COPY]].hsub
+ ; CHECK-NEXT: $h0 = COPY [[COPY1]]
; CHECK-NEXT: RET_ReallyLR implicit $h0
entry:
%b = extractelement <8 x i16> %a, i32 0
%c = bitcast i16 %b to half
ret half %c
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/AArch64/neon-insextbitcast.ll b/llvm/test/CodeGen/AArch64/neon-insextbitcast.ll
index d9cdbc2f92aca..8d13de3ff7c81 100644
--- a/llvm/test/CodeGen/AArch64/neon-insextbitcast.ll
+++ b/llvm/test/CodeGen/AArch64/neon-insextbitcast.ll
@@ -93,7 +93,6 @@ define half @test_vext_v8i16(<8 x i16> %a) {
; CHECK-LABEL: test_vext_v8i16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov h0, v0.h[5]
-; CHECK-NEXT: // kill: def $h0 killed $h0 killed $q0
; CHECK-NEXT: ret
entry:
%b = extractelement <8 x i16> %a, i32 5
@@ -117,7 +116,6 @@ define half @test_vext_v4i16(<4 x i16> %a) {
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov h0, v0.h[1]
-; CHECK-NEXT: // kill: def $h0 killed $h0 killed $q0
; CHECK-NEXT: ret
entry:
%b = extractelement <4 x i16> %a, i32 1
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