[llvm] AMDGPU/GlobalISel: Implement RegBankLegalizeRules for amdgcn_log, amdgcn_rcp, and amdgcn_sqrt (PR #195099)

[Petar Avramovic via llvm-commits]

petar-avramovic wrote:

## RegBankLegalize coverage check

The PR adds `amdgcn_rcp` and `amdgcn_log` to `addRulesForIOpcs`. Each `.Div()`/`.Uni()` call is one rule. Probed by removing each rule and checking whether any `new-reg-bank-select` test fails.

| Opcode | Rule | Test file | Function | Status |
|--------|------|-----------|----------|--------|
| `amdgcn_rcp` | Div S16 | — | — | ❌ MISSING |
| `amdgcn_rcp` | Uni S16 hasPST | — | — | ❌ MISSING |
| `amdgcn_rcp` | Uni S16 !hasPST | — | — | ❌ MISSING |
| `amdgcn_rcp` | Div S32 | — | — | ❌ MISSING |
| `amdgcn_rcp` | Uni S32 hasPST | — | — | ❌ MISSING |
| `amdgcn_rcp` | Uni S32 !hasPST | — | — | ❌ MISSING |
| `amdgcn_rcp` | Div S64 | `llvm.amdgcn.sqrt.ll` | `v_sqrt_f64` | ✅ (via shared block with sqrt) |
| `amdgcn_rcp` | Uni S64 | `llvm.amdgcn.sqrt.ll` | `s_sqrt_f64` | ✅ (via shared block with sqrt) |
| `amdgcn_log` | Div S16 | — | — | ❌ MISSING |
| `amdgcn_log` | Uni S16 hasPST | `pseudo-scalar-transcendental.ll` | `v_s_amdgcn_log_f16` | ✅ |
| `amdgcn_log` | Uni S16 !hasPST | — | — | ❌ MISSING |
| `amdgcn_log` | Div S32 | — | — | ❌ MISSING |
| `amdgcn_log` | Uni S32 hasPST | `pseudo-scalar-transcendental.ll` | `v_s_log_f32` | ✅ |
| `amdgcn_log` | Uni S32 !hasPST | — | — | ❌ MISSING |

### Suggested fix

**For `amdgcn_log`:** `llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.ll` already has divergent functions `v_log_f32` and `v_log_f16` under `global-isel=1 -mcpu=fiji`. Adding a `-new-reg-bank-select` RUN line would cover Div S16 and Div S32. The Uni !hasPST (fiji, SGPR arg) cases would need additional functions where the argument is uniform.

**For `amdgcn_rcp`:** No existing file has divergent rcp functions under GISel with `new-reg-bank-select`. New functions are needed in `llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll` (or a dedicated file):

```llvm
; Divergent rcp — hits Div S16, Div S32
define void @v_rcp_f16(half %src, ptr addrspace(1) %out) {
  %result = call fast half @llvm.amdgcn.rcp.f16(half %src)
  store half %result, ptr addrspace(1) %out
  ret void
}

define void @v_rcp_f32(float %src, ptr addrspace(1) %out) {
  %result = call fast float @llvm.amdgcn.rcp.f32(float %src)
  store float %result, ptr addrspace(1) %out
  ret void
}

; Uniform-in-vgpr rcp (!hasPST, e.g. fiji) — hits Uni S16 !hasPST, Uni S32 !hasPST
define amdgpu_cs half @s_rcp_f16_nopst(half inreg %src) {
  %result = call fast half @llvm.amdgcn.rcp.f16(half %src)
  ret half %result
}

define amdgpu_cs float @s_rcp_f32_nopst(float inreg %src) {
  %result = call fast float @llvm.amdgcn.rcp.f32(float %src)
  ret float %result
}
```

Run `update_llc_test_checks.py` to generate check lines after adding the functions.

> *Automated check — not a human review. Generated by Claude (claude.ai).*

https://github.com/llvm/llvm-project/pull/195099