[llvm] [AMDGPU] Disable dpp src1 sgpr on gfx11 (PR #164241)

[via llvm-commits]

================
@@ -307,10 +307,12 @@ MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI,
     if (Src1) {
       assert(AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::src1) &&
              "dpp version of instruction missing src1");
-      // If subtarget does not support SGPRs for src1 operand then the
-      // requirements are the same as for src0. We check src0 instead because
-      // pseudos are shared between subtargets and allow SGPR for src1 on all.
----------------
LU-JOHN wrote:

Sorry, I didn't mean to keep the comment exactly.  Something like:

```
// If subtarget does not support SGPRs for src1 operand then the
// register requirements are the same as for src0 and src1.
```

This property between two reg operands can't be checked in isLegalRegOperand.  If this property isn't true because of instructions like V_LSHRREV_B64_e64_dpp, then we should also remove the following code and add a test for it:

```
      if (!ST->hasDPPSrc1SGPR()) {
        assert(TII->getOpSize(*DPPInst, Src0Idx) ==
                   TII->getOpSize(*DPPInst, NumOperands) &&
               "Src0 and Src1 operands should have the same size");
      }
```

https://github.com/llvm/llvm-project/pull/164241