[llvm] [ARM] Port shouldBeAdjustedToZero to ARM (PR #195968)
via llvm-commits
llvm-commits at lists.llvm.org
Thu May 7 05:11:19 PDT 2026
https://github.com/LumioseSil updated https://github.com/llvm/llvm-project/pull/195968
>From d5a0958afe0c375da0977e523e1b5a6abb963aa2 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Tue, 5 May 2026 17:28:06 -0400
Subject: [PATCH] [ARM] Port shouldBeAdjustedToZero to ARM
---
llvm/lib/Target/ARM/ARMISelLowering.cpp | 109 +++++++++----
.../CodeGen/ARM/arm-shrink-wrapping-linux.ll | 18 +--
llvm/test/CodeGen/ARM/consthoist-icmpimm.ll | 144 +++++++++---------
llvm/test/CodeGen/ARM/dsp-loop-indexing.ll | 2 +-
llvm/test/CodeGen/ARM/select-constant-xor.ll | 14 +-
llvm/test/CodeGen/ARM/sub-cmp-peephole.ll | 5 +-
llvm/test/CodeGen/ARM/vsel.ll | 16 +-
llvm/test/CodeGen/Thumb2/mve-memtp-loop.ll | 6 +-
.../CodeGen/Thumb2/mve-vselect-constants.ll | 8 +-
.../CodeGen/Thumb2/pacbti-m-outliner-4.ll | 4 +-
10 files changed, 184 insertions(+), 142 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index cbff40f697b9b..9af529410c390 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -4452,6 +4452,28 @@ static bool isFloatingPointZero(SDValue Op) {
return false;
}
+static bool isLegalArithImmed(unsigned Imm, const ARMSubtarget *Subtarget) {
+ if (!Subtarget->isThumb())
+ return ARM_AM::getSOImmVal(Imm) != -1;
+ if (Subtarget->isThumb2())
+ return ARM_AM::getT2SOImmVal(Imm) != -1;
+ // Thumb1 only has 8-bit unsigned immediate.
+ return Imm <= 255;
+}
+
+bool isLegalCmpImmed(const APInt &C, const ARMSubtarget *Subtarget) {
+ int64_t Imm = C.getSExtValue();
+ // Thumb2 and ARM modes can use cmn for negative immediates.
+ if (!Subtarget->isThumb())
+ return ARM_AM::getSOImmVal((uint32_t)Imm) != -1 ||
+ ARM_AM::getSOImmVal(-(uint32_t)Imm) != -1;
+ if (Subtarget->isThumb2())
+ return ARM_AM::getT2SOImmVal((uint32_t)Imm) != -1 ||
+ ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1;
+ // Thumb1 doesn't have cmn, and only 8-bit immediates.
+ return Imm >= 0 && Imm <= 255;
+}
+
static bool isSafeSignedCMN(SDValue Op, SelectionDAG &DAG) {
// 0 - INT_MIN sign wraps, so no signed wrap means cmn is safe.
if (Op->getFlags().hasNoSignedWrap())
@@ -4475,49 +4497,81 @@ static bool isCMN(SDValue Op, ISD::CondCode CC, SelectionDAG &DAG) {
(isSignedIntSetCC(CC) && isSafeSignedCMN(Op, DAG)));
}
+// Adjust compares against -1 to a compare against 0 in signed cases.
+// This specifically enables condition forms that map to sign checks (mi/pl).
+static bool shouldBeAdjustedToZero(SDValue LHS, const APInt &C,
+ ISD::CondCode &CC) {
+ if (!LHS.hasOneUse())
+ return false;
+ if (C.isAllOnes() && (CC == ISD::SETLE || CC == ISD::SETGT)) {
+ CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
+ return true;
+ }
+ return false;
+}
+
/// Returns appropriate ARM CMP (cmp) and corresponding condition code for
/// the given operands.
SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
SDValue &ARMcc, SelectionDAG &DAG,
const SDLoc &dl) const {
if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
- unsigned C = RHSC->getZExtValue();
- if (!isLegalICmpImmediate((int32_t)C)) {
+ APInt CInt = RHSC->getAPIntValue();
+ if (shouldBeAdjustedToZero(LHS, CInt, CC)) {
+ // Adjust the constant to zero.
+ // CC has already been adjusted.
+ RHS = DAG.getConstant(0, dl, MVT::i32);
+ } else if (!isLegalCmpImmed(CInt, Subtarget)) {
// Constant does not fit, try adjusting it by one.
switch (CC) {
- default: break;
+ default:
+ break;
case ISD::SETLT:
case ISD::SETGE:
- if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
- CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
- RHS = DAG.getConstant(C - 1, dl, MVT::i32);
+ if (!CInt.isMinSignedValue()) {
+ APInt CMinusOne = CInt - 1;
+ if (isLegalCmpImmed(CMinusOne, Subtarget)) {
+ CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
+ RHS = DAG.getConstant(CMinusOne, dl, MVT::i32);
+ }
}
break;
case ISD::SETULT:
- case ISD::SETUGE:
- if (C != 0 && isLegalICmpImmediate(C-1)) {
+ case ISD::SETUGE: {
+ // C is not 0 because it is a legal immediate.
+ assert(!CInt.isZero() && "C should not be zero here");
+ APInt CMinusOne = CInt - 1;
+ if (isLegalCmpImmed(CMinusOne, Subtarget)) {
CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
- RHS = DAG.getConstant(C - 1, dl, MVT::i32);
+ RHS = DAG.getConstant(CMinusOne, dl, MVT::i32);
}
- break;
+ } break;
case ISD::SETLE:
case ISD::SETGT:
- if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
- CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
- RHS = DAG.getConstant(C + 1, dl, MVT::i32);
+ if (!CInt.isMaxSignedValue()) {
+ APInt CPlusOne = CInt + 1;
+ if (isLegalCmpImmed(CPlusOne, Subtarget)) {
+ CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
+ RHS = DAG.getConstant(CPlusOne, dl, MVT::i32);
+ }
}
break;
case ISD::SETULE:
case ISD::SETUGT:
- if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
- CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
- RHS = DAG.getConstant(C + 1, dl, MVT::i32);
+ if (!CInt.isAllOnes()) {
+ APInt CPlusOne = CInt + 1;
+ if (isLegalCmpImmed(CPlusOne, Subtarget)) {
+ CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
+ RHS = DAG.getConstant(CPlusOne, dl, MVT::i32);
+ }
}
break;
}
}
- } else if ((ARM_AM::getShiftOpcForNode(LHS.getOpcode()) != ARM_AM::no_shift) &&
- (ARM_AM::getShiftOpcForNode(RHS.getOpcode()) == ARM_AM::no_shift)) {
+ } else if ((ARM_AM::getShiftOpcForNode(LHS.getOpcode()) !=
+ ARM_AM::no_shift) &&
+ (ARM_AM::getShiftOpcForNode(RHS.getOpcode()) ==
+ ARM_AM::no_shift)) {
// In ARM and Thumb-2, the compare instructions can shift their second
// operand.
CC = ISD::getSetCCSwappedOperands(CC);
@@ -13071,7 +13125,7 @@ static SDValue PerformAddeSubeCombine(SDNode *N,
SelectionDAG &DAG = DCI.DAG;
SDValue RHS = N->getOperand(1);
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
- int64_t imm = C->getSExtValue();
+ int32_t imm = C->getSExtValue();
if (imm < 0) {
SDLoc DL(N);
@@ -19687,6 +19741,7 @@ bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const {
uint64_t AbsImm = AbsoluteValue(Imm);
if (!Subtarget->isThumb())
return ARM_AM::getSOImmVal(AbsImm) != -1;
+
if (Subtarget->isThumb2())
return ARM_AM::getT2SOImmVal(AbsImm) != -1;
// Thumb1 only has 8-bit unsigned immediate.
@@ -20164,16 +20219,6 @@ void ARMTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
}
}
-static bool isLegalLogicalImmediate(unsigned Imm,
- const ARMSubtarget *Subtarget) {
- if (!Subtarget->isThumb())
- return ARM_AM::getSOImmVal(Imm) != -1;
- if (Subtarget->isThumb2())
- return ARM_AM::getT2SOImmVal(Imm) != -1;
- // Thumb1 only has 8-bit unsigned immediate.
- return Imm <= 255;
-}
-
/// Refine i32 AND/OR/XOR with a constant RHS using demanded bits: replace the
/// immediate with an equivalent constant that ARM/Thumb can encode as a
/// logical immediate (or that selects better lowering), without changing the
@@ -20239,7 +20284,7 @@ static bool optimizeLogicalImm(SDValue Op, unsigned Imm,
}
// Don't optimize if it is legal.
- if (isLegalLogicalImmediate(Imm, Subtarget))
+ if (isLegalArithImmed(Imm, Subtarget))
return false;
// FIXME: Check for BIC being legal causes infinite loop due to target
@@ -20247,7 +20292,7 @@ static bool optimizeLogicalImm(SDValue Op, unsigned Imm,
// Prefer strict shrink when ShrunkImm encodes for this target, before
// complement expansion.
- if (isLegalLogicalImmediate(ShrunkImm, Subtarget)) {
+ if (isLegalArithImmed(ShrunkImm, Subtarget)) {
++NumOptimizedImms;
return UseImm(ShrunkImm);
}
@@ -20264,7 +20309,7 @@ static bool optimizeLogicalImm(SDValue Op, unsigned Imm,
// FIXME: The check for v6 is because this interferes with some ubfx
// optimizations.
- if (Opc == ISD::AND && isLegalLogicalImmediate(~ExpandedImm, Subtarget) &&
+ if (Opc == ISD::AND && isLegalArithImmed(~ExpandedImm, Subtarget) &&
!Subtarget->hasV6Ops()) {
++NumOptimizedImms;
return UseImm(ExpandedImm);
diff --git a/llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll b/llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll
index b92f03d43bb4c..2889d1c33d10b 100644
--- a/llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll
+++ b/llvm/test/CodeGen/ARM/arm-shrink-wrapping-linux.ll
@@ -19,10 +19,9 @@ define fastcc ptr @wrongUseOfPostDominate(ptr readonly %s, i32 %off, ptr readnon
; ENABLE: @ %bb.0: @ %entry
; ENABLE-NEXT: .save {r11, lr}
; ENABLE-NEXT: push {r11, lr}
-; ENABLE-NEXT: cmn r1, #1
-; ENABLE-NEXT: ble .LBB0_7
-; ENABLE-NEXT: @ %bb.1: @ %while.cond.preheader
; ENABLE-NEXT: cmp r1, #0
+; ENABLE-NEXT: bmi .LBB0_7
+; ENABLE-NEXT: @ %bb.1: @ %while.cond.preheader
; ENABLE-NEXT: beq .LBB0_6
; ENABLE-NEXT: @ %bb.2: @ %while.cond.preheader
; ENABLE-NEXT: cmp r0, r2
@@ -74,8 +73,8 @@ define fastcc ptr @wrongUseOfPostDominate(ptr readonly %s, i32 %off, ptr readnon
; ENABLE-NEXT: bls .LBB0_7
; ENABLE-NEXT: @ %bb.12: @ %land.rhs14.preheader
; ENABLE-NEXT: @ in Loop: Header=BB0_7 Depth=1
-; ENABLE-NEXT: cmn lr, #1
-; ENABLE-NEXT: bgt .LBB0_7
+; ENABLE-NEXT: cmp lr, #0
+; ENABLE-NEXT: bpl .LBB0_7
; ENABLE-NEXT: @ %bb.13: @ %land.rhs14.preheader
; ENABLE-NEXT: @ in Loop: Header=BB0_7 Depth=1
; ENABLE-NEXT: cmp r12, #191
@@ -109,10 +108,9 @@ define fastcc ptr @wrongUseOfPostDominate(ptr readonly %s, i32 %off, ptr readnon
; DISABLE: @ %bb.0: @ %entry
; DISABLE-NEXT: .save {r11, lr}
; DISABLE-NEXT: push {r11, lr}
-; DISABLE-NEXT: cmn r1, #1
-; DISABLE-NEXT: ble .LBB0_7
-; DISABLE-NEXT: @ %bb.1: @ %while.cond.preheader
; DISABLE-NEXT: cmp r1, #0
+; DISABLE-NEXT: bmi .LBB0_7
+; DISABLE-NEXT: @ %bb.1: @ %while.cond.preheader
; DISABLE-NEXT: beq .LBB0_6
; DISABLE-NEXT: @ %bb.2: @ %while.cond.preheader
; DISABLE-NEXT: cmp r0, r2
@@ -164,8 +162,8 @@ define fastcc ptr @wrongUseOfPostDominate(ptr readonly %s, i32 %off, ptr readnon
; DISABLE-NEXT: bls .LBB0_7
; DISABLE-NEXT: @ %bb.12: @ %land.rhs14.preheader
; DISABLE-NEXT: @ in Loop: Header=BB0_7 Depth=1
-; DISABLE-NEXT: cmn lr, #1
-; DISABLE-NEXT: bgt .LBB0_7
+; DISABLE-NEXT: cmp lr, #0
+; DISABLE-NEXT: bpl .LBB0_7
; DISABLE-NEXT: @ %bb.13: @ %land.rhs14.preheader
; DISABLE-NEXT: @ in Loop: Header=BB0_7 Depth=1
; DISABLE-NEXT: cmp r12, #191
diff --git a/llvm/test/CodeGen/ARM/consthoist-icmpimm.ll b/llvm/test/CodeGen/ARM/consthoist-icmpimm.ll
index 16b7403bdb932..2f9a8ed997feb 100644
--- a/llvm/test/CodeGen/ARM/consthoist-icmpimm.ll
+++ b/llvm/test/CodeGen/ARM/consthoist-icmpimm.ll
@@ -44,19 +44,19 @@ define i32 @icmp64_sge_0(i64 %x, i64 %y, i32 %a, i32 %b, i1 %c) {
; CHECKV7M-NEXT: ldrd r2, r0, [sp]
; CHECKV7M-NEXT: beq .LBB0_2
; CHECKV7M-NEXT: @ %bb.1: @ %then
-; CHECKV7M-NEXT: cmp.w r3, #-1
+; CHECKV7M-NEXT: cmp r3, #0
; CHECKV7M-NEXT: mov r3, r0
-; CHECKV7M-NEXT: it gt
-; CHECKV7M-NEXT: movgt r3, r2
-; CHECKV7M-NEXT: cmp.w r1, #-1
-; CHECKV7M-NEXT: it gt
-; CHECKV7M-NEXT: movgt r0, r2
+; CHECKV7M-NEXT: it ge
+; CHECKV7M-NEXT: movge r3, r2
+; CHECKV7M-NEXT: cmp r1, #0
+; CHECKV7M-NEXT: it ge
+; CHECKV7M-NEXT: movge r0, r2
; CHECKV7M-NEXT: add r0, r3
; CHECKV7M-NEXT: bx lr
; CHECKV7M-NEXT: .LBB0_2: @ %else
-; CHECKV7M-NEXT: cmp.w r1, #-1
-; CHECKV7M-NEXT: it gt
-; CHECKV7M-NEXT: movgt r0, r2
+; CHECKV7M-NEXT: cmp r1, #0
+; CHECKV7M-NEXT: it ge
+; CHECKV7M-NEXT: movge r0, r2
; CHECKV7M-NEXT: bx lr
;
; CHECKV7A-LABEL: icmp64_sge_0:
@@ -66,19 +66,19 @@ define i32 @icmp64_sge_0(i64 %x, i64 %y, i32 %a, i32 %b, i1 %c) {
; CHECKV7A-NEXT: lsls r2, r2, #31
; CHECKV7A-NEXT: beq .LBB0_2
; CHECKV7A-NEXT: @ %bb.1: @ %then
-; CHECKV7A-NEXT: cmp.w r3, #-1
+; CHECKV7A-NEXT: cmp r3, #0
; CHECKV7A-NEXT: mov r2, r0
-; CHECKV7A-NEXT: it gt
-; CHECKV7A-NEXT: movgt r2, r12
-; CHECKV7A-NEXT: cmp.w r1, #-1
-; CHECKV7A-NEXT: it gt
-; CHECKV7A-NEXT: movgt r0, r12
+; CHECKV7A-NEXT: it ge
+; CHECKV7A-NEXT: movge r2, r12
+; CHECKV7A-NEXT: cmp r1, #0
+; CHECKV7A-NEXT: it ge
+; CHECKV7A-NEXT: movge r0, r12
; CHECKV7A-NEXT: add r0, r2
; CHECKV7A-NEXT: bx lr
; CHECKV7A-NEXT: .LBB0_2: @ %else
-; CHECKV7A-NEXT: cmp.w r1, #-1
-; CHECKV7A-NEXT: it gt
-; CHECKV7A-NEXT: movgt r0, r12
+; CHECKV7A-NEXT: cmp r1, #0
+; CHECKV7A-NEXT: it ge
+; CHECKV7A-NEXT: movge r0, r12
; CHECKV7A-NEXT: bx lr
br i1 %c, label %then, label %else
then:
@@ -135,19 +135,19 @@ define i32 @icmp64_sgt_m1(i64 %x, i64 %y, i32 %a, i32 %b, i1 %c) {
; CHECKV7M-NEXT: ldrd r2, r0, [sp]
; CHECKV7M-NEXT: beq .LBB1_2
; CHECKV7M-NEXT: @ %bb.1: @ %then
-; CHECKV7M-NEXT: cmp.w r3, #-1
+; CHECKV7M-NEXT: cmp r3, #0
; CHECKV7M-NEXT: mov r3, r0
-; CHECKV7M-NEXT: it gt
-; CHECKV7M-NEXT: movgt r3, r2
-; CHECKV7M-NEXT: cmp.w r1, #-1
-; CHECKV7M-NEXT: it gt
-; CHECKV7M-NEXT: movgt r0, r2
+; CHECKV7M-NEXT: it ge
+; CHECKV7M-NEXT: movge r3, r2
+; CHECKV7M-NEXT: cmp r1, #0
+; CHECKV7M-NEXT: it ge
+; CHECKV7M-NEXT: movge r0, r2
; CHECKV7M-NEXT: add r0, r3
; CHECKV7M-NEXT: bx lr
; CHECKV7M-NEXT: .LBB1_2: @ %else
-; CHECKV7M-NEXT: cmp.w r3, #-1
-; CHECKV7M-NEXT: it gt
-; CHECKV7M-NEXT: movgt r0, r2
+; CHECKV7M-NEXT: cmp r3, #0
+; CHECKV7M-NEXT: it ge
+; CHECKV7M-NEXT: movge r0, r2
; CHECKV7M-NEXT: bx lr
;
; CHECKV7A-LABEL: icmp64_sgt_m1:
@@ -157,19 +157,19 @@ define i32 @icmp64_sgt_m1(i64 %x, i64 %y, i32 %a, i32 %b, i1 %c) {
; CHECKV7A-NEXT: lsls r2, r2, #31
; CHECKV7A-NEXT: beq .LBB1_2
; CHECKV7A-NEXT: @ %bb.1: @ %then
-; CHECKV7A-NEXT: cmp.w r3, #-1
+; CHECKV7A-NEXT: cmp r3, #0
; CHECKV7A-NEXT: mov r2, r0
-; CHECKV7A-NEXT: it gt
-; CHECKV7A-NEXT: movgt r2, r12
-; CHECKV7A-NEXT: cmp.w r1, #-1
-; CHECKV7A-NEXT: it gt
-; CHECKV7A-NEXT: movgt r0, r12
+; CHECKV7A-NEXT: it ge
+; CHECKV7A-NEXT: movge r2, r12
+; CHECKV7A-NEXT: cmp r1, #0
+; CHECKV7A-NEXT: it ge
+; CHECKV7A-NEXT: movge r0, r12
; CHECKV7A-NEXT: add r0, r2
; CHECKV7A-NEXT: bx lr
; CHECKV7A-NEXT: .LBB1_2: @ %else
-; CHECKV7A-NEXT: cmp.w r3, #-1
-; CHECKV7A-NEXT: it gt
-; CHECKV7A-NEXT: movgt r0, r12
+; CHECKV7A-NEXT: cmp r3, #0
+; CHECKV7A-NEXT: it ge
+; CHECKV7A-NEXT: movge r0, r12
; CHECKV7A-NEXT: bx lr
br i1 %c, label %then, label %else
then:
@@ -227,19 +227,19 @@ define i32 @icmp32_sge_0(i32 %x, i32 %y, i32 %a, i32 %b, i1 %c) {
; CHECKV7M-NEXT: lsls r3, r3, #31
; CHECKV7M-NEXT: beq .LBB2_2
; CHECKV7M-NEXT: @ %bb.1: @ %then
-; CHECKV7M-NEXT: cmp.w r1, #-1
+; CHECKV7M-NEXT: cmp r1, #0
; CHECKV7M-NEXT: mov r1, r12
-; CHECKV7M-NEXT: it gt
-; CHECKV7M-NEXT: movgt r1, r2
-; CHECKV7M-NEXT: cmp.w r0, #-1
-; CHECKV7M-NEXT: it gt
-; CHECKV7M-NEXT: movgt r12, r2
+; CHECKV7M-NEXT: it ge
+; CHECKV7M-NEXT: movge r1, r2
+; CHECKV7M-NEXT: cmp r0, #0
+; CHECKV7M-NEXT: it ge
+; CHECKV7M-NEXT: movge r12, r2
; CHECKV7M-NEXT: add.w r0, r12, r1
; CHECKV7M-NEXT: bx lr
; CHECKV7M-NEXT: .LBB2_2: @ %else
-; CHECKV7M-NEXT: cmp.w r0, #-1
-; CHECKV7M-NEXT: it gt
-; CHECKV7M-NEXT: movgt r12, r2
+; CHECKV7M-NEXT: cmp r0, #0
+; CHECKV7M-NEXT: it ge
+; CHECKV7M-NEXT: movge r12, r2
; CHECKV7M-NEXT: mov r0, r12
; CHECKV7M-NEXT: bx lr
;
@@ -250,19 +250,19 @@ define i32 @icmp32_sge_0(i32 %x, i32 %y, i32 %a, i32 %b, i1 %c) {
; CHECKV7A-NEXT: lsls r3, r3, #31
; CHECKV7A-NEXT: beq .LBB2_2
; CHECKV7A-NEXT: @ %bb.1: @ %then
-; CHECKV7A-NEXT: cmp.w r1, #-1
+; CHECKV7A-NEXT: cmp r1, #0
; CHECKV7A-NEXT: mov r1, r12
-; CHECKV7A-NEXT: it gt
-; CHECKV7A-NEXT: movgt r1, r2
-; CHECKV7A-NEXT: cmp.w r0, #-1
-; CHECKV7A-NEXT: it gt
-; CHECKV7A-NEXT: movgt r12, r2
+; CHECKV7A-NEXT: it ge
+; CHECKV7A-NEXT: movge r1, r2
+; CHECKV7A-NEXT: cmp r0, #0
+; CHECKV7A-NEXT: it ge
+; CHECKV7A-NEXT: movge r12, r2
; CHECKV7A-NEXT: add.w r0, r12, r1
; CHECKV7A-NEXT: bx lr
; CHECKV7A-NEXT: .LBB2_2: @ %else
-; CHECKV7A-NEXT: cmp.w r0, #-1
-; CHECKV7A-NEXT: it gt
-; CHECKV7A-NEXT: movgt r12, r2
+; CHECKV7A-NEXT: cmp r0, #0
+; CHECKV7A-NEXT: it ge
+; CHECKV7A-NEXT: movge r12, r2
; CHECKV7A-NEXT: mov r0, r12
; CHECKV7A-NEXT: bx lr
br i1 %c, label %then, label %else
@@ -321,19 +321,19 @@ define i32 @icmp32_sgt_m1(i32 %x, i32 %y, i32 %a, i32 %b, i1 %c) {
; CHECKV7M-NEXT: lsls r3, r3, #31
; CHECKV7M-NEXT: beq .LBB3_2
; CHECKV7M-NEXT: @ %bb.1: @ %then
-; CHECKV7M-NEXT: cmp.w r1, #-1
+; CHECKV7M-NEXT: cmp r1, #0
; CHECKV7M-NEXT: mov r1, r12
-; CHECKV7M-NEXT: it gt
-; CHECKV7M-NEXT: movgt r1, r2
-; CHECKV7M-NEXT: cmp.w r0, #-1
-; CHECKV7M-NEXT: it gt
-; CHECKV7M-NEXT: movgt r12, r2
+; CHECKV7M-NEXT: it ge
+; CHECKV7M-NEXT: movge r1, r2
+; CHECKV7M-NEXT: cmp r0, #0
+; CHECKV7M-NEXT: it ge
+; CHECKV7M-NEXT: movge r12, r2
; CHECKV7M-NEXT: add.w r0, r12, r1
; CHECKV7M-NEXT: bx lr
; CHECKV7M-NEXT: .LBB3_2: @ %else
-; CHECKV7M-NEXT: cmp.w r1, #-1
-; CHECKV7M-NEXT: it gt
-; CHECKV7M-NEXT: movgt r12, r2
+; CHECKV7M-NEXT: cmp r1, #0
+; CHECKV7M-NEXT: it ge
+; CHECKV7M-NEXT: movge r12, r2
; CHECKV7M-NEXT: mov r0, r12
; CHECKV7M-NEXT: bx lr
;
@@ -344,19 +344,19 @@ define i32 @icmp32_sgt_m1(i32 %x, i32 %y, i32 %a, i32 %b, i1 %c) {
; CHECKV7A-NEXT: lsls r3, r3, #31
; CHECKV7A-NEXT: beq .LBB3_2
; CHECKV7A-NEXT: @ %bb.1: @ %then
-; CHECKV7A-NEXT: cmp.w r1, #-1
+; CHECKV7A-NEXT: cmp r1, #0
; CHECKV7A-NEXT: mov r1, r12
-; CHECKV7A-NEXT: it gt
-; CHECKV7A-NEXT: movgt r1, r2
-; CHECKV7A-NEXT: cmp.w r0, #-1
-; CHECKV7A-NEXT: it gt
-; CHECKV7A-NEXT: movgt r12, r2
+; CHECKV7A-NEXT: it ge
+; CHECKV7A-NEXT: movge r1, r2
+; CHECKV7A-NEXT: cmp r0, #0
+; CHECKV7A-NEXT: it ge
+; CHECKV7A-NEXT: movge r12, r2
; CHECKV7A-NEXT: add.w r0, r12, r1
; CHECKV7A-NEXT: bx lr
; CHECKV7A-NEXT: .LBB3_2: @ %else
-; CHECKV7A-NEXT: cmp.w r1, #-1
-; CHECKV7A-NEXT: it gt
-; CHECKV7A-NEXT: movgt r12, r2
+; CHECKV7A-NEXT: cmp r1, #0
+; CHECKV7A-NEXT: it ge
+; CHECKV7A-NEXT: movge r12, r2
; CHECKV7A-NEXT: mov r0, r12
; CHECKV7A-NEXT: bx lr
br i1 %c, label %then, label %else
diff --git a/llvm/test/CodeGen/ARM/dsp-loop-indexing.ll b/llvm/test/CodeGen/ARM/dsp-loop-indexing.ll
index 9fb64471e9881..892e66aed4e5f 100644
--- a/llvm/test/CodeGen/ARM/dsp-loop-indexing.ll
+++ b/llvm/test/CodeGen/ARM/dsp-loop-indexing.ll
@@ -22,7 +22,7 @@
; CHECK-DEFAULT: ldr{{.*}}, #4]
; CHECK-DEFAULT: str{{.*}}, #4]
; CHECK-DEFAULT: ldr{{.*}}, #8]!
-; CHECK-DEAFULT: ldr{{.*}}, #8]!
+; CHECK-DEFAULT: ldr{{.*}}, #8]!
; CHECK-DEFAULT: str{{.*}}, #8]!
; CHECK-COMPLEX: ldr{{.*}}, #8]!
diff --git a/llvm/test/CodeGen/ARM/select-constant-xor.ll b/llvm/test/CodeGen/ARM/select-constant-xor.ll
index 543ddcd3efac9..2318418d02bd9 100644
--- a/llvm/test/CodeGen/ARM/select-constant-xor.ll
+++ b/llvm/test/CodeGen/ARM/select-constant-xor.ll
@@ -320,8 +320,8 @@ define i32 @icmpasreq(i32 %input, i32 %a, i32 %b) {
define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
; CHECK7A-LABEL: icmpasrne:
; CHECK7A: @ %bb.0:
-; CHECK7A-NEXT: cmn r0, #1
-; CHECK7A-NEXT: movle r1, r2
+; CHECK7A-NEXT: cmp r0, #0
+; CHECK7A-NEXT: movlt r1, r2
; CHECK7A-NEXT: mov r0, r1
; CHECK7A-NEXT: bx lr
;
@@ -337,16 +337,16 @@ define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
;
; CHECK7M-LABEL: icmpasrne:
; CHECK7M: @ %bb.0:
-; CHECK7M-NEXT: cmp.w r0, #-1
-; CHECK7M-NEXT: it le
-; CHECK7M-NEXT: movle r1, r2
+; CHECK7M-NEXT: cmp r0, #0
+; CHECK7M-NEXT: it lt
+; CHECK7M-NEXT: movlt r1, r2
; CHECK7M-NEXT: mov r0, r1
; CHECK7M-NEXT: bx lr
;
; CHECK81M-LABEL: icmpasrne:
; CHECK81M: @ %bb.0:
-; CHECK81M-NEXT: cmp.w r0, #-1
-; CHECK81M-NEXT: csel r0, r1, r2, gt
+; CHECK81M-NEXT: cmp r0, #0
+; CHECK81M-NEXT: csel r0, r1, r2, ge
; CHECK81M-NEXT: bx lr
%sh = ashr i32 %input, 31
%c = icmp ne i32 %sh, -1
diff --git a/llvm/test/CodeGen/ARM/sub-cmp-peephole.ll b/llvm/test/CodeGen/ARM/sub-cmp-peephole.ll
index fb966c29f39a2..f17b2e6db5fa6 100644
--- a/llvm/test/CodeGen/ARM/sub-cmp-peephole.ll
+++ b/llvm/test/CodeGen/ARM/sub-cmp-peephole.ll
@@ -264,9 +264,8 @@ define i32 @cmp_slt0(i32 %a, i32 %b, i32 %x, i32 %y) {
; CHECK-NEXT: movw r0, :lower16:t
; CHECK-NEXT: movt r0, :upper16:t
; CHECK-NEXT: ldr r0, [r0]
-; CHECK-NEXT: sub r0, r0, #17
-; CHECK-NEXT: cmn r0, #1
-; CHECK-NEXT: ble .LBB11_2
+; CHECK-NEXT: subs r0, r0, #17
+; CHECK-NEXT: bmi .LBB11_2
; CHECK-NEXT: @ %bb.1: @ %if.else
; CHECK-NEXT: mov r0, #0
; CHECK-NEXT: bl exit
diff --git a/llvm/test/CodeGen/ARM/vsel.ll b/llvm/test/CodeGen/ARM/vsel.ll
index 272e3361bd470..3825abf7c7f72 100644
--- a/llvm/test/CodeGen/ARM/vsel.ll
+++ b/llvm/test/CodeGen/ARM/vsel.ll
@@ -560,13 +560,13 @@ define void @test_vsel_gezero(i32 %lhs32, float %a, float %b) {
%tst1 = icmp sge i32 %lhs32, 0
%val1 = select i1 %tst1, float %a, float %b
store float %val1, ptr @varfloat
-; CHECK: cmn r0, #1
-; CHECK: vselgt.f32 s0, s0, s1
+; CHECK: cmp r0, #0
+; CHECK: vselge.f32 s0, s0, s1
ret void
}
define void @test_vsel_ltzero64(i32 %lhs32, double %a, double %b) {
-; CHECK-LABEL: test_vsel_ltzero
+; CHECK-LABEL: test_vsel_ltzero64
%tst1 = icmp slt i32 %lhs32, 0
%val1 = select i1 %tst1, double %a, double %b
store double %val1, ptr @vardouble
@@ -576,7 +576,7 @@ define void @test_vsel_ltzero64(i32 %lhs32, double %a, double %b) {
}
define void @test_vsel_lezero64(i32 %lhs32, double %a, double %b) {
-; CHECK-LABEL: test_vsel_lezero
+; CHECK-LABEL: test_vsel_lezero64
%tst1 = icmp sle i32 %lhs32, 0
%val1 = select i1 %tst1, double %a, double %b
store double %val1, ptr @vardouble
@@ -586,7 +586,7 @@ define void @test_vsel_lezero64(i32 %lhs32, double %a, double %b) {
}
define void @test_vsel_gtzero64(i32 %lhs32, double %a, double %b) {
-; CHECK-LABEL: test_vsel_gtzero
+; CHECK-LABEL: test_vsel_gtzero64
%tst1 = icmp sgt i32 %lhs32, 0
%val1 = select i1 %tst1, double %a, double %b
store double %val1, ptr @vardouble
@@ -596,11 +596,11 @@ define void @test_vsel_gtzero64(i32 %lhs32, double %a, double %b) {
}
define void @test_vsel_gezero64(i32 %lhs32, double %a, double %b) {
-; CHECK-LABEL: test_vsel_gezero
+; CHECK-LABEL: test_vsel_gezero64
%tst1 = icmp sge i32 %lhs32, 0
%val1 = select i1 %tst1, double %a, double %b
store double %val1, ptr @vardouble
-; CHECK: cmn r0, #1
-; CHECK: vselgt.f64 d16, d0, d1
+; CHECK: cmp r0, #0
+; CHECK: vselge.f64 d16, d0, d1
ret void
}
diff --git a/llvm/test/CodeGen/Thumb2/mve-memtp-loop.ll b/llvm/test/CodeGen/Thumb2/mve-memtp-loop.ll
index da59cb259db61..af17bb1430634 100644
--- a/llvm/test/CodeGen/Thumb2/mve-memtp-loop.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-memtp-loop.ll
@@ -211,9 +211,9 @@ entry:
define void @test11(ptr nocapture %x, ptr nocapture %y, i32 %n) {
; CHECK-LABEL: test11:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: cmp.w r2, #-1
-; CHECK-NEXT: it gt
-; CHECK-NEXT: bxgt lr
+; CHECK-NEXT: cmp r2, #0
+; CHECK-NEXT: it pl
+; CHECK-NEXT: bxpl lr
; CHECK-NEXT: .LBB10_1: @ %prehead
; CHECK-NEXT: .save {r4, lr}
; CHECK-NEXT: push {r4, lr}
diff --git a/llvm/test/CodeGen/Thumb2/mve-vselect-constants.ll b/llvm/test/CodeGen/Thumb2/mve-vselect-constants.ll
index 256456a2e9d0a..1ebfb7ed66fb7 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vselect-constants.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vselect-constants.ll
@@ -276,12 +276,12 @@ define arm_aapcs_vfpcc <2 x i64> @not_signbit_mask_v2i64(<2 x i64> %a, <2 x i64>
; CHECK-NEXT: vmov r1, s1
; CHECK-NEXT: movs r0, #0
; CHECK-NEXT: vmov.i32 q2, #0x0
-; CHECK-NEXT: cmp.w r1, #-1
-; CHECK-NEXT: csetm r1, gt
+; CHECK-NEXT: cmp r1, #0
+; CHECK-NEXT: csetm r1, pl
; CHECK-NEXT: bfi r0, r1, #0, #8
; CHECK-NEXT: vmov r1, s3
-; CHECK-NEXT: cmp.w r1, #-1
-; CHECK-NEXT: csetm r1, gt
+; CHECK-NEXT: cmp r1, #0
+; CHECK-NEXT: csetm r1, pl
; CHECK-NEXT: bfi r0, r1, #8, #8
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpsel q0, q1, q2
diff --git a/llvm/test/CodeGen/Thumb2/pacbti-m-outliner-4.ll b/llvm/test/CodeGen/Thumb2/pacbti-m-outliner-4.ll
index 5a154f4f4adbe..99bb85541d6ba 100644
--- a/llvm/test/CodeGen/Thumb2/pacbti-m-outliner-4.ll
+++ b/llvm/test/CodeGen/Thumb2/pacbti-m-outliner-4.ll
@@ -40,8 +40,8 @@ define hidden i32 @_Z1hii(i32 %a, i32 %b) local_unnamed_addr #0 {
; CHECK-NEXT: .cfi_offset lr, -4
; CHECK-NEXT: .cfi_offset ra_auth_code, -8
; CHECK-NEXT: .cfi_offset r7, -12
-; CHECK-NEXT: cmp.w r0, #-1
-; CHECK-NEXT: ble .LBB0_2
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: bmi .LBB0_2
; CHECK-NEXT: @ %bb.1: @ %if.end
; CHECK-NEXT: add r0, r1
; CHECK-NEXT: pop.w {r3, r7, r12, lr}
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