[llvm] [AArch64][ISel] Use SVE for fixed width vector reductions (PR #195806)

[Hassnaa Hamdi via llvm-commits]

================
@@ -0,0 +1,284 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu -mattr=+sve | FileCheck %s --check-prefixes=CHECK-SVE
+
+define i8 @test_v8i8_and(<8 x i8> %a) {
----------------
hassnaaHamdi wrote:

But why we are testing these reduction types here while this patch is for min/max reductions ?

https://github.com/llvm/llvm-project/pull/195806