[llvm] [AArch64] Add C1-Nano scheduling model (PR #182316)
via llvm-commits
llvm-commits at lists.llvm.org
Thu May 7 06:56:23 PDT 2026
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@@ -0,0 +1,3152 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=c1-nano -mattr=+aes -instruction-tables < %p/../Inputs/neon-instructions.s | FileCheck %s
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.50 abs d29, d24
+# CHECK-NEXT: 1 3 0.50 abs v0.16b, v0.16b
+# CHECK-NEXT: 1 3 0.50 abs v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.50 abs v0.2s, v0.2s
+# CHECK-NEXT: 1 3 0.50 abs v0.4h, v0.4h
+# CHECK-NEXT: 1 3 0.50 abs v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 abs v0.8b, v0.8b
+# CHECK-NEXT: 1 3 0.50 abs v0.8h, v0.8h
+# CHECK-NEXT: 1 3 0.50 add d17, d31, d29
+# CHECK-NEXT: 1 3 0.50 add v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 4 0.50 addhn v0.2s, v0.2d, v0.2d
+# CHECK-NEXT: 1 4 0.50 addhn v0.4h, v0.4s, v0.4s
+# CHECK-NEXT: 1 4 0.50 addhn v0.8b, v0.8h, v0.8h
+# CHECK-NEXT: 1 4 0.50 addhn2 v0.16b, v0.8h, v0.8h
+# CHECK-NEXT: 1 4 0.50 addhn2 v0.4s, v0.2d, v0.2d
+# CHECK-NEXT: 1 4 0.50 addhn2 v0.8h, v0.4s, v0.4s
+# CHECK-NEXT: 1 3 0.50 addp v7.2s, v1.2s, v2.2s
+# CHECK-NEXT: 1 3 0.50 addp v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 1 3 0.50 addp v0.8b, v0.8b, v0.8b
+# CHECK-NEXT: 1 3 0.50 addp d1, v14.2d
+# CHECK-NEXT: 1 3 1.00 addv s0, v0.4s
+# CHECK-NEXT: 1 3 1.00 addv h0, v0.4h
----------------
walkerkd wrote:
Fixed
https://github.com/llvm/llvm-project/pull/182316
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