[llvm] [ARM] preferIncOfAddToSubOfNot should just be VT.isScalarInteger(); (PR #196316)
via llvm-commits
llvm-commits at lists.llvm.org
Thu May 7 06:37:46 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-arm
Author: LumioseSil (LumioseSil)
<details>
<summary>Changes</summary>
We want this for scalars, not for vectors. Simple as.
---
Patch is 25.39 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/196316.diff
5 Files Affected:
- (modified) llvm/lib/Target/ARM/ARMISelLowering.cpp (+1-5)
- (modified) llvm/test/CodeGen/ARM/inc-of-add.ll (+111-111)
- (modified) llvm/test/CodeGen/ARM/sub-of-not.ll (+15-15)
- (modified) llvm/test/CodeGen/Thumb2/mve-halving.ll (+24-36)
- (modified) llvm/test/CodeGen/Thumb2/mve-vhadd.ll (+10-13)
``````````diff
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index cbff40f697b9b..201742062311d 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -13781,11 +13781,7 @@ bool ARMTargetLowering::shouldFoldSelectWithIdentityConstant(
}
bool ARMTargetLowering::preferIncOfAddToSubOfNot(EVT VT) const {
- if (!Subtarget->hasNEON()) {
- if (Subtarget->isThumb1Only())
- return VT.getScalarSizeInBits() <= 32;
- return true;
- }
+ // We want inc-of-add for scalars and sub-of-not for vectors.
return VT.isScalarInteger();
}
diff --git a/llvm/test/CodeGen/ARM/inc-of-add.ll b/llvm/test/CodeGen/ARM/inc-of-add.ll
index 3079dbceb9844..b5062412e86f7 100644
--- a/llvm/test/CodeGen/ARM/inc-of-add.ll
+++ b/llvm/test/CodeGen/ARM/inc-of-add.ll
@@ -91,11 +91,11 @@ define i64 @scalar_i64(i64 %x, i64 %y) nounwind {
;
; THUMB6-LABEL: scalar_i64:
; THUMB6: @ %bb.0:
-; THUMB6-NEXT: mvns r1, r1
-; THUMB6-NEXT: mvns r0, r0
-; THUMB6-NEXT: subs r0, r2, r0
-; THUMB6-NEXT: sbcs r3, r1
-; THUMB6-NEXT: mov r1, r3
+; THUMB6-NEXT: adds r0, r0, r2
+; THUMB6-NEXT: adcs r1, r3
+; THUMB6-NEXT: movs r2, #0
+; THUMB6-NEXT: adds r0, r0, #1
+; THUMB6-NEXT: adcs r1, r2
; THUMB6-NEXT: bx lr
;
; THUMB78-LABEL: scalar_i64:
@@ -113,82 +113,82 @@ define i64 @scalar_i64(i64 %x, i64 %y) nounwind {
define <16 x i8> @vector_i128_i8(<16 x i8> %x, <16 x i8> %y) nounwind {
; ARM6-LABEL: vector_i128_i8:
; ARM6: @ %bb.0:
-; ARM6-NEXT: ldrb r12, [sp, #116]
-; ARM6-NEXT: ldrb r1, [sp, #52]
+; ARM6-NEXT: ldrb r12, [sp, #52]
+; ARM6-NEXT: ldrb r1, [sp, #116]
; ARM6-NEXT: add r1, r1, r12
-; ARM6-NEXT: ldrb r12, [sp, #112]
+; ARM6-NEXT: ldrb r12, [sp, #48]
; ARM6-NEXT: add r1, r1, #1
; ARM6-NEXT: strb r1, [r0, #15]
-; ARM6-NEXT: ldrb r1, [sp, #48]
+; ARM6-NEXT: ldrb r1, [sp, #112]
; ARM6-NEXT: add r1, r1, r12
-; ARM6-NEXT: ldrb r12, [sp, #108]
+; ARM6-NEXT: ldrb r12, [sp, #44]
; ARM6-NEXT: add r1, r1, #1
; ARM6-NEXT: strb r1, [r0, #14]
-; ARM6-NEXT: ldrb r1, [sp, #44]
+; ARM6-NEXT: ldrb r1, [sp, #108]
; ARM6-NEXT: add r1, r1, r12
-; ARM6-NEXT: ldrb r12, [sp, #104]
+; ARM6-NEXT: ldrb r12, [sp, #40]
; ARM6-NEXT: add r1, r1, #1
; ARM6-NEXT: strb r1, [r0, #13]
-; ARM6-NEXT: ldrb r1, [sp, #40]
+; ARM6-NEXT: ldrb r1, [sp, #104]
; ARM6-NEXT: add r1, r1, r12
-; ARM6-NEXT: ldrb r12, [sp, #100]
+; ARM6-NEXT: ldrb r12, [sp, #36]
; ARM6-NEXT: add r1, r1, #1
; ARM6-NEXT: strb r1, [r0, #12]
-; ARM6-NEXT: ldrb r1, [sp, #36]
+; ARM6-NEXT: ldrb r1, [sp, #100]
; ARM6-NEXT: add r1, r1, r12
-; ARM6-NEXT: ldrb r12, [sp, #96]
+; ARM6-NEXT: ldrb r12, [sp, #32]
; ARM6-NEXT: add r1, r1, #1
; ARM6-NEXT: strb r1, [r0, #11]
-; ARM6-NEXT: ldrb r1, [sp, #32]
+; ARM6-NEXT: ldrb r1, [sp, #96]
; ARM6-NEXT: add r1, r1, r12
-; ARM6-NEXT: ldrb r12, [sp, #92]
+; ARM6-NEXT: ldrb r12, [sp, #28]
; ARM6-NEXT: add r1, r1, #1
; ARM6-NEXT: strb r1, [r0, #10]
-; ARM6-NEXT: ldrb r1, [sp, #28]
+; ARM6-NEXT: ldrb r1, [sp, #92]
; ARM6-NEXT: add r1, r1, r12
-; ARM6-NEXT: ldrb r12, [sp, #88]
+; ARM6-NEXT: ldrb r12, [sp, #24]
; ARM6-NEXT: add r1, r1, #1
; ARM6-NEXT: strb r1, [r0, #9]
-; ARM6-NEXT: ldrb r1, [sp, #24]
+; ARM6-NEXT: ldrb r1, [sp, #88]
; ARM6-NEXT: add r1, r1, r12
-; ARM6-NEXT: ldrb r12, [sp, #84]
+; ARM6-NEXT: ldrb r12, [sp, #20]
; ARM6-NEXT: add r1, r1, #1
; ARM6-NEXT: strb r1, [r0, #8]
-; ARM6-NEXT: ldrb r1, [sp, #20]
+; ARM6-NEXT: ldrb r1, [sp, #84]
; ARM6-NEXT: add r1, r1, r12
-; ARM6-NEXT: ldrb r12, [sp, #80]
+; ARM6-NEXT: ldrb r12, [sp, #16]
; ARM6-NEXT: add r1, r1, #1
; ARM6-NEXT: strb r1, [r0, #7]
-; ARM6-NEXT: ldrb r1, [sp, #16]
+; ARM6-NEXT: ldrb r1, [sp, #80]
; ARM6-NEXT: add r1, r1, r12
-; ARM6-NEXT: ldrb r12, [sp, #76]
+; ARM6-NEXT: ldrb r12, [sp, #12]
; ARM6-NEXT: add r1, r1, #1
; ARM6-NEXT: strb r1, [r0, #6]
-; ARM6-NEXT: ldrb r1, [sp, #12]
+; ARM6-NEXT: ldrb r1, [sp, #76]
; ARM6-NEXT: add r1, r1, r12
-; ARM6-NEXT: ldrb r12, [sp, #72]
+; ARM6-NEXT: ldrb r12, [sp, #8]
; ARM6-NEXT: add r1, r1, #1
; ARM6-NEXT: strb r1, [r0, #5]
-; ARM6-NEXT: ldrb r1, [sp, #8]
+; ARM6-NEXT: ldrb r1, [sp, #72]
; ARM6-NEXT: add r1, r1, r12
-; ARM6-NEXT: ldrb r12, [sp, #68]
+; ARM6-NEXT: ldrb r12, [sp, #4]
; ARM6-NEXT: add r1, r1, #1
; ARM6-NEXT: strb r1, [r0, #4]
-; ARM6-NEXT: ldrb r1, [sp, #4]
+; ARM6-NEXT: ldrb r1, [sp, #68]
; ARM6-NEXT: add r1, r1, r12
-; ARM6-NEXT: ldrb r12, [sp, #64]
+; ARM6-NEXT: ldrb r12, [sp]
; ARM6-NEXT: add r1, r1, #1
; ARM6-NEXT: strb r1, [r0, #3]
-; ARM6-NEXT: ldrb r1, [sp]
+; ARM6-NEXT: ldrb r1, [sp, #64]
; ARM6-NEXT: add r1, r1, r12
; ARM6-NEXT: add r1, r1, #1
; ARM6-NEXT: strb r1, [r0, #2]
; ARM6-NEXT: ldrb r1, [sp, #60]
-; ARM6-NEXT: add r1, r3, r1
+; ARM6-NEXT: add r1, r1, r3
; ARM6-NEXT: add r1, r1, #1
; ARM6-NEXT: strb r1, [r0, #1]
; ARM6-NEXT: ldrb r1, [sp, #56]
-; ARM6-NEXT: add r1, r2, r1
+; ARM6-NEXT: add r1, r1, r2
; ARM6-NEXT: add r1, r1, #1
; ARM6-NEXT: strb r1, [r0]
; ARM6-NEXT: bx lr
@@ -208,82 +208,82 @@ define <16 x i8> @vector_i128_i8(<16 x i8> %x, <16 x i8> %y) nounwind {
; THUMB6-LABEL: vector_i128_i8:
; THUMB6: @ %bb.0:
; THUMB6-NEXT: push {r4, lr}
-; THUMB6-NEXT: ldr r1, [sp, #124]
-; THUMB6-NEXT: ldr r4, [sp, #60]
+; THUMB6-NEXT: ldr r1, [sp, #60]
+; THUMB6-NEXT: ldr r4, [sp, #124]
; THUMB6-NEXT: adds r1, r4, r1
; THUMB6-NEXT: adds r1, r1, #1
; THUMB6-NEXT: strb r1, [r0, #15]
-; THUMB6-NEXT: ldr r1, [sp, #120]
-; THUMB6-NEXT: ldr r4, [sp, #56]
+; THUMB6-NEXT: ldr r1, [sp, #56]
+; THUMB6-NEXT: ldr r4, [sp, #120]
; THUMB6-NEXT: adds r1, r4, r1
; THUMB6-NEXT: adds r1, r1, #1
; THUMB6-NEXT: strb r1, [r0, #14]
-; THUMB6-NEXT: ldr r1, [sp, #116]
-; THUMB6-NEXT: ldr r4, [sp, #52]
+; THUMB6-NEXT: ldr r1, [sp, #52]
+; THUMB6-NEXT: ldr r4, [sp, #116]
; THUMB6-NEXT: adds r1, r4, r1
; THUMB6-NEXT: adds r1, r1, #1
; THUMB6-NEXT: strb r1, [r0, #13]
-; THUMB6-NEXT: ldr r1, [sp, #112]
-; THUMB6-NEXT: ldr r4, [sp, #48]
+; THUMB6-NEXT: ldr r1, [sp, #48]
+; THUMB6-NEXT: ldr r4, [sp, #112]
; THUMB6-NEXT: adds r1, r4, r1
; THUMB6-NEXT: adds r1, r1, #1
; THUMB6-NEXT: strb r1, [r0, #12]
-; THUMB6-NEXT: ldr r1, [sp, #108]
-; THUMB6-NEXT: ldr r4, [sp, #44]
+; THUMB6-NEXT: ldr r1, [sp, #44]
+; THUMB6-NEXT: ldr r4, [sp, #108]
; THUMB6-NEXT: adds r1, r4, r1
; THUMB6-NEXT: adds r1, r1, #1
; THUMB6-NEXT: strb r1, [r0, #11]
-; THUMB6-NEXT: ldr r1, [sp, #104]
-; THUMB6-NEXT: ldr r4, [sp, #40]
+; THUMB6-NEXT: ldr r1, [sp, #40]
+; THUMB6-NEXT: ldr r4, [sp, #104]
; THUMB6-NEXT: adds r1, r4, r1
; THUMB6-NEXT: adds r1, r1, #1
; THUMB6-NEXT: strb r1, [r0, #10]
-; THUMB6-NEXT: ldr r1, [sp, #100]
-; THUMB6-NEXT: ldr r4, [sp, #36]
+; THUMB6-NEXT: ldr r1, [sp, #36]
+; THUMB6-NEXT: ldr r4, [sp, #100]
; THUMB6-NEXT: adds r1, r4, r1
; THUMB6-NEXT: adds r1, r1, #1
; THUMB6-NEXT: strb r1, [r0, #9]
-; THUMB6-NEXT: ldr r1, [sp, #96]
-; THUMB6-NEXT: ldr r4, [sp, #32]
+; THUMB6-NEXT: ldr r1, [sp, #32]
+; THUMB6-NEXT: ldr r4, [sp, #96]
; THUMB6-NEXT: adds r1, r4, r1
; THUMB6-NEXT: adds r1, r1, #1
; THUMB6-NEXT: strb r1, [r0, #8]
-; THUMB6-NEXT: ldr r1, [sp, #92]
-; THUMB6-NEXT: ldr r4, [sp, #28]
+; THUMB6-NEXT: ldr r1, [sp, #28]
+; THUMB6-NEXT: ldr r4, [sp, #92]
; THUMB6-NEXT: adds r1, r4, r1
; THUMB6-NEXT: adds r1, r1, #1
; THUMB6-NEXT: strb r1, [r0, #7]
-; THUMB6-NEXT: ldr r1, [sp, #88]
-; THUMB6-NEXT: ldr r4, [sp, #24]
+; THUMB6-NEXT: ldr r1, [sp, #24]
+; THUMB6-NEXT: ldr r4, [sp, #88]
; THUMB6-NEXT: adds r1, r4, r1
; THUMB6-NEXT: adds r1, r1, #1
; THUMB6-NEXT: strb r1, [r0, #6]
-; THUMB6-NEXT: ldr r1, [sp, #84]
-; THUMB6-NEXT: ldr r4, [sp, #20]
+; THUMB6-NEXT: ldr r1, [sp, #20]
+; THUMB6-NEXT: ldr r4, [sp, #84]
; THUMB6-NEXT: adds r1, r4, r1
; THUMB6-NEXT: adds r1, r1, #1
; THUMB6-NEXT: strb r1, [r0, #5]
-; THUMB6-NEXT: ldr r1, [sp, #80]
-; THUMB6-NEXT: ldr r4, [sp, #16]
+; THUMB6-NEXT: ldr r1, [sp, #16]
+; THUMB6-NEXT: ldr r4, [sp, #80]
; THUMB6-NEXT: adds r1, r4, r1
; THUMB6-NEXT: adds r1, r1, #1
; THUMB6-NEXT: strb r1, [r0, #4]
-; THUMB6-NEXT: ldr r1, [sp, #76]
-; THUMB6-NEXT: ldr r4, [sp, #12]
+; THUMB6-NEXT: ldr r1, [sp, #12]
+; THUMB6-NEXT: ldr r4, [sp, #76]
; THUMB6-NEXT: adds r1, r4, r1
; THUMB6-NEXT: adds r1, r1, #1
; THUMB6-NEXT: strb r1, [r0, #3]
-; THUMB6-NEXT: ldr r1, [sp, #72]
-; THUMB6-NEXT: ldr r4, [sp, #8]
+; THUMB6-NEXT: ldr r1, [sp, #8]
+; THUMB6-NEXT: ldr r4, [sp, #72]
; THUMB6-NEXT: adds r1, r4, r1
; THUMB6-NEXT: adds r1, r1, #1
; THUMB6-NEXT: strb r1, [r0, #2]
; THUMB6-NEXT: ldr r1, [sp, #68]
-; THUMB6-NEXT: adds r1, r3, r1
+; THUMB6-NEXT: adds r1, r1, r3
; THUMB6-NEXT: adds r1, r1, #1
; THUMB6-NEXT: strb r1, [r0, #1]
; THUMB6-NEXT: ldr r1, [sp, #64]
-; THUMB6-NEXT: adds r1, r2, r1
+; THUMB6-NEXT: adds r1, r1, r2
; THUMB6-NEXT: adds r1, r1, #1
; THUMB6-NEXT: strb r1, [r0]
; THUMB6-NEXT: pop {r4, pc}
@@ -307,42 +307,42 @@ define <16 x i8> @vector_i128_i8(<16 x i8> %x, <16 x i8> %y) nounwind {
define <8 x i16> @vector_i128_i16(<8 x i16> %x, <8 x i16> %y) nounwind {
; ARM6-LABEL: vector_i128_i16:
; ARM6: @ %bb.0:
-; ARM6-NEXT: ldrh r12, [sp, #52]
-; ARM6-NEXT: ldrh r1, [sp, #20]
+; ARM6-NEXT: ldrh r12, [sp, #20]
+; ARM6-NEXT: ldrh r1, [sp, #52]
; ARM6-NEXT: add r1, r1, r12
-; ARM6-NEXT: ldrh r12, [sp, #48]
+; ARM6-NEXT: ldrh r12, [sp, #16]
; ARM6-NEXT: add r1, r1, #1
; ARM6-NEXT: strh r1, [r0, #14]
-; ARM6-NEXT: ldrh r1, [sp, #16]
+; ARM6-NEXT: ldrh r1, [sp, #48]
; ARM6-NEXT: add r1, r1, r12
-; ARM6-NEXT: ldrh r12, [sp, #44]
+; ARM6-NEXT: ldrh r12, [sp, #12]
; ARM6-NEXT: add r1, r1, #1
; ARM6-NEXT: strh r1, [r0, #12]
-; ARM6-NEXT: ldrh r1, [sp, #12]
+; ARM6-NEXT: ldrh r1, [sp, #44]
; ARM6-NEXT: add r1, r1, r12
-; ARM6-NEXT: ldrh r12, [sp, #40]
+; ARM6-NEXT: ldrh r12, [sp, #8]
; ARM6-NEXT: add r1, r1, #1
; ARM6-NEXT: strh r1, [r0, #10]
-; ARM6-NEXT: ldrh r1, [sp, #8]
+; ARM6-NEXT: ldrh r1, [sp, #40]
; ARM6-NEXT: add r1, r1, r12
-; ARM6-NEXT: ldrh r12, [sp, #36]
+; ARM6-NEXT: ldrh r12, [sp, #4]
; ARM6-NEXT: add r1, r1, #1
; ARM6-NEXT: strh r1, [r0, #8]
-; ARM6-NEXT: ldrh r1, [sp, #4]
+; ARM6-NEXT: ldrh r1, [sp, #36]
; ARM6-NEXT: add r1, r1, r12
-; ARM6-NEXT: ldrh r12, [sp, #32]
+; ARM6-NEXT: ldrh r12, [sp]
; ARM6-NEXT: add r1, r1, #1
; ARM6-NEXT: strh r1, [r0, #6]
-; ARM6-NEXT: ldrh r1, [sp]
+; ARM6-NEXT: ldrh r1, [sp, #32]
; ARM6-NEXT: add r1, r1, r12
; ARM6-NEXT: add r1, r1, #1
; ARM6-NEXT: strh r1, [r0, #4]
; ARM6-NEXT: ldrh r1, [sp, #28]
-; ARM6-NEXT: add r1, r3, r1
+; ARM6-NEXT: add r1, r1, r3
; ARM6-NEXT: add r1, r1, #1
; ARM6-NEXT: strh r1, [r0, #2]
; ARM6-NEXT: ldrh r1, [sp, #24]
-; ARM6-NEXT: add r1, r2, r1
+; ARM6-NEXT: add r1, r1, r2
; ARM6-NEXT: add r1, r1, #1
; ARM6-NEXT: strh r1, [r0]
; ARM6-NEXT: bx lr
@@ -362,42 +362,42 @@ define <8 x i16> @vector_i128_i16(<8 x i16> %x, <8 x i16> %y) nounwind {
; THUMB6-LABEL: vector_i128_i16:
; THUMB6: @ %bb.0:
; THUMB6-NEXT: push {r4, lr}
-; THUMB6-NEXT: ldr r1, [sp, #60]
-; THUMB6-NEXT: ldr r4, [sp, #28]
+; THUMB6-NEXT: ldr r1, [sp, #28]
+; THUMB6-NEXT: ldr r4, [sp, #60]
; THUMB6-NEXT: adds r1, r4, r1
; THUMB6-NEXT: adds r1, r1, #1
; THUMB6-NEXT: strh r1, [r0, #14]
-; THUMB6-NEXT: ldr r1, [sp, #56]
-; THUMB6-NEXT: ldr r4, [sp, #24]
+; THUMB6-NEXT: ldr r1, [sp, #24]
+; THUMB6-NEXT: ldr r4, [sp, #56]
; THUMB6-NEXT: adds r1, r4, r1
; THUMB6-NEXT: adds r1, r1, #1
; THUMB6-NEXT: strh r1, [r0, #12]
-; THUMB6-NEXT: ldr r1, [sp, #52]
-; THUMB6-NEXT: ldr r4, [sp, #20]
+; THUMB6-NEXT: ldr r1, [sp, #20]
+; THUMB6-NEXT: ldr r4, [sp, #52]
; THUMB6-NEXT: adds r1, r4, r1
; THUMB6-NEXT: adds r1, r1, #1
; THUMB6-NEXT: strh r1, [r0, #10]
-; THUMB6-NEXT: ldr r1, [sp, #48]
-; THUMB6-NEXT: ldr r4, [sp, #16]
+; THUMB6-NEXT: ldr r1, [sp, #16]
+; THUMB6-NEXT: ldr r4, [sp, #48]
; THUMB6-NEXT: adds r1, r4, r1
; THUMB6-NEXT: adds r1, r1, #1
; THUMB6-NEXT: strh r1, [r0, #8]
-; THUMB6-NEXT: ldr r1, [sp, #44]
-; THUMB6-NEXT: ldr r4, [sp, #12]
+; THUMB6-NEXT: ldr r1, [sp, #12]
+; THUMB6-NEXT: ldr r4, [sp, #44]
; THUMB6-NEXT: adds r1, r4, r1
; THUMB6-NEXT: adds r1, r1, #1
; THUMB6-NEXT: strh r1, [r0, #6]
-; THUMB6-NEXT: ldr r1, [sp, #40]
-; THUMB6-NEXT: ldr r4, [sp, #8]
+; THUMB6-NEXT: ldr r1, [sp, #8]
+; THUMB6-NEXT: ldr r4, [sp, #40]
; THUMB6-NEXT: adds r1, r4, r1
; THUMB6-NEXT: adds r1, r1, #1
; THUMB6-NEXT: strh r1, [r0, #4]
; THUMB6-NEXT: ldr r1, [sp, #36]
-; THUMB6-NEXT: adds r1, r3, r1
+; THUMB6-NEXT: adds r1, r1, r3
; THUMB6-NEXT: adds r1, r1, #1
; THUMB6-NEXT: strh r1, [r0, #2]
; THUMB6-NEXT: ldr r1, [sp, #32]
-; THUMB6-NEXT: adds r1, r2, r1
+; THUMB6-NEXT: adds r1, r1, r2
; THUMB6-NEXT: adds r1, r1, #1
; THUMB6-NEXT: strh r1, [r0]
; THUMB6-NEXT: pop {r4, pc}
@@ -422,16 +422,16 @@ define <4 x i32> @vector_i128_i32(<4 x i32> %x, <4 x i32> %y) nounwind {
; ARM6-LABEL: vector_i128_i32:
; ARM6: @ %bb.0:
; ARM6-NEXT: ldr r12, [sp]
-; ARM6-NEXT: add r0, r0, r12
+; ARM6-NEXT: add r0, r12, r0
; ARM6-NEXT: ldr r12, [sp, #4]
; ARM6-NEXT: add r0, r0, #1
-; ARM6-NEXT: add r1, r1, r12
+; ARM6-NEXT: add r1, r12, r1
; ARM6-NEXT: ldr r12, [sp, #8]
; ARM6-NEXT: add r1, r1, #1
-; ARM6-NEXT: add r2, r2, r12
+; ARM6-NEXT: add r2, r12, r2
; ARM6-NEXT: ldr r12, [sp, #12]
; ARM6-NEXT: add r2, r2, #1
-; ARM6-NEXT: add r3, r3, r12
+; ARM6-NEXT: add r3, r12, r3
; ARM6-NEXT: add r3, r3, #1
; ARM6-NEXT: bx lr
;
@@ -451,16 +451,16 @@ define <4 x i32> @vector_i128_i32(<4 x i32> %x, <4 x i32> %y) nounwind {
; THUMB6: @ %bb.0:
; THUMB6-NEXT: push {r4, lr}
; THUMB6-NEXT: ldr r4, [sp, #8]
-; THUMB6-NEXT: adds r0, r0, r4
+; THUMB6-NEXT: adds r0, r4, r0
; THUMB6-NEXT: adds r0, r0, #1
; THUMB6-NEXT: ldr r4, [sp, #12]
-; THUMB6-NEXT: adds r1, r1, r4
+; THUMB6-NEXT: adds r1, r4, r1
; THUMB6-NEXT: adds r1, r1, #1
; THUMB6-NEXT: ldr r4, [sp, #16]
-; THUMB6-NEXT: adds r2, r2, r4
+; THUMB6-NEXT: adds r2, r4, r2
; THUMB6-NEXT: adds r2, r2, #1
; THUMB6-NEXT: ldr r4, [sp, #20]
-; THUMB6-NEXT: adds r3, r3, r4
+; THUMB6-NEXT: adds r3, r4, r3
; THUMB6-NEXT: adds r3, r3, #1
; THUMB6-NEXT: pop {r4, pc}
;
@@ -484,18 +484,18 @@ define <2 x i64> @vector_i128_i64(<2 x i64> %x, <2 x i64> %y) nounwind {
; ARM6-LABEL: vector_i128_i64:
; ARM6: @ %bb.0:
; ARM6-NEXT: push {r11, lr}
-; ARM6-NEXT: ldr lr, [sp, #8]
+; ARM6-NEXT: mvn lr, r1
+; ARM6-NEXT: ldr r1, [sp, #8]
+; ARM6-NEXT: mvn r0, r0
; ARM6-NEXT: ldr r12, [sp, #12]
-; ARM6-NEXT: adds r0, r0, lr
-; ARM6-NEXT: ldr lr, [sp, #16]
-; ARM6-NEXT: adc r1, r1, r12
-; ARM6-NEXT: adds r0, r0, #1
+; ARM6-NEXT: subs r0, r1, r0
+; ARM6-NEXT: mvn r2, r2
+; ARM6-NEXT: sbc r1, r12, lr
+; ARM6-NEXT: mvn lr, r3
+; ARM6-NEXT: ldr r3, [sp, #16]
; ARM6-NEXT: ldr r12, [sp, #20]
-; ARM6-NEXT: adc r1, r1, #0
-; ARM6-NEXT: adds r2, r2, lr
-; ARM6-NEXT: adc r3, r3, r12
-; ARM6-NEXT: adds r2, r2, #1
-; ARM6-NEXT: adc r3, r3, #0
+; ARM6-NEXT: subs r2, r3, r2
+; ARM6-NEXT: sbc r3, r12, lr
; ARM6-NEXT: pop {r11, pc}
;
; ARM78-LABEL: vector_i128_i64:
diff --git a/llvm/test/CodeGen/ARM/sub-of-not.ll b/llvm/test/CodeGen/ARM/sub-of-not.ll
index 97c6f8f25a3bb..93a6d03b71f3f 100644
--- a/llvm/test/CodeGen/ARM/sub-of-not.ll
+++ b/llvm/test/CodeGen/ARM/sub-of-not.ll
@@ -91,11 +91,11 @@ define i64 @scalar_i64(i64 %x, i64 %y) nounwind {
;
; THUMB6-LABEL: scalar_i64:
; THUMB6: @ %bb.0:
-; THUMB6-NEXT: mvns r1, r1
-; THUMB6-NEXT: mvns r0, r0
-; THUMB6-NEXT: subs r0, r2, r0
-; THUMB6-NEXT: sbcs r3, r1
-; THUMB6-NEXT: mov r1, r3
+; THUMB6-NEXT: adds r0, r2, r0
+; THUMB6-NEXT: adcs r1, r3
+; THUMB6-NEXT: movs r2, #0
+; THUMB6-NEXT: adds r0, r0, #1
+; THUMB6-NEXT: adcs r1, r2
; THUMB6-NEXT: bx lr
;
; THUMB78-LABEL: scalar_i64:
@@ -484,18 +484,18 @@ define <2 x i64> @vector_i128_i64(<2 x i64> %x, <2 x i64> %y) nounwind {
; ARM6-LABEL: vector_i128_i64:
; ARM6: @ %bb.0:
; ARM6-NEXT: push {r11, lr}
-; ARM6-NEXT: ldr lr, [sp, #8]
+; ARM6-NEXT: mvn lr, r1
+; ARM6-NEXT: ldr r1, [sp, #8]
+; ARM6-NEXT: mvn r0, r0
; ARM6-NEXT: ldr r12, [sp, #12]
-; ARM6-NEXT: adds r0, lr, r0
-; ARM6-NEXT: ldr lr, [sp, #16]
-; ARM6-NEXT: adc r1, r12, r1
-; ARM6-NEXT: adds r0, r0, #1
+; ARM6-NEXT: subs r0, r1, r0
+; ARM6-NEXT: mvn r2, r2
+; ARM6-NEXT: sbc r1, r12, lr
+; ARM6-NEXT: mvn lr, r3
+; ARM6-NEXT: ldr r3, [sp, #16]
; ARM6-NEXT: ldr r12, [sp, #20]
-; ARM6-NEXT: adc r1, r1, #0
-; ARM6-NEXT: adds r2, lr, r2
-; ARM6-NEXT: adc r3, r12, r3
-; ARM6-NEXT: adds r2, r2, #1
-; ARM6-NEXT: adc r3, r3, #0
+; ARM6-NEXT: subs r2, r3, r2
+; ARM6-NEXT: sbc r3, r12, lr
; ARM6-NEXT: pop {r11, pc}
;
; ARM78-LABEL: vector_i128_i64:
diff --git a/llvm/test/CodeGen/Thumb2/mve-halving.ll b/llvm/test/CodeGen/Thumb2/mve-halving.ll
index b4dc97cf13311..524818e8d210d 100644
--- a/llvm/test/CodeGen/Thumb2/mve-halving.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-halving.ll
@@ -233,9 +233,8 @@ define arm_aapcs_vfpcc <4 x i32> @vhsubu_v4i32_nw(<4 x i32> %x, <4 x i32> %y) {
define arm_aapcs_vfpcc <16 x i8> @vrhadds_v16i8(<16 x i8> %x, <16 x i8> %y) {
; CHECK-LABEL: vrhadds_v16i8:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vadd.i8 q0, q0, q1
-; CHECK-NEXT: movs r0, #1
-; CHECK-NEXT: vadd.i8 q0, q0, r0
+; CHECK-NEXT: vmvn q0, q0
+; CHECK-NEXT: vsub.i8 q0, q1, q0
; CHECK-NEXT: vshr.s8 q0, q0, #1
; CHECK-NEXT: bx lr
%add = add <16 x i8> %x, %y
@@ -246,9 +245,8 @@ define arm_aapcs_vfpcc <16 x i8> @vrhadds_v16i8(<16 x i8> %x, <16 x i8> %y) {
define arm_aapcs_vfpcc <16 x i8> @vrhaddu_v16i8(<16 x i8> %x, <16 x i8> %y) {
; CHECK-LABEL: vrhaddu_v16i8:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vadd.i8 q0, q0, q1
-; CHECK-NEXT: movs r0, #1
-; CHECK-NEXT: vadd.i8 q0, q0, r0
+; CHECK-NEXT: vmvn q0, q0
+; CHECK-NEXT: vsub.i8 q0, q1, q0
; CHECK-NEXT: vshr.u8 q0, q0, #1
; CHECK-NEXT: bx lr
%add = add <16 x i8> %x, %y
@@ -259,9 +257,8 @@ define arm_aapcs_vfpcc <16 x i8> @vrhaddu_v16i8(<16 x i8> %x, <16 x i8> %y) {
define arm_aapcs_vfpcc <8 x i16> @vrhadds_v8i16(<8 x i16> %x, <8 x i16> %y) {
; CHECK-LABEL: vrhadds_v8i16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vadd.i16 q0, q0, q1
-; CHECK-NEXT: movs r0, #1
-; CHECK-NEXT: vadd.i16 q0, q0, r0
+; CHECK-NEXT: vmvn q0, q0
+; CHECK-NEXT: vsub.i16 q0, q1, q0
; CHECK-NEXT: vshr.s16 q0, q0, #1
; CHECK-NEXT: bx lr
%add = add <8 x i16> %x, %y
@@ -272,9 +269,8 @@ define arm_aapcs_vfpcc <8 x i16> @vrhadds_v8i16(<8 x i16> %x, <8 x i16> %y) {
define arm_aapcs_vfpcc <8 x i16> @vrhaddu_v8i16(<8 x i16> %x, <8 x i16> %y) {
; CHECK-LABEL: vrhaddu_v8i16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vadd.i16 q0, q0, q1
-; CHECK-NEXT: movs r0, #1
-; CHECK-NEXT: vadd.i16 q0, q0, r0
+; CHECK-NEXT: vmvn q0, q0
+; CHECK-NEXT: vsub.i16 q0, q1, q0
; CHECK-NEXT: vshr.u16 q0, q0, #1
; CHECK-NEXT: bx lr
%add = add <8 x i16> %x, %y
@@ -285,9 +281,8 @@ define arm_aapcs_vfpcc <8 x i16> @vrhaddu_v8i16(<8 x i16> %x, <8 x i16> %y) {
define arm_aapcs_vfpcc <4 x i32> @vrhadds_v4i32(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: vrhadds_v4i32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vadd.i32 q0, q0, q1
-; CHECK-NEXT: movs r0, #1
-; CHECK-NEXT: vadd.i32 q0, q0, r0
+; CHECK-NEXT: vmvn q0, q0
+; CHECK-NEXT: vsub.i32 q0, q1, q0
; CHECK-NEXT: vshr.s32 q0, q0, #1
; CHECK-NEXT: bx lr
%add = add <4 x i32...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/196316
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