[llvm] [AArch64][ISel] Use SVE for fixed width vector reductions (PR #195806)

[Paul Walker via llvm-commits]

================
@@ -1935,13 +1935,13 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
     setOperationAction(ISD::MUL, MVT::v1i64, Custom);
     setOperationAction(ISD::MUL, MVT::v2i64, Custom);
 
+    // NEON doesn't support 128-bit [s|u][min|max] operations.
+    // With SVE we can try lowering these to predicated operations (e.g. smaxv).
     // With SVE2 we can try lowering these to pairwise operations (e.g. smaxp).
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paulwalker-arm wrote:

```suggestion
    // NEON doesn't support i64 vector [s|u][min|max] operations, but SVE does.
```

https://github.com/llvm/llvm-project/pull/195806