[llvm] [ARM][MVE] Combine extract(bitcast(buildvec(extract))) (PR #196263)
via llvm-commits
llvm-commits at lists.llvm.org
Thu May 7 02:09:02 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-arm
Author: David Green (davemgreen)
<details>
<summary>Changes</summary>
Due to some of the lowering we have for buildvector to attempt to use fp lanes efficiently under arm, we can end up with
extract(bitcast(BUILD_VECTOR(extract(bitcast(a)), ..))) that we can convert into simpler extract(a).
---
Patch is 61.67 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/196263.diff
12 Files Affected:
- (modified) llvm/lib/Target/ARM/ARMISelLowering.cpp (+29)
- (modified) llvm/test/CodeGen/Thumb2/active_lane_mask.ll (+5-6)
- (modified) llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll (+2-4)
- (modified) llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll (+2-4)
- (modified) llvm/test/CodeGen/Thumb2/mve-laneinterleaving-cost.ll (+103-117)
- (modified) llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll (+2-4)
- (modified) llvm/test/CodeGen/Thumb2/mve-sext-masked-load.ll (+12-17)
- (modified) llvm/test/CodeGen/Thumb2/mve-shuffle.ll (+69-134)
- (modified) llvm/test/CodeGen/Thumb2/mve-vabdus.ll (+28-36)
- (modified) llvm/test/CodeGen/Thumb2/mve-vld3.ll (+218-183)
- (modified) llvm/test/CodeGen/Thumb2/mve-vld4.ll (+13-19)
- (modified) llvm/test/CodeGen/Thumb2/mve-vst3.ll (+139-153)
``````````diff
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index cbff40f697b9b..66390c04f405b 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -15659,6 +15659,35 @@ static SDValue PerformExtractEltCombine(SDNode *N,
DCI.DAG.getConstant(SubIdx, dl, MVT::i32));
}
+ // extract(bitcast(BUILD_VECTOR(extract(bitcast(a)), ..))) -> extract(a)
+ if (ST->isLittle() && Op0.getOpcode() == ISD::BITCAST &&
+ Op0.getOperand(0).getOpcode() == ARMISD::BUILD_VECTOR &&
+ isa<ConstantSDNode>(N->getOperand(1)) &&
+ Op0.getScalarValueSizeInBits() <=
+ Op0.getOperand(0).getScalarValueSizeInBits()) {
+ unsigned Lane = N->getConstantOperandVal(1);
+ EVT ExtVT = Op0.getValueType();
+ EVT BVVT = Op0.getOperand(0).getValueType();
+ unsigned BVLane =
+ (Lane * BVVT.getVectorNumElements()) / ExtVT.getVectorNumElements();
+ assert(BVLane < Op0.getOperand(0).getNumOperands());
+ SDValue Ext = Op0.getOperand(0).getOperand(BVLane);
+ if (Ext.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
+ Ext.getOperand(0).getOpcode() == ISD::BITCAST &&
+ isa<ConstantSDNode>(Ext.getOperand(1)) &&
+ Ext.getOperand(0).getOperand(0).getValueType() == ExtVT) {
+ unsigned InnerLane = Ext.getConstantOperandVal(1);
+ unsigned BVSubLane = Lane - (BVLane * ExtVT.getVectorNumElements()) /
+ BVVT.getVectorNumElements();
+ unsigned FinalLane = (InnerLane * ExtVT.getVectorNumElements()) /
+ BVVT.getVectorNumElements() +
+ BVSubLane;
+ return DCI.DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT,
+ Ext.getOperand(0).getOperand(0),
+ DCI.DAG.getConstant(FinalLane, dl, MVT::i32));
+ }
+ }
+
return SDValue();
}
diff --git a/llvm/test/CodeGen/Thumb2/active_lane_mask.ll b/llvm/test/CodeGen/Thumb2/active_lane_mask.ll
index b75f1ff742bee..deb4dc7450640 100644
--- a/llvm/test/CodeGen/Thumb2/active_lane_mask.ll
+++ b/llvm/test/CodeGen/Thumb2/active_lane_mask.ll
@@ -119,12 +119,11 @@ define <7 x i32> @v7i32(i32 %index, i32 %TC, <7 x i32> %V1, <7 x i32> %V2) {
; CHECK-NEXT: ldr r1, [sp, #24]
; CHECK-NEXT: vmov q1[2], q1[0], r2, r1
; CHECK-NEXT: vpsel q0, q1, q0
-; CHECK-NEXT: vmov r1, s2
-; CHECK-NEXT: vmov.f32 s2, s1
-; CHECK-NEXT: vmov r3, s0
-; CHECK-NEXT: vmov r2, s2
-; CHECK-NEXT: strd r3, r2, [r0, #16]
-; CHECK-NEXT: str r1, [r0, #24]
+; CHECK-NEXT: vmov r1, s1
+; CHECK-NEXT: vmov r2, s0
+; CHECK-NEXT: vmov r3, s2
+; CHECK-NEXT: strd r2, r1, [r0, #16]
+; CHECK-NEXT: str r3, [r0, #24]
; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: @ %bb.1:
diff --git a/llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll b/llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll
index 77548b49d77f2..67250d5a05d4f 100644
--- a/llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll
@@ -185,9 +185,8 @@ define arm_aapcs_vfpcc <6 x i32> @test_signed_v6f32_v6i32(<6 x float> %f) {
; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vcvt.s32.f32 q1, q1
; CHECK-MVEFP-NEXT: vcvt.s32.f32 q0, q0
-; CHECK-MVEFP-NEXT: vmov.f32 s6, s5
+; CHECK-MVEFP-NEXT: vmov r1, s5
; CHECK-MVEFP-NEXT: vmov r2, s4
-; CHECK-MVEFP-NEXT: vmov r1, s6
; CHECK-MVEFP-NEXT: strd r2, r1, [r0, #16]
; CHECK-MVEFP-NEXT: vstrw.32 q0, [r0]
; CHECK-MVEFP-NEXT: bx lr
@@ -221,10 +220,9 @@ define arm_aapcs_vfpcc <7 x i32> @test_signed_v7f32_v7i32(<7 x float> %f) {
; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vcvt.s32.f32 q1, q1
; CHECK-MVEFP-NEXT: vcvt.s32.f32 q0, q0
-; CHECK-MVEFP-NEXT: vmov.f32 s10, s5
+; CHECK-MVEFP-NEXT: vmov r1, s5
; CHECK-MVEFP-NEXT: vmov r2, s4
; CHECK-MVEFP-NEXT: vmov r3, s6
-; CHECK-MVEFP-NEXT: vmov r1, s10
; CHECK-MVEFP-NEXT: strd r2, r1, [r0, #16]
; CHECK-MVEFP-NEXT: str r3, [r0, #24]
; CHECK-MVEFP-NEXT: vstrw.32 q0, [r0]
diff --git a/llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll b/llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll
index 1a22270ea0ebe..4602a5d6dd44c 100644
--- a/llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll
@@ -172,9 +172,8 @@ define arm_aapcs_vfpcc <6 x i32> @test_unsigned_v6f32_v6i32(<6 x float> %f) {
; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vcvt.u32.f32 q1, q1
; CHECK-MVEFP-NEXT: vcvt.u32.f32 q0, q0
-; CHECK-MVEFP-NEXT: vmov.f32 s6, s5
+; CHECK-MVEFP-NEXT: vmov r1, s5
; CHECK-MVEFP-NEXT: vmov r2, s4
-; CHECK-MVEFP-NEXT: vmov r1, s6
; CHECK-MVEFP-NEXT: strd r2, r1, [r0, #16]
; CHECK-MVEFP-NEXT: vstrw.32 q0, [r0]
; CHECK-MVEFP-NEXT: bx lr
@@ -208,10 +207,9 @@ define arm_aapcs_vfpcc <7 x i32> @test_unsigned_v7f32_v7i32(<7 x float> %f) {
; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vcvt.u32.f32 q1, q1
; CHECK-MVEFP-NEXT: vcvt.u32.f32 q0, q0
-; CHECK-MVEFP-NEXT: vmov.f32 s10, s5
+; CHECK-MVEFP-NEXT: vmov r1, s5
; CHECK-MVEFP-NEXT: vmov r2, s4
; CHECK-MVEFP-NEXT: vmov r3, s6
-; CHECK-MVEFP-NEXT: vmov r1, s10
; CHECK-MVEFP-NEXT: strd r2, r1, [r0, #16]
; CHECK-MVEFP-NEXT: str r3, [r0, #24]
; CHECK-MVEFP-NEXT: vstrw.32 q0, [r0]
diff --git a/llvm/test/CodeGen/Thumb2/mve-laneinterleaving-cost.ll b/llvm/test/CodeGen/Thumb2/mve-laneinterleaving-cost.ll
index 7be08b04c5957..577c78309cd48 100644
--- a/llvm/test/CodeGen/Thumb2/mve-laneinterleaving-cost.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-laneinterleaving-cost.ll
@@ -4,54 +4,51 @@
define arm_aapcs_vfpcc <4 x i32> @loads_i32(ptr %A, ptr %B, ptr %C) {
; CHECK-LABEL: loads_i32:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: .save {r4, r5, r6, lr}
-; CHECK-NEXT: push {r4, r5, r6, lr}
-; CHECK-NEXT: vldrw.u32 q2, [r1]
-; CHECK-NEXT: vmov.i64 q1, #0xffffffff
-; CHECK-NEXT: vmov.f32 s0, s10
-; CHECK-NEXT: vmov.f32 s2, s11
-; CHECK-NEXT: vand q0, q0, q1
-; CHECK-NEXT: vmov.f32 s10, s9
-; CHECK-NEXT: vmov r1, r3, d0
-; CHECK-NEXT: vand q2, q2, q1
-; CHECK-NEXT: vmov r4, r5, d1
-; CHECK-NEXT: vldrw.u32 q0, [r0]
-; CHECK-NEXT: vldrw.u32 q1, [r2]
-; CHECK-NEXT: vmov lr, r12, d5
-; CHECK-NEXT: vmov.f32 s12, s2
-; CHECK-NEXT: vmov.f32 s2, s3
-; CHECK-NEXT: vmov r0, s12
-; CHECK-NEXT: vmov.f32 s12, s6
-; CHECK-NEXT: vmov.f32 s6, s7
-; CHECK-NEXT: asrs r2, r0, #31
-; CHECK-NEXT: adds r0, r0, r1
-; CHECK-NEXT: adc.w r1, r2, r3
-; CHECK-NEXT: vmov r2, s12
-; CHECK-NEXT: asrl r0, r1, r2
-; CHECK-NEXT: vmov r1, s2
-; CHECK-NEXT: vmov.f32 s2, s1
-; CHECK-NEXT: adds r2, r1, r4
-; CHECK-NEXT: asr.w r3, r1, #31
-; CHECK-NEXT: adc.w r1, r3, r5
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: vldrw.u32 q3, [r1]
+; CHECK-NEXT: vldrw.u32 q1, [r0]
+; CHECK-NEXT: vmov.i64 q2, #0xffffffff
+; CHECK-NEXT: vmov.f32 s0, s12
+; CHECK-NEXT: vmov.f32 s2, s13
+; CHECK-NEXT: vmov lr, r0, d2
+; CHECK-NEXT: vand q0, q0, q2
+; CHECK-NEXT: vmov r1, r5, d1
+; CHECK-NEXT: vmov.f32 s12, s14
+; CHECK-NEXT: vmov.f32 s14, s15
+; CHECK-NEXT: vand q2, q3, q2
+; CHECK-NEXT: vmov r4, r3, d5
+; CHECK-NEXT: asrs r6, r0, #31
+; CHECK-NEXT: adds.w r12, r0, r1
+; CHECK-NEXT: vmov r0, s7
+; CHECK-NEXT: adc.w r1, r6, r5
+; CHECK-NEXT: adds.w r8, r0, r4
+; CHECK-NEXT: vmov r4, r6, d4
+; CHECK-NEXT: asr.w r5, r0, #31
+; CHECK-NEXT: adcs r5, r3
; CHECK-NEXT: vmov r3, s6
-; CHECK-NEXT: asrl r2, r1, r3
-; CHECK-NEXT: vmov r4, r5, d4
-; CHECK-NEXT: vmov r1, s2
-; CHECK-NEXT: vmov.f32 s2, s5
-; CHECK-NEXT: adds.w r6, r1, lr
-; CHECK-NEXT: asr.w r3, r1, #31
-; CHECK-NEXT: adc.w r1, r3, r12
-; CHECK-NEXT: vmov r3, s2
-; CHECK-NEXT: asrl r6, r1, r3
-; CHECK-NEXT: vmov r1, s0
-; CHECK-NEXT: adds r4, r4, r1
-; CHECK-NEXT: asr.w r3, r1, #31
-; CHECK-NEXT: adc.w r1, r3, r5
-; CHECK-NEXT: vmov r3, s4
-; CHECK-NEXT: asrl r4, r1, r3
-; CHECK-NEXT: vmov q0[2], q0[0], r4, r0
-; CHECK-NEXT: vmov q0[3], q0[1], r6, r2
-; CHECK-NEXT: pop {r4, r5, r6, pc}
+; CHECK-NEXT: vldrw.u32 q1, [r2]
+; CHECK-NEXT: vmov.f32 s8, s6
+; CHECK-NEXT: vmov.f32 s2, s7
+; CHECK-NEXT: vmov.f32 s6, s5
+; CHECK-NEXT: vmov r2, s8
+; CHECK-NEXT: adds r4, r4, r3
+; CHECK-NEXT: asr.w r7, r3, #31
+; CHECK-NEXT: adc.w r3, r7, r6
+; CHECK-NEXT: asrl r4, r3, r2
+; CHECK-NEXT: asr.w r2, lr, #31
+; CHECK-NEXT: vmov r3, r6, d0
+; CHECK-NEXT: adds.w r0, lr, r3
+; CHECK-NEXT: adc.w r3, r2, r6
+; CHECK-NEXT: vmov r2, s4
+; CHECK-NEXT: asrl r0, r3, r2
+; CHECK-NEXT: vmov r2, s2
+; CHECK-NEXT: vmov q0[2], q0[0], r0, r4
+; CHECK-NEXT: vmov r0, s6
+; CHECK-NEXT: asrl r8, r5, r2
+; CHECK-NEXT: asrl r12, r1, r0
+; CHECK-NEXT: vmov q0[3], q0[1], r12, r8
+; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, pc}
entry:
%a = load <4 x i32>, ptr %A, align 4
%b = load <4 x i32>, ptr %B, align 4
@@ -134,58 +131,51 @@ entry:
define arm_aapcs_vfpcc void @load_store_i32(ptr %A, ptr %B, ptr %C, ptr %D) {
; CHECK-LABEL: load_store_i32:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
-; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr}
-; CHECK-NEXT: .vsave {d8, d9}
-; CHECK-NEXT: vpush {d8, d9}
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr}
+; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r11, lr}
; CHECK-NEXT: vldrw.u32 q1, [r1]
; CHECK-NEXT: vmov.i64 q0, #0xffffffff
; CHECK-NEXT: vmov.f32 s8, s6
; CHECK-NEXT: vmov.f32 s10, s7
+; CHECK-NEXT: vand q2, q2, q0
; CHECK-NEXT: vmov.f32 s6, s5
-; CHECK-NEXT: vand q4, q2, q0
-; CHECK-NEXT: vand q2, q1, q0
-; CHECK-NEXT: vldrw.u32 q0, [r0]
-; CHECK-NEXT: vmov r4, r5, d9
+; CHECK-NEXT: vmov r1, r12, d5
+; CHECK-NEXT: vand q0, q1, q0
+; CHECK-NEXT: vmov lr, r4, d4
+; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vldrw.u32 q1, [r2]
-; CHECK-NEXT: vmov.f32 s12, s2
-; CHECK-NEXT: vmov.f32 s2, s3
-; CHECK-NEXT: vmov lr, r12, d8
-; CHECK-NEXT: vmov.f32 s16, s6
-; CHECK-NEXT: vmov.f32 s6, s7
-; CHECK-NEXT: vmov r6, r1, d5
-; CHECK-NEXT: vmov.f32 s10, s1
-; CHECK-NEXT: vmov r0, s2
-; CHECK-NEXT: vmov.f32 s2, s5
-; CHECK-NEXT: adds.w r8, r0, r4
-; CHECK-NEXT: asr.w r2, r0, #31
-; CHECK-NEXT: adcs r5, r2
-; CHECK-NEXT: vmov r2, s6
-; CHECK-NEXT: asrl r8, r5, r2
+; CHECK-NEXT: vmov r9, r8, d0
+; CHECK-NEXT: vmov r0, s11
+; CHECK-NEXT: vmov.f32 s0, s6
+; CHECK-NEXT: vmov.f32 s6, s5
+; CHECK-NEXT: asrs r2, r0, #31
+; CHECK-NEXT: adds r0, r0, r1
+; CHECK-NEXT: adc.w r11, r2, r12
; CHECK-NEXT: vmov r2, s10
-; CHECK-NEXT: vmov r5, r7, d4
-; CHECK-NEXT: asrs r4, r2, #31
-; CHECK-NEXT: adds r2, r2, r6
-; CHECK-NEXT: adcs r1, r4
-; CHECK-NEXT: vmov r4, s2
-; CHECK-NEXT: asrl r2, r1, r4
-; CHECK-NEXT: vmov r1, s12
-; CHECK-NEXT: adds.w r6, r1, lr
-; CHECK-NEXT: asr.w r4, r1, #31
-; CHECK-NEXT: adc.w r1, r4, r12
-; CHECK-NEXT: vmov r4, s16
-; CHECK-NEXT: asrl r6, r1, r4
-; CHECK-NEXT: vmov r1, s0
-; CHECK-NEXT: adds r0, r1, r5
-; CHECK-NEXT: asr.w r4, r1, #31
-; CHECK-NEXT: adc.w r1, r4, r7
-; CHECK-NEXT: vmov r7, s4
-; CHECK-NEXT: asrl r0, r1, r7
-; CHECK-NEXT: vmov q0[2], q0[0], r0, r6
-; CHECK-NEXT: vmov q0[3], q0[1], r2, r8
+; CHECK-NEXT: vmov.f32 s10, s7
+; CHECK-NEXT: asrs r6, r2, #31
+; CHECK-NEXT: adds.w r2, r2, lr
+; CHECK-NEXT: adc.w r7, r6, r4
+; CHECK-NEXT: vmov r4, r5, d4
+; CHECK-NEXT: vmov r6, s0
+; CHECK-NEXT: asrl r2, r7, r6
+; CHECK-NEXT: adds.w r6, r4, r9
+; CHECK-NEXT: asr.w r7, r4, #31
+; CHECK-NEXT: vmov r4, s4
+; CHECK-NEXT: adc.w r7, r7, r8
+; CHECK-NEXT: asrl r6, r7, r4
+; CHECK-NEXT: vmov r4, r1, d1
+; CHECK-NEXT: vmov q0[2], q0[0], r6, r2
+; CHECK-NEXT: asrs r2, r5, #31
+; CHECK-NEXT: vmov r7, s10
+; CHECK-NEXT: asrl r0, r11, r7
+; CHECK-NEXT: adds r6, r5, r4
+; CHECK-NEXT: adcs r1, r2
+; CHECK-NEXT: vmov r2, s6
+; CHECK-NEXT: asrl r6, r1, r2
+; CHECK-NEXT: vmov q0[3], q0[1], r6, r0
; CHECK-NEXT: vstrw.32 q0, [r3]
-; CHECK-NEXT: vpop {d8, d9}
-; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, pc}
+; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r11, pc}
entry:
%a = load <4 x i32>, ptr %A, align 4
%b = load <4 x i32>, ptr %B, align 4
@@ -268,36 +258,32 @@ entry:
define arm_aapcs_vfpcc void @load_one_store_i32(ptr %A, ptr %D) {
; CHECK-LABEL: load_one_store_i32:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: .save {r4, r5, r6, lr}
-; CHECK-NEXT: push {r4, r5, r6, lr}
+; CHECK-NEXT: .save {r4, r5, r6, r7, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, lr}
; CHECK-NEXT: vldrw.u32 q0, [r0]
-; CHECK-NEXT: vmov.f32 s4, s2
-; CHECK-NEXT: vmov.f32 s2, s3
-; CHECK-NEXT: vmov r2, s2
-; CHECK-NEXT: vmov.f32 s2, s1
-; CHECK-NEXT: adds.w r12, r2, r2
-; CHECK-NEXT: asr.w r3, r2, #31
-; CHECK-NEXT: adc.w r3, r3, r2, asr #31
-; CHECK-NEXT: asrl r12, r3, r2
-; CHECK-NEXT: vmov r3, s2
-; CHECK-NEXT: adds r2, r3, r3
+; CHECK-NEXT: vmov r0, s3
+; CHECK-NEXT: vmov r2, r3, d0
+; CHECK-NEXT: adds.w r12, r0, r0
+; CHECK-NEXT: asr.w lr, r0, #31
+; CHECK-NEXT: adc.w r5, lr, r0, asr #31
+; CHECK-NEXT: asrl r12, r5, r0
+; CHECK-NEXT: vmov r0, s2
+; CHECK-NEXT: asr.w lr, r2, #31
+; CHECK-NEXT: adds r4, r0, r0
+; CHECK-NEXT: asr.w r5, r0, #31
+; CHECK-NEXT: adc.w r5, r5, r0, asr #31
+; CHECK-NEXT: adds r6, r3, r3
+; CHECK-NEXT: asrl r4, r5, r0
; CHECK-NEXT: asr.w r0, r3, #31
; CHECK-NEXT: adc.w r5, r0, r3, asr #31
-; CHECK-NEXT: vmov r0, s4
-; CHECK-NEXT: asrl r2, r5, r3
-; CHECK-NEXT: adds r4, r0, r0
-; CHECK-NEXT: asr.w r3, r0, #31
-; CHECK-NEXT: adc.w r3, r3, r0, asr #31
-; CHECK-NEXT: asrl r4, r3, r0
-; CHECK-NEXT: vmov r0, s0
-; CHECK-NEXT: adds r6, r0, r0
-; CHECK-NEXT: asr.w r3, r0, #31
-; CHECK-NEXT: adc.w r3, r3, r0, asr #31
-; CHECK-NEXT: asrl r6, r3, r0
-; CHECK-NEXT: vmov q0[2], q0[0], r6, r4
-; CHECK-NEXT: vmov q0[3], q0[1], r2, r12
+; CHECK-NEXT: adds r0, r2, r2
+; CHECK-NEXT: adc.w r7, lr, r2, asr #31
+; CHECK-NEXT: asrl r6, r5, r3
+; CHECK-NEXT: asrl r0, r7, r2
+; CHECK-NEXT: vmov q0[2], q0[0], r0, r4
+; CHECK-NEXT: vmov q0[3], q0[1], r6, r12
; CHECK-NEXT: vstrw.32 q0, [r1]
-; CHECK-NEXT: pop {r4, r5, r6, pc}
+; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
entry:
%a = load <4 x i32>, ptr %A, align 4
%sa = sext <4 x i32> %a to <4 x i64>
diff --git a/llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll b/llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
index 5972a9a7cf934..40d534a0ebfc5 100644
--- a/llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
@@ -474,7 +474,6 @@ define arm_aapcs_vfpcc void @ssatmul_4t_q31(ptr nocapture readonly %pSrcA, ptr n
; CHECK-NEXT: vmov.f32 s28, s22
; CHECK-NEXT: vmov.f32 s30, s23
; CHECK-NEXT: vmullb.s32 q0, q7, q6
-; CHECK-NEXT: vmov.f32 s18, s21
; CHECK-NEXT: vmov r10, r5, d0
; CHECK-NEXT: asrl r10, r5, #31
; CHECK-NEXT: rsbs.w r7, r10, #-2147483648
@@ -488,7 +487,7 @@ define arm_aapcs_vfpcc void @ssatmul_4t_q31(ptr nocapture readonly %pSrcA, ptr n
; CHECK-NEXT: sbcs.w r3, r12, r7
; CHECK-NEXT: vmov q0[3], q0[1], r5, r7
; CHECK-NEXT: csetm r3, lt
-; CHECK-NEXT: vmov r7, s18
+; CHECK-NEXT: vmov r7, s21
; CHECK-NEXT: bfi r4, r3, #8, #8
; CHECK-NEXT: vmsr p0, r4
; CHECK-NEXT: vpsel q0, q0, q2
@@ -507,7 +506,6 @@ define arm_aapcs_vfpcc void @ssatmul_4t_q31(ptr nocapture readonly %pSrcA, ptr n
; CHECK-NEXT: vmsr p0, r4
; CHECK-NEXT: vmov r4, s20
; CHECK-NEXT: vpsel q6, q0, q3
-; CHECK-NEXT: vmov.f32 s2, s17
; CHECK-NEXT: smull r10, r5, r4, r3
; CHECK-NEXT: movs r4, #0
; CHECK-NEXT: asrl r10, r5, #31
@@ -515,7 +513,7 @@ define arm_aapcs_vfpcc void @ssatmul_4t_q31(ptr nocapture readonly %pSrcA, ptr n
; CHECK-NEXT: sbcs.w r3, r12, r5
; CHECK-NEXT: csetm r3, lt
; CHECK-NEXT: bfi r4, r3, #0, #8
-; CHECK-NEXT: vmov r3, s2
+; CHECK-NEXT: vmov r3, s17
; CHECK-NEXT: smull r6, r3, r7, r3
; CHECK-NEXT: asrl r6, r3, #31
; CHECK-NEXT: rsbs.w r7, r6, #-2147483648
diff --git a/llvm/test/CodeGen/Thumb2/mve-sext-masked-load.ll b/llvm/test/CodeGen/Thumb2/mve-sext-masked-load.ll
index 05f438acc3a7e..84db3e635c7fc 100644
--- a/llvm/test/CodeGen/Thumb2/mve-sext-masked-load.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-sext-masked-load.ll
@@ -51,41 +51,36 @@ entry:
define arm_aapcs_vfpcc <4 x double> @foo_v4i32(ptr nocapture readonly %pSrc, i32 %blockSize, <4 x i32> %a) {
; CHECK-LABEL: foo_v4i32:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: .save {r7, lr}
-; CHECK-NEXT: push {r7, lr}
+; CHECK-NEXT: .save {r4, r5, r7, lr}
+; CHECK-NEXT: push {r4, r5, r7, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vpt.s32 lt, q0, zr
-; CHECK-NEXT: vldrwt.u32 q5, [r0]
-; CHECK-NEXT: vmov.f32 s2, s23
-; CHECK-NEXT: vmov.f32 s16, s22
-; CHECK-NEXT: vmov r0, s2
+; CHECK-NEXT: vldrwt.u32 q4, [r0]
+; CHECK-NEXT: vmov r0, s19
; CHECK-NEXT: asrs r1, r0, #31
; CHECK-NEXT: bl __aeabi_l2d
-; CHECK-NEXT: vmov r2, s16
+; CHECK-NEXT: vmov r2, s18
; CHECK-NEXT: vmov d9, r0, r1
+; CHECK-NEXT: vmov r4, r5, d8
; CHECK-NEXT: asrs r3, r2, #31
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: mov r1, r3
; CHECK-NEXT: bl __aeabi_l2d
-; CHECK-NEXT: vmov.f32 s2, s21
; CHECK-NEXT: vmov d8, r0, r1
-; CHECK-NEXT: vmov r2, s2
-; CHECK-NEXT: asrs r3, r2, #31
-; CHECK-NEXT: mov r0, r2
-; CHECK-NEXT: mov r1, r3
+; CHECK-NEXT: asrs r1, r5, #31
+; CHECK-NEXT: mov r0, r5
; CHECK-NEXT: bl __aeabi_l2d
-; CHECK-NEXT: vmov r2, s20
+; CHECK-NEXT: asrs r2, r4, #31
; CHECK-NEXT: vmov d11, r0, r1
-; CHECK-NEXT: asrs r3, r2, #31
-; CHECK-NEXT: mov r0, r2
-; CHECK-NEXT: mov r1, r3
+; CHECK-NEXT: mov r0, r4
+; CHECK-NEXT: mov r1, r2
; CHECK-NEXT: bl __aeabi_l2d
; CHECK-NEXT: vmov d10, r0, r1
; CHECK-NEXT: vmov q1, q4
; CHECK-NEXT: vmov q0, q5
; CHECK-NEXT: vpop {d8, d9, d10, d11}
-; CHECK-NEXT: pop {r7, pc}
+; CHECK-NEXT: pop {r4, r5, r7, pc}
entry:
%active.lane.mask = icmp slt <4 x i32> %a, zeroinitializer
%wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %pSrc, i32 4, <4 x i1> %active.lane.mask, <4 x i32> undef)
diff --git a/llvm/test/CodeGen/Thumb2/mve-shuffle.ll b/llvm/test/CodeGen/Thumb2/mve-shuffle.ll
index 7f624cffa014c..d01734e3c1358 100644
--- a/llvm/test/CodeGen/Thumb2/mve-shuffle.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-shuffle.ll
@@ -1363,66 +1363,39 @@ entry:
define arm_aapcs_vfpcc <8 x half> @shuffle3step_f16(<32 x half> %src) {
; CHECKFP16-LABEL: shuffle3step_f16:
; CHECKFP16: @ %bb.0: @ %entry
-; CHECKFP16-NEXT: .vsave {d8, d9, d10, d11}
-; CHECKFP16-NEXT: vpush {d8, d9, d10, d11}
-; CHECKFP16-NEXT: vmovx.f16 s13, s1
-; CHECKFP16-NEXT: vmovx.f16 s16, s0
-; CHECKFP16-NEXT: vins.f16 s0, s13
-; CHECKFP16-NEXT: vmovx.f16 s13, s4
-; CHECKFP16-NEXT: vmovx.f16 s15, s3
-; CHECKFP16-NEXT: vins.f16 s3, s13
-; CHECKFP16-NEXT: vmov q5, q0
-; CHECKFP16-NEXT: vins.f16 s16, s2
-; CHECKFP16-NEXT: vmovx.f16 s2, s2
-; CHECKFP16-NEXT: vmovx.f16 s14, s6
-; CHECKFP16-NEXT: vins.f16 s1, s2
-; CHECKFP16-NEXT: vmovx.f16 s2, s5
-; CHECKFP16-NEXT: vmovx.f16 s18, s16
-; CHECKFP16-NEXT: vmovx.f16 s0, s20
-; CHECKFP16-NEXT: vins.f16 s4, s2
-; CHECKFP16-NEXT: vins.f16 s14, s8
-; CHECKFP16-NEXT: vmovx.f16 s2, s8
-; CHECKFP16-NEXT: vadd.f16 s0, s0, s18
-; CHECKFP16-NEXT: vmovx.f16 s8, s1
-; CHECKFP16-NEXT: vins.f16 s15, s5
-; CHECKFP16-NEXT: vadd.f16 s8, s0, s8
-; CHECKFP16-NEXT: vadd.f16 s0, s20, s16
-; CHECKFP16-NEXT: vadd.f16 s0, s0, s1
-; CHECKFP16-NEXT: vmovx.f16 s1, s3
-; CHECKFP16-NEXT: vins.f16 s0, s8
+; CHECKFP16-NEXT: vmov q3, q0
+; CHECKFP16-NEXT: vmovx.f16 s0, s6
+; CHECKFP16-NEXT: vadd.f16 s0, s6, s0
+; CHECKFP16-NEXT: vmovx.f16 s6, s14
+; CHECKFP16-NEXT: vadd.f16 s2, s0, s...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/196263
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