[llvm] [SystemZ] Fold i16/i32/i64 logical RMW operations into memory operands in TableGen (PR #192802)

[Ulrich Weigand via llvm-commits]

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@@ -696,3 +696,46 @@ def cond4 : PatLeaf<(i32 timm), [{ return (N->getZExtValue() < 16); }]>,
   let PrintMethod = "printCond4Operand";
   let OperandType = "OPERAND_IMMEDIATE";
 }
+
+// Extracts the base register from the load node.
+def get_base_from_load : SDNodeXForm<ld, [{
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uweigand wrote:

All these operators (partially) duplicate the address handling code in `selectAddress` and friends.  It would be nicer if we could extend those routines to handle offset addresses, similar to what we already do to support LX/STX via the `bdxaddr20only128` operator.

Maybe we can provide operators like `bdxaddr20off1` etc. that parse an address and return it after adding the given offset.

https://github.com/llvm/llvm-project/pull/192802