[llvm] [AArch64][Isel] For fixed lenght vectors use sve for bitreverse when available (PR #196025)

[Ricardo Jesus via llvm-commits]

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@@ -1332,6 +1332,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
       setOperationAction(ISD::CTLS, VT, Legal);
     setOperationAction(ISD::BITREVERSE, MVT::v8i8, Legal);
     setOperationAction(ISD::BITREVERSE, MVT::v16i8, Legal);
+    setOperationAction(ISD::BITREVERSE, MVT::v4i16, Custom);
+    setOperationAction(ISD::BITREVERSE, MVT::v8i16, Custom);
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rj-jesus wrote:

Rather than adding these here, I think you could have something like:
```
for (auto VT : {MVT::v4i16, MVT::v8i16, MVT::v2i32, MVT::v4i32, MVT::v1i64,
                MVT::v2i64})
  setOperationAction(ISD::BITREVERSE, VT, Custom);
```
Inside the `if (Subtarget->isSVEorStreamingSVEAvailable())` below, similar to what's done for 64-bit multiplies and MULH near https://github.com/llvm/llvm-project/blob/272c8c7d00050920f38f437837de60cee838a8cf/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp#L1922. Perhaps there's a better way of doing this, but with a change like this I believe you should no longer need the new lowering code for i16 vectors.

https://github.com/llvm/llvm-project/pull/196025