[llvm] [AArch64][Isel] For fixed lenght vectors use sve for bitreverse when available (PR #196025)

[Ricardo Jesus via llvm-commits]

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@@ -11832,6 +11834,20 @@ SDValue AArch64TargetLowering::LowerBitreverse(SDValue Op,
   default:
     llvm_unreachable("Invalid type for bitreverse!");
 
+  case MVT::v4i16: {
+    SDValue Bswap = DAG.getNode(ISD::BSWAP, DL, VT, Op.getOperand(0));
+    VST = MVT::v8i8;
+    REVB = DAG.getBitcast(VST, Bswap);
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rj-jesus wrote:

I think this should be AArch64ISD::NVCAST, otherwise it emits a bswap on BE targets that cancels out with the one above.

https://github.com/llvm/llvm-project/pull/196025