[llvm] [AMDGPU] Add VOP3 encoding for gfx13 (PR #196258)
via llvm-commits
llvm-commits at lists.llvm.org
Thu May 7 01:27:40 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Mariusz Sikora (mariusz-sikora-at-amd)
<details>
<summary>Changes</summary>
---
Patch is 2.44 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/196258.diff
16 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp (+33-3)
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.td (+1)
- (modified) llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp (+5-1)
- (modified) llvm/lib/Target/AMDGPU/VOP2Instructions.td (+30-24)
- (modified) llvm/lib/Target/AMDGPU/VOP3Instructions.td (+265-224)
- (modified) llvm/lib/Target/AMDGPU/VOPInstructions.td (+166-52)
- (added) llvm/test/MC/AMDGPU/gfx13_asm_vop3-fake16.s (+8182)
- (added) llvm/test/MC/AMDGPU/gfx13_asm_vop3.s (+8195)
- (added) llvm/test/MC/AMDGPU/gfx13_asm_vop3_aliases.s (+54)
- (added) llvm/test/MC/AMDGPU/gfx13_asm_vop3_dpp16-fake16.s (+5574)
- (added) llvm/test/MC/AMDGPU/gfx13_asm_vop3_dpp16.s (+5587)
- (added) llvm/test/MC/AMDGPU/gfx13_asm_vop3_dpp8-fake16.s (+3520)
- (added) llvm/test/MC/AMDGPU/gfx13_asm_vop3_dpp8.s (+3524)
- (added) llvm/test/MC/AMDGPU/gfx13_asm_vop3_from_vop1-fake16.s (+4106)
- (added) llvm/test/MC/AMDGPU/gfx13_asm_vop3_from_vop1_dpp16-fake16.s (+297)
- (added) llvm/test/MC/AMDGPU/gfx13_asm_vop3_from_vop1_dpp8-fake16.s (+87)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index f22f5f3f9841f..37076dbe3539d 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -9594,7 +9594,9 @@ void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands,
Opc == AMDGPU::V_CVT_SR_BF8_F32_gfx12_e64_gfx11 ||
Opc == AMDGPU::V_CVT_SR_FP8_F32_gfx12_e64_gfx11 ||
Opc == AMDGPU::V_CVT_SR_BF8_F32_gfx12_e64_gfx12 ||
- Opc == AMDGPU::V_CVT_SR_FP8_F32_gfx12_e64_gfx12) {
+ Opc == AMDGPU::V_CVT_SR_FP8_F32_gfx12_e64_gfx12 ||
+ Opc == AMDGPU::V_CVT_SR_BF8_F32_gfx12_e64_gfx13 ||
+ Opc == AMDGPU::V_CVT_SR_FP8_F32_gfx12_e64_gfx13) {
Inst.addOperand(MCOperand::createImm(0)); // Placeholder for src2_mods
Inst.addOperand(Inst.getOperand(0));
}
@@ -9622,24 +9624,48 @@ void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands,
Opc == AMDGPU::V_CVT_PK_FP8_F32_fake16_e64_dpp_gfx12 ||
Opc == AMDGPU::V_CVT_PK_BF8_F32_fake16_e64_dpp8_gfx12 ||
Opc == AMDGPU::V_CVT_PK_FP8_F32_fake16_e64_dpp8_gfx12 ||
+ Opc == AMDGPU::V_CVT_PK_BF8_F32_t16_e64_dpp_gfx13 ||
+ Opc == AMDGPU::V_CVT_PK_FP8_F32_t16_e64_dpp_gfx13 ||
+ Opc == AMDGPU::V_CVT_PK_BF8_F32_t16_e64_dpp8_gfx13 ||
+ Opc == AMDGPU::V_CVT_PK_FP8_F32_t16_e64_dpp8_gfx13 ||
+ Opc == AMDGPU::V_CVT_PK_BF8_F32_fake16_e64_dpp_gfx13 ||
+ Opc == AMDGPU::V_CVT_PK_FP8_F32_fake16_e64_dpp_gfx13 ||
+ Opc == AMDGPU::V_CVT_PK_BF8_F32_fake16_e64_dpp8_gfx13 ||
+ Opc == AMDGPU::V_CVT_PK_FP8_F32_fake16_e64_dpp8_gfx13 ||
Opc == AMDGPU::V_CVT_SR_FP8_F32_gfx12_e64_dpp_gfx12 ||
+ Opc == AMDGPU::V_CVT_SR_FP8_F32_gfx12_e64_dpp_gfx13 ||
Opc == AMDGPU::V_CVT_SR_FP8_F32_gfx12_e64_dpp8_gfx12 ||
+ Opc == AMDGPU::V_CVT_SR_FP8_F32_gfx12_e64_dpp8_gfx13 ||
Opc == AMDGPU::V_CVT_SR_FP8_F32_gfx1250_e64_dpp_gfx1250 ||
Opc == AMDGPU::V_CVT_SR_FP8_F32_gfx1250_e64_dpp8_gfx1250 ||
Opc == AMDGPU::V_CVT_SR_BF8_F32_gfx12_e64_dpp_gfx12 ||
+ Opc == AMDGPU::V_CVT_SR_BF8_F32_gfx12_e64_dpp_gfx13 ||
Opc == AMDGPU::V_CVT_SR_BF8_F32_gfx12_e64_dpp8_gfx12 ||
+ Opc == AMDGPU::V_CVT_SR_BF8_F32_gfx12_e64_dpp8_gfx13 ||
Opc == AMDGPU::V_CVT_SR_FP8_F16_t16_e64_dpp_gfx1250 ||
Opc == AMDGPU::V_CVT_SR_FP8_F16_fake16_e64_dpp_gfx1250 ||
+ Opc == AMDGPU::V_CVT_SR_FP8_F16_t16_e64_dpp_gfx13 ||
+ Opc == AMDGPU::V_CVT_SR_FP8_F16_fake16_e64_dpp_gfx13 ||
Opc == AMDGPU::V_CVT_SR_FP8_F16_t16_e64_dpp8_gfx1250 ||
Opc == AMDGPU::V_CVT_SR_FP8_F16_fake16_e64_dpp8_gfx1250 ||
+ Opc == AMDGPU::V_CVT_SR_FP8_F16_t16_e64_dpp8_gfx13 ||
+ Opc == AMDGPU::V_CVT_SR_FP8_F16_fake16_e64_dpp8_gfx13 ||
Opc == AMDGPU::V_CVT_SR_FP8_F16_t16_e64_gfx1250 ||
Opc == AMDGPU::V_CVT_SR_FP8_F16_fake16_e64_gfx1250 ||
+ Opc == AMDGPU::V_CVT_SR_FP8_F16_t16_e64_gfx13 ||
+ Opc == AMDGPU::V_CVT_SR_FP8_F16_fake16_e64_gfx13 ||
Opc == AMDGPU::V_CVT_SR_BF8_F16_t16_e64_dpp_gfx1250 ||
Opc == AMDGPU::V_CVT_SR_BF8_F16_fake16_e64_dpp_gfx1250 ||
+ Opc == AMDGPU::V_CVT_SR_BF8_F16_t16_e64_dpp_gfx13 ||
+ Opc == AMDGPU::V_CVT_SR_BF8_F16_fake16_e64_dpp_gfx13 ||
Opc == AMDGPU::V_CVT_SR_BF8_F16_t16_e64_dpp8_gfx1250 ||
Opc == AMDGPU::V_CVT_SR_BF8_F16_fake16_e64_dpp8_gfx1250 ||
+ Opc == AMDGPU::V_CVT_SR_BF8_F16_t16_e64_dpp8_gfx13 ||
+ Opc == AMDGPU::V_CVT_SR_BF8_F16_fake16_e64_dpp8_gfx13 ||
Opc == AMDGPU::V_CVT_SR_BF8_F16_t16_e64_gfx1250 ||
- Opc == AMDGPU::V_CVT_SR_BF8_F16_fake16_e64_gfx1250)) {
+ Opc == AMDGPU::V_CVT_SR_BF8_F16_fake16_e64_gfx1250 ||
+ Opc == AMDGPU::V_CVT_SR_BF8_F16_t16_e64_gfx13 ||
+ Opc == AMDGPU::V_CVT_SR_BF8_F16_fake16_e64_gfx13)) {
Inst.addOperand(Inst.getOperand(0));
}
@@ -10203,9 +10229,13 @@ void AMDGPUAsmParser::cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands,
int Fi = 0;
int VdstInIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst_in);
bool IsVOP3CvtSrDpp = Opc == AMDGPU::V_CVT_SR_BF8_F32_gfx12_e64_dpp8_gfx12 ||
+ Opc == AMDGPU::V_CVT_SR_BF8_F32_gfx12_e64_dpp8_gfx13 ||
Opc == AMDGPU::V_CVT_SR_FP8_F32_gfx12_e64_dpp8_gfx12 ||
+ Opc == AMDGPU::V_CVT_SR_FP8_F32_gfx12_e64_dpp8_gfx13 ||
Opc == AMDGPU::V_CVT_SR_BF8_F32_gfx12_e64_dpp_gfx12 ||
- Opc == AMDGPU::V_CVT_SR_FP8_F32_gfx12_e64_dpp_gfx12;
+ Opc == AMDGPU::V_CVT_SR_BF8_F32_gfx12_e64_dpp_gfx13 ||
+ Opc == AMDGPU::V_CVT_SR_FP8_F32_gfx12_e64_dpp_gfx12 ||
+ Opc == AMDGPU::V_CVT_SR_FP8_F32_gfx12_e64_dpp_gfx13;
for (unsigned E = Operands.size(); I != E; ++I) {
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index 7c3aff9c9f47f..90b5f7b0b794b 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -3095,6 +3095,7 @@ def VOP_V2BF16_F32_F32_I32 : VOPProfile <[v2bf16, f32, f32, i32]>;
def VOP_V2F16_F32_F32_I32 : VOPProfile <[v2f16, f32, f32, i32]>;
def VOP_V6I32_V32F16_F32 : VOPProfile<[v6i32, v32f16, f32, untyped]>;
def VOP_V6I32_V32BF16_F32 : VOPProfile<[v6i32, v32bf16, f32, untyped]>;
+def VOP_V6I32_V32F32_F32 : VOPProfile<[v6i32, v32f32, f32, untyped]>;
def VOP_V3I32_V16F16_F32 : VOPProfile<[v3i32, v16f16, f32, untyped]>;
def VOP_V3I32_V16BF16_F32 : VOPProfile<[v3i32, v16bf16, f32, untyped]>;
def VOP_V3I32_V16F32_F32 : VOPProfile<[v3i32, v16f32, f32, untyped]>;
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index 1c145359ccc61..ed48e52fdea13 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -724,9 +724,13 @@ bool isPermlane16(unsigned Opc) {
Opc == AMDGPU::V_PERMLANE16_B32_e64_gfx11 ||
Opc == AMDGPU::V_PERMLANEX16_B32_e64_gfx11 ||
Opc == AMDGPU::V_PERMLANE16_B32_e64_gfx12 ||
+ Opc == AMDGPU::V_PERMLANE16_B32_e64_gfx13 ||
Opc == AMDGPU::V_PERMLANEX16_B32_e64_gfx12 ||
+ Opc == AMDGPU::V_PERMLANEX16_B32_e64_gfx13 ||
Opc == AMDGPU::V_PERMLANE16_VAR_B32_e64_gfx12 ||
- Opc == AMDGPU::V_PERMLANEX16_VAR_B32_e64_gfx12;
+ Opc == AMDGPU::V_PERMLANE16_VAR_B32_e64_gfx13 ||
+ Opc == AMDGPU::V_PERMLANEX16_VAR_B32_e64_gfx12 ||
+ Opc == AMDGPU::V_PERMLANEX16_VAR_B32_e64_gfx13;
}
bool isCvt_F32_Fp8_Bf8_e64(unsigned Opc) {
diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
index 96737e5e61020..ea2681846e0d6 100644
--- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
@@ -1977,23 +1977,29 @@ multiclass VOP2_Real_FULL_with_name_gfx1170<bits<6> op, string opName,
string asmName> :
VOP2_Real_FULL_with_name<GFX1170Gen, op, opName, asmName>;
+multiclass VOP3Only_Realtriple_gfx11_gfx12_gfx13<
+ bits<10> preGFX13Op, bits<10> op = preGFX13Op> :
+ VOP3Only_Realtriple<GFX11Gen, preGFX13Op>,
+ VOP3Only_Realtriple<GFX12Gen, preGFX13Op>,
+ VOP3Only_Realtriple<GFX13Gen, op>;
+
multiclass VOP2_Real_e32_gfx11_gfx12<bits<6> op> :
VOP2Only_Real_e32<GFX11Gen, op>, VOP2Only_Real_e32<GFX12Gen, op>;
-multiclass VOP3Only_Realtriple_gfx11_gfx12<bits<10> op> :
- VOP3Only_Realtriple<GFX11Gen, op>, VOP3Only_Realtriple<GFX12Gen, op>;
-
-multiclass VOP3Only_Realtriple_t16_gfx11_gfx12<bits<10> op, string asmName, string OpName = NAME> :
- VOP3_Realtriple_t16_gfx11<op, asmName, OpName, "", /*IsSingle*/1>,
- VOP3_Realtriple_t16_gfx12<op, asmName, OpName, "", /*IsSingle*/1>;
+multiclass VOP3Only_Realtriple_t16_gfx11_gfx12_gfx13<bits<10> preGFX13Op, bits<10> op, string asmName, string OpName = NAME> :
+ VOP3_Realtriple_t16_gfx11<preGFX13Op, asmName, OpName, "", /*IsSingle*/1>,
+ VOP3_Realtriple_t16_gfx12<preGFX13Op, asmName, OpName, "", /*IsSingle*/1>,
+ VOP3_Realtriple_t16_gfx13<op, asmName, OpName, "", /*IsSingle*/1>;
-multiclass VOP3Only_Realtriple_t16_and_fake16_gfx11_gfx12<bits<10> op, string asmName, string OpName = NAME> {
- defm _t16: VOP3Only_Realtriple_t16_gfx11_gfx12<op, asmName, OpName#"_t16">;
- defm _fake16: VOP3Only_Realtriple_t16_gfx11_gfx12<op, asmName, OpName#"_fake16">;
+multiclass VOP3Only_Realtriple_t16_and_fake16_gfx11_gfx12_gfx13<bits<10> preGFX13Op, bits<10> op, string asmName, string OpName = NAME> {
+ defm _t16: VOP3Only_Realtriple_t16_gfx11_gfx12_gfx13<preGFX13Op, op, asmName, OpName#"_t16">;
+ defm _fake16: VOP3Only_Realtriple_t16_gfx11_gfx12_gfx13<preGFX13Op, op, asmName, OpName#"_fake16">;
}
-multiclass VOP3beOnly_Realtriple_gfx11_gfx12<bits<10> op> :
- VOP3beOnly_Realtriple<GFX11Gen, op>, VOP3beOnly_Realtriple<GFX12Gen, op>;
+multiclass VOP3beOnly_Realtriple_gfx11_gfx12_gfx13<bits<10> preGFX13Op, bits<10> op> :
+ VOP3beOnly_Realtriple<GFX11Gen, preGFX13Op>,
+ VOP3beOnly_Realtriple<GFX12Gen, preGFX13Op>,
+ VOP3beOnly_Realtriple<GFX13Gen, op>;
multiclass VOP2Only_Real_MADK_t16_gfx11_gfx12_gfx13<
bits<6> op, string asmName, string opName = NAME> :
@@ -2056,19 +2062,19 @@ defm V_FMAMK_F16 : VOP2Only_Real_MADK_t16_and_fake16_gfx11_gfx12_gfx13
defm V_FMAAK_F16 : VOP2Only_Real_MADK_t16_and_fake16_gfx11_gfx12_gfx13<0x038, "v_fmaak_f16">;
// VOP3 only.
-defm V_CNDMASK_B16 : VOP3Only_Realtriple_t16_and_fake16_gfx11_gfx12<0x25d, "v_cndmask_b16">;
-defm V_LDEXP_F32 : VOP3Only_Realtriple_gfx11_gfx12<0x31c>;
-defm V_BFM_B32 : VOP3Only_Realtriple_gfx11_gfx12<0x31d>;
-defm V_BCNT_U32_B32 : VOP3Only_Realtriple_gfx11_gfx12<0x31e>;
-defm V_MBCNT_LO_U32_B32 : VOP3Only_Realtriple_gfx11_gfx12<0x31f>;
-defm V_MBCNT_HI_U32_B32 : VOP3Only_Realtriple_gfx11_gfx12<0x320>;
-defm V_CVT_PK_NORM_I16_F32 : VOP3Only_Realtriple_with_name_gfx11_gfx12<0x321, "V_CVT_PKNORM_I16_F32", "v_cvt_pk_norm_i16_f32">;
-defm V_CVT_PK_NORM_U16_F32 : VOP3Only_Realtriple_with_name_gfx11_gfx12<0x322, "V_CVT_PKNORM_U16_F32", "v_cvt_pk_norm_u16_f32">;
-defm V_CVT_PK_U16_U32 : VOP3Only_Realtriple_gfx11_gfx12<0x323>;
-defm V_CVT_PK_I16_I32 : VOP3Only_Realtriple_gfx11_gfx12<0x324>;
-defm V_ADD_CO_U32 : VOP3beOnly_Realtriple_gfx11_gfx12<0x300>;
-defm V_SUB_CO_U32 : VOP3beOnly_Realtriple_gfx11_gfx12<0x301>;
-defm V_SUBREV_CO_U32 : VOP3beOnly_Realtriple_gfx11_gfx12<0x302>;
+defm V_CNDMASK_B16 : VOP3Only_Realtriple_t16_and_fake16_gfx11_gfx12_gfx13<0x25d, 0x25d, "v_cndmask_b16">;
+defm V_LDEXP_F32 : VOP3Only_Realtriple_gfx11_gfx12_gfx13<0x31c, 0x362>;
+defm V_BFM_B32 : VOP3Only_Realtriple_gfx11_gfx12_gfx13<0x31d>;
+defm V_BCNT_U32_B32 : VOP3Only_Realtriple_gfx11_gfx12_gfx13<0x31e, 0x364>;
+defm V_MBCNT_LO_U32_B32 : VOP3Only_Realtriple_gfx11_gfx12_gfx13<0x31f, 0x365>;
+defm V_MBCNT_HI_U32_B32 : VOP3Only_Realtriple_gfx11_gfx12_gfx13<0x320, 0x366>;
+defm V_CVT_PK_NORM_I16_F32 : VOP3Only_Realtriple_with_name_gfx11_gfx12_gfx13<0x321, 0x368, "V_CVT_PKNORM_I16_F32", "v_cvt_pk_norm_i16_f32">;
+defm V_CVT_PK_NORM_U16_F32 : VOP3Only_Realtriple_with_name_gfx11_gfx12_gfx13<0x322, 0x369, "V_CVT_PKNORM_U16_F32", "v_cvt_pk_norm_u16_f32">;
+defm V_CVT_PK_U16_U32 : VOP3Only_Realtriple_gfx11_gfx12_gfx13<0x323, 0x36a>;
+defm V_CVT_PK_I16_I32 : VOP3Only_Realtriple_gfx11_gfx12_gfx13<0x324, 0x36b>;
+defm V_ADD_CO_U32 : VOP3beOnly_Realtriple_gfx11_gfx12_gfx13<0x300, 0x30f>;
+defm V_SUB_CO_U32 : VOP3beOnly_Realtriple_gfx11_gfx12_gfx13<0x301, 0x310>;
+defm V_SUBREV_CO_U32 : VOP3beOnly_Realtriple_gfx11_gfx12_gfx13<0x302, 0x319>;
let SubtargetPredicate = isGFX11Only in {
defm : VOP2eInstAliases<V_CNDMASK_B32_e32, V_CNDMASK_B32_e32_gfx11>;
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index 41e76063386ec..dcf40511c59b8 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -191,7 +191,7 @@ let SubtargetPredicate = HasLerpInst in
let SchedRW = [WriteIntMul] in {
let SubtargetPredicate = HasMadU32Inst in
defm V_MAD_U32 : VOP3Inst <"v_mad_u32", V_MAD_U32_PROF>;
- let SubtargetPredicate = isGFX1250Plus in {
+ let SubtargetPredicate = isGFX125xOnly in {
defm V_MAD_NC_U64_U32 : VOP3Inst<"v_mad_nc_u64_u32", VOP_I32_I32_I64_DPP>;
defm V_MAD_NC_I64_I32 : VOP3Inst<"v_mad_nc_i64_i32", VOP_I32_I32_I64_DPP>;
}
@@ -232,12 +232,12 @@ defm V_MAXIMUM_F64 : VOP3Inst <"v_maximum_f64", VOP3_Profile<VOP_F64_F64_F64>, f
} // End SchedRW = [WriteDoubleAdd], IsDPMACCInstruction = 1
} // End SubtargetPredicate = HasIEEEMinimumMaximumInsts, ReadsModeReg = 0, AddedComplexity = 1
-let SubtargetPredicate = isGFX1250Plus, SchedRW = [WriteDoubleAdd] in {
+let SubtargetPredicate = isGFX125xOnly, SchedRW = [WriteDoubleAdd] in {
defm V_MAX_I64 : VOP3Inst <"v_max_i64", VOP_I64_I64_I64_DPP, smax>;
defm V_MAX_U64 : VOP3Inst <"v_max_u64", VOP_I64_I64_I64_DPP, umax>;
defm V_MIN_I64 : VOP3Inst <"v_min_i64", VOP_I64_I64_I64_DPP, smin>;
defm V_MIN_U64 : VOP3Inst <"v_min_u64", VOP_I64_I64_I64_DPP, umin>;
-} // End SubtargetPredicate = isGFX1250Plus, SchedRW = [WriteDoubleAdd]
+} // End SubtargetPredicate = isGFX125xOnly, SchedRW = [WriteDoubleAdd]
} // End isReMaterializable = 1
@@ -1855,12 +1855,14 @@ let SubtargetPredicate = isGFX1250Plus in {
}
let Constraints = "@earlyclobber $vdst" in {
- defm V_CVT_SCALE_PK8_F16_FP8 : VOP3CvtScaleSelInst<"v_cvt_scale_pk8_f16_fp8", VOP_V8F16_V2I32_I32, int_amdgcn_cvt_scale_pk8_f16_fp8>;
- defm V_CVT_SCALE_PK8_BF16_FP8 : VOP3CvtScaleSelInst<"v_cvt_scale_pk8_bf16_fp8", VOP_V8BF16_V2I32_I32, int_amdgcn_cvt_scale_pk8_bf16_fp8>;
- defm V_CVT_SCALE_PK8_F16_BF8 : VOP3CvtScaleSelInst<"v_cvt_scale_pk8_f16_bf8", VOP_V8F16_V2I32_I32, int_amdgcn_cvt_scale_pk8_f16_bf8>;
- defm V_CVT_SCALE_PK8_BF16_BF8 : VOP3CvtScaleSelInst<"v_cvt_scale_pk8_bf16_bf8", VOP_V8BF16_V2I32_I32, int_amdgcn_cvt_scale_pk8_bf16_bf8>;
- defm V_CVT_SCALE_PK8_F32_FP8 : VOP3CvtScaleSelInst<"v_cvt_scale_pk8_f32_fp8", VOP_V8F32_V2I32_I32, int_amdgcn_cvt_scale_pk8_f32_fp8>;
- defm V_CVT_SCALE_PK8_F32_BF8 : VOP3CvtScaleSelInst<"v_cvt_scale_pk8_f32_bf8", VOP_V8F32_V2I32_I32, int_amdgcn_cvt_scale_pk8_f32_bf8>;
+ let WaveSizePredicate = isWave32 in {
+ defm V_CVT_SCALE_PK8_F16_FP8 : VOP3CvtScaleSelInst<"v_cvt_scale_pk8_f16_fp8", VOP_V8F16_V2I32_I32, int_amdgcn_cvt_scale_pk8_f16_fp8>;
+ defm V_CVT_SCALE_PK8_BF16_FP8 : VOP3CvtScaleSelInst<"v_cvt_scale_pk8_bf16_fp8", VOP_V8BF16_V2I32_I32, int_amdgcn_cvt_scale_pk8_bf16_fp8>;
+ defm V_CVT_SCALE_PK8_F16_BF8 : VOP3CvtScaleSelInst<"v_cvt_scale_pk8_f16_bf8", VOP_V8F16_V2I32_I32, int_amdgcn_cvt_scale_pk8_f16_bf8>;
+ defm V_CVT_SCALE_PK8_BF16_BF8 : VOP3CvtScaleSelInst<"v_cvt_scale_pk8_bf16_bf8", VOP_V8BF16_V2I32_I32, int_amdgcn_cvt_scale_pk8_bf16_bf8>;
+ defm V_CVT_SCALE_PK8_F32_FP8 : VOP3CvtScaleSelInst<"v_cvt_scale_pk8_f32_fp8", VOP_V8F32_V2I32_I32, int_amdgcn_cvt_scale_pk8_f32_fp8>;
+ defm V_CVT_SCALE_PK8_F32_BF8 : VOP3CvtScaleSelInst<"v_cvt_scale_pk8_f32_bf8", VOP_V8F32_V2I32_I32, int_amdgcn_cvt_scale_pk8_f32_bf8>;
+ }
defm V_CVT_SCALE_PK16_F16_FP6 : VOP3CvtScaleSelInst<"v_cvt_scale_pk16_f16_fp6", VOP_V16F16_V3I32_I32, int_amdgcn_cvt_scale_pk16_f16_fp6>;
defm V_CVT_SCALE_PK16_BF16_FP6 : VOP3CvtScaleSelInst<"v_cvt_scale_pk16_bf16_fp6", VOP_V16BF16_V3I32_I32, int_amdgcn_cvt_scale_pk16_bf16_fp6>;
defm V_CVT_SCALE_PK16_F16_BF6 : VOP3CvtScaleSelInst<"v_cvt_scale_pk16_f16_bf6", VOP_V16F16_V3I32_I32, int_amdgcn_cvt_scale_pk16_f16_bf6>;
@@ -1869,9 +1871,11 @@ let SubtargetPredicate = isGFX1250Plus in {
defm V_CVT_SCALE_PK16_F32_BF6 : VOP3CvtScaleSelInst<"v_cvt_scale_pk16_f32_bf6", VOP_V16F32_V3I32_I32, int_amdgcn_cvt_scale_pk16_f32_bf6>;
} // End Constraints = "@earlyclobber $vdst"
- defm V_CVT_SCALE_PK8_F16_FP4 : VOP3CvtScaleSelInst<"v_cvt_scale_pk8_f16_fp4", VOP_V8F16_I32_I32, int_amdgcn_cvt_scale_pk8_f16_fp4>;
- defm V_CVT_SCALE_PK8_BF16_FP4 : VOP3CvtScaleSelInst<"v_cvt_scale_pk8_bf16_fp4", VOP_V8BF16_I32_I32, int_amdgcn_cvt_scale_pk8_bf16_fp4>;
- defm V_CVT_SCALE_PK8_F32_FP4 : VOP3CvtScaleSelInst<"v_cvt_scale_pk8_f32_fp4", VOP_V8F32_I32_I32, int_amdgcn_cvt_scale_pk8_f32_fp4>;
+ let WaveSizePredicate = isWave32 in {
+ defm V_CVT_SCALE_PK8_F16_FP4 : VOP3CvtScaleSelInst<"v_cvt_scale_pk8_f16_fp4", VOP_V8F16_I32_I32, int_amdgcn_cvt_scale_pk8_f16_fp4>;
+ defm V_CVT_SCALE_PK8_BF16_FP4 : VOP3CvtScaleSelInst<"v_cvt_scale_pk8_bf16_fp4", VOP_V8BF16_I32_I32, int_amdgcn_cvt_scale_pk8_bf16_fp4>;
+ defm V_CVT_SCALE_PK8_F32_FP4 : VOP3CvtScaleSelInst<"v_cvt_scale_pk8_f32_fp4", VOP_V8F32_I32_I32, int_amdgcn_cvt_scale_pk8_f32_fp4>;
+ }
} // End ReadsModeReg = 0
let Constraints = "@earlyclobber $vdst" in {
@@ -2028,6 +2032,11 @@ let SubtargetPredicate = HasAshrPkInsts in {
def : AshrPkU8Pat<V_ASHR_PK_U8_I32_e64, 0, 255>;
}
+let SubtargetPredicate = isGFX13Plus in {
+ defm V_CVT_SCALEF32_PK32_BF6_F32 : VOP3Inst<"v_cvt_scalef32_pk32_bf6_f32", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_V6I32_V32F32_F32>>;
+ defm V_CVT_SCALEF32_PK32_FP6_F32 : VOP3Inst<"v_cvt_scalef32_pk32_fp6_f32", VOP3_CVT_SCALEF32_PK_F864_Profile<VOP_V6I32_V32F32_F32>>;
+}
+
//===----------------------------------------------------------------------===//
// Integer Clamp Patterns
//===----------------------------------------------------------------------===//
@@ -2090,56 +2099,56 @@ def : MinimumMaximumByMinimum3Maximum3<fmaximum, f32, V_MAXIMUM3_F32_e64>;
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
-// GFX12.
+// GFX12, GFX13.
//===----------------------------------------------------------------------===//
-defm V_MIN3_NUM_F32 : VOP3_Realtriple_with_name_gfx12<0x229, "V_MIN3_F32", "v_min3_num_f32">;
-defm V_MAX3_NUM_F32 : VOP3_Realtriple_with_name_gfx12<0x22a, "V_MAX3_F32", "v_max3_num_f32">;
-defm V_MIN3_NUM_F16 : VOP3_Realtriple_t16_and_fake16_gfx12<0x22b, "v_min3_num_f16", "V_MIN3_F16", "v_min3_f16">;
-defm V_MAX3_NUM_F16 : VOP3_Realtriple_t16_and_fake16_gfx12<0x22c, "v_max3_num_f16", "V_MAX3_F16", "v_max3_f16">;
-defm V_MED3_NUM_F32 : VOP3_Realtriple_with_name_gfx12<0x231, "V_MED3_F32", "v_med3_num_f32">;
-defm V_MED3_NUM_F16 : VOP3_Realtriple_t16_and_fake16_gfx12<0x232, "v_med3_num_f16", "V_MED3_F16", "v_med3_f16">;
-defm V_MINMAX_NUM_F32 : VOP3_Realtriple_with_name_gfx12<0x268, "V_MINMAX_F32", "v_minmax_num_f32">;
-defm V_MAXMIN_NUM_F32 : VOP3_Realtriple_with_name_gfx12<0x269, "V_MAXMIN_F32", "v_maxmin_num_f32">;
-defm V_MINMAX_NUM_F16 : VOP3_Realtriple_t16_and_fake16_gfx12<0x26a, "v_minmax_num_f16", "V_MINMAX_F16", "v_minmax_f16">;
-defm V_MAXMIN_NUM_F16 : VOP3_Realtriple_t16_and_fake16_gfx12<0x26b, "v_maxmin_num_f16", "V_MAXMIN_F16", "v_maxmin_f16">;
-defm V_S_EXP_F32 : VOP3Only_Real_Base_gfx12<0x280>;
-defm V_S_EXP_F16 : VOP3Only_Real_Base_gfx12<0x281>;
-defm V_S_LOG_F32 : VOP3Only_Real_Base_gfx12<0x282>;
-defm V_S_LOG_F16 : VOP3Only_Real_Base_gfx12<0x283>;
-defm V_S_RCP_F32 : VOP3Only_Real_Base_gfx12<0x284>;
-defm V_S_RCP_F16 : VOP3Only_Real_Base_gfx12<0x285>;
-defm V_S_RSQ_F32 : VOP3Only_Real_Base_gfx12<0x286>;
-defm V_S_RSQ_F16 : VOP3Only_Real_Base_gfx12<0x287>;
-defm V_S_SQRT_F32 : VOP3Only_Real_Base_gfx12<0x288>;
-defm V_S_SQRT_F16 : VOP3Only_Real_Base_gfx12<0x289>;
-defm V_MAD_CO_U64_U32 : VOP3be_Real_with_name_gfx12<0x2fe, "V_MAD_U64_U32", "v_mad_co_u64_u32">;
-defm V_MAD_CO_I64_I32 : VOP3be_Real_with_name_gfx12<0x2ff, "V_MAD_I64_I32", "v_mad_co_i64_i32">;
+defm V_MIN3_NUM_F32 : VOP3_Realtriple_with_name_gfx12_gfx13<0x229, 0x229, "V_MIN3_F32", "v_min3_num_f32">;
+defm V_MAX3_NUM_F32 : VOP3_Realtriple_with_name_gfx12_gfx13<0x22a, 0x22...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/196258
More information about the llvm-commits
mailing list