[llvm] [AMDGPU] Add VOP3P encoding to gfx13 (PR #196252)
via llvm-commits
llvm-commits at lists.llvm.org
Thu May 7 00:24:42 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Mariusz Sikora (mariusz-sikora-at-amd)
<details>
<summary>Changes</summary>
---
Patch is 107.47 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/196252.diff
6 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/VOP3PInstructions.td (+60-42)
- (modified) llvm/test/MC/AMDGPU/gfx12_asm_vop3p_aliases.s (+1)
- (added) llvm/test/MC/AMDGPU/gfx13_asm_vop3p.s (+1608)
- (added) llvm/test/MC/AMDGPU/gfx13_asm_vop3p_dpp16.s (+18)
- (added) llvm/test/MC/AMDGPU/gfx13_asm_vop3p_dpp8.s (+34)
- (added) llvm/test/MC/AMDGPU/gfx13_asm_vop3p_features.s (+125)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
index 7ae93b30e7f03..c7835010032ea 100644
--- a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
@@ -2568,20 +2568,27 @@ defm V_DOT4_F32_FP8_FP8 : VOP3P_Realtriple_gfx11_gfx12<0x26>;
defm V_DOT4_F32_BF8_BF8 : VOP3P_Realtriple_gfx11_gfx12<0x27>;
//===----------------------------------------------------------------------===//
-// GFX12
+// GFX12, GFX13.
//===----------------------------------------------------------------------===//
multiclass VOP3P_Real_gfx12<bits<8> op> : VOP3P_Real_Base<GFX12Gen, op>;
multiclass VOP3P_Real_gfx1250<bits<8> op> : VOP3P_Real_Base<GFX1250Gen, op>;
-multiclass VOP3P_Real_with_name_gfx12<bits<8> op,
+multiclass VOP3P_Real_gfx1250_gfx13<bits<8> op> :
+ VOP3P_Real_gfx1250<op>, VOP3P_Real_Base<GFX13Gen, op>;
+
+multiclass VOP3P_Real_with_name_gfx12_gfx13<bits<8> op,
string backing_ps_name = NAME,
string asmName = !cast<VOP3P_Pseudo>(NAME).Mnemonic> :
- VOP3P_Real_with_name<GFX12Gen, op, backing_ps_name, asmName>;
+ VOP3P_Real_with_name<GFX12Gen, op, backing_ps_name, asmName>,
+ VOP3P_Real_with_name<GFX13Gen, op, backing_ps_name, asmName>;
+
+multiclass VOP3P_Realtriple_gfx1250_gfx13<bits<8> op> :
+ VOP3P_Realtriple<GFX1250Gen, op>, VOP3P_Realtriple<GFX13Gen, op>;
-defm V_PK_MIN_NUM_F16 : VOP3P_Real_with_name_gfx12<0x1b, "V_PK_MIN_F16", "v_pk_min_num_f16">;
-defm V_PK_MAX_NUM_F16 : VOP3P_Real_with_name_gfx12<0x1c, "V_PK_MAX_F16", "v_pk_max_num_f16">;
+defm V_PK_MIN_NUM_F16 : VOP3P_Real_with_name_gfx12_gfx13<0x1b, "V_PK_MIN_F16", "v_pk_min_num_f16">;
+defm V_PK_MAX_NUM_F16 : VOP3P_Real_with_name_gfx12_gfx13<0x1c, "V_PK_MAX_F16", "v_pk_max_num_f16">;
defm V_PK_FMA_F32 : VOP3P_Real_gfx12<0x1f>;
defm V_PK_MUL_F32 : VOP3P_Real_gfx12<0x28>;
@@ -2595,19 +2602,19 @@ defm V_PK_MAX3_I16 : VOP3P_Real_gfx1250<0x2f>;
defm V_PK_MAX3_U16 : VOP3P_Real_gfx1250<0x30>;
defm V_PK_MIN3_I16 : VOP3P_Real_gfx1250<0x31>;
defm V_PK_MIN3_U16 : VOP3P_Real_gfx1250<0x32>;
-defm V_PK_FMA_BF16 : VOP3P_Real_gfx1250<0x11>;
-defm V_PK_ADD_BF16 : VOP3P_Real_gfx1250<0x23>;
-defm V_PK_MUL_BF16 : VOP3P_Real_gfx1250<0x2a>;
-defm V_PK_MIN_NUM_BF16 : VOP3P_Real_gfx1250<0x2b>;
-defm V_PK_MAX_NUM_BF16 : VOP3P_Real_gfx1250<0x2c>;
+defm V_PK_FMA_BF16 : VOP3P_Real_gfx1250_gfx13<0x11>;
+defm V_PK_ADD_BF16 : VOP3P_Real_gfx1250_gfx13<0x23>;
+defm V_PK_MUL_BF16 : VOP3P_Real_gfx1250_gfx13<0x2a>;
+defm V_PK_MIN_NUM_BF16 : VOP3P_Real_gfx1250_gfx13<0x2b>;
+defm V_PK_MAX_NUM_BF16 : VOP3P_Real_gfx1250_gfx13<0x2c>;
defm V_PK_MINIMUM3_F16 : VOP3P_Real_gfx1250<0x36>;
defm V_PK_MAXIMUM3_F16 : VOP3P_Real_gfx1250<0x37>;
defm V_PK_MIN3_NUM_F16 : VOP3P_Real_gfx1250<0x38>;
defm V_PK_MAX3_NUM_F16 : VOP3P_Real_gfx1250<0x39>;
-defm V_FMA_MIX_F32_BF16 : VOP3P_Realtriple<GFX1250Gen, 0x3d>;
-defm V_FMA_MIXLO_BF16 : VOP3P_Realtriple<GFX1250Gen, 0x3e>;
-defm V_FMA_MIXHI_BF16 : VOP3P_Realtriple<GFX1250Gen, 0x3f>;
+defm V_FMA_MIX_F32_BF16 : VOP3P_Realtriple_gfx1250_gfx13<0x3d>;
+defm V_FMA_MIXLO_BF16 : VOP3P_Realtriple_gfx1250_gfx13<0x3e>;
+defm V_FMA_MIXHI_BF16 : VOP3P_Realtriple_gfx1250_gfx13<0x3f>;
let PostEncoderMethod = "postEncodeVOP3<true, true, false>" in {
defm V_WMMA_LD_SCALE_PAIRED_B32 : VOP3P_Real_gfx1250<0x35>;
@@ -2632,15 +2639,18 @@ multiclass VOP3P_Real_with_name_gfx1170<bits<8> op,
defm V_PK_MIN_NUM_F16 : VOP3P_Real_with_name_gfx1170<0x11, "V_PK_MIN_F16", "v_pk_min_num_f16">;
defm V_PK_MAX_NUM_F16 : VOP3P_Real_with_name_gfx1170<0x12, "V_PK_MAX_F16", "v_pk_max_num_f16">;
-defm V_PK_MINIMUM_F16 : VOP3P_Real_gfx11_gfx12<0x1d>;
-defm V_PK_MAXIMUM_F16 : VOP3P_Real_gfx11_gfx12<0x1e>;
-
//===----------------------------------------------------------------------===//
-// GFX11
+// GFX11, GFX12, GFX13.
//===----------------------------------------------------------------------===//
+multiclass VOP3P_Real_gfx11_gfx12_gfx13<bits<8> op> :
+ VOP3P_Real_gfx11_gfx12<op>, VOP3P_Real_Base<GFX13Gen, op>;
+
+defm V_PK_MINIMUM_F16 : VOP3P_Real_gfx11_gfx12_gfx13<0x1d>;
+defm V_PK_MAXIMUM_F16 : VOP3P_Real_gfx11_gfx12_gfx13<0x1e>;
+
+defm V_DOT4_I32_IU8 : VOP3P_Real_gfx11_gfx12_gfx13<0x16>;
+defm V_DOT8_I32_IU4 : VOP3P_Real_gfx11_gfx12_gfx13<0x18>;
-defm V_DOT4_I32_IU8 : VOP3P_Real_gfx11_gfx12<0x16>;
-defm V_DOT8_I32_IU4 : VOP3P_Real_gfx11_gfx12<0x18>;
defm V_DOT2_F32_BF16 : VOP3P_Realtriple_gfx11_gfx12<0x1a>;
let AssemblerPredicate = isGFX11Plus in {
@@ -3006,7 +3016,7 @@ defm V_PK_ADD_F32 : VOP3P_Real_vi <0x32>;
defm V_PK_MOV_B32 : VOP3P_Real_vi <0x33>;
//===----------------------------------------------------------------------===//
-// GFX10.
+// GFX10, GFX11, GFX12, GFX13.
//===----------------------------------------------------------------------===//
let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10", VOP3P = 1 in {
@@ -3019,6 +3029,10 @@ let AssemblerPredicate = isGFX10Only, DecoderNamespace = "GFX10", VOP3P = 1 in {
multiclass VOP3P_Real_gfx10_gfx11<bits<8> op> :
VOP3P_Real_gfx10<op>, VOP3P_Real_Base<GFX11Gen, op>;
+multiclass VOP3P_Real_gfx10_gfx11_gfx12_gfx13<bits<8> op> :
+ VOP3P_Real_gfx10_gfx11<op>, VOP3P_Real_Base<GFX12Gen, op>,
+ VOP3P_Real_Base<GFX13Gen, op>;
+
multiclass VOP3P_Real_gfx10_gfx11_not_gfx1170<bits<8> op> :
VOP3P_Real_gfx10<op>, VOP3P_Real_Base<GFX11Not11_70Gen, op>;
@@ -3029,35 +3043,39 @@ multiclass VOP3P_Real_gfx10_gfx11_gfx12_Triple<bits<8> op> :
VOP3P_Real_gfx10<op>, VOP3P_Realtriple<GFX11Gen, op>,
VOP3P_Realtriple<GFX12Gen, op>;
-defm V_PK_MAD_I16 : VOP3P_Real_gfx10_gfx11_gfx12<0x00>;
-defm V_PK_MUL_LO_U16 : VOP3P_Real_gfx10_gfx11_gfx12<0x01>;
-defm V_PK_ADD_I16 : VOP3P_Real_gfx10_gfx11_gfx12<0x02>;
-defm V_PK_SUB_I16 : VOP3P_Real_gfx10_gfx11_gfx12<0x03>;
-defm V_PK_LSHLREV_B16 : VOP3P_Real_gfx10_gfx11_gfx12<0x04>;
-defm V_PK_LSHRREV_B16 : VOP3P_Real_gfx10_gfx11_gfx12<0x05>;
-defm V_PK_ASHRREV_I16 : VOP3P_Real_gfx10_gfx11_gfx12<0x06>;
-defm V_PK_MAX_I16 : VOP3P_Real_gfx10_gfx11_gfx12<0x07>;
-defm V_PK_MIN_I16 : VOP3P_Real_gfx10_gfx11_gfx12<0x08>;
-defm V_PK_MAD_U16 : VOP3P_Real_gfx10_gfx11_gfx12<0x09>;
-defm V_PK_ADD_U16 : VOP3P_Real_gfx10_gfx11_gfx12<0x0a>;
-defm V_PK_SUB_U16 : VOP3P_Real_gfx10_gfx11_gfx12<0x0b>;
-defm V_PK_MAX_U16 : VOP3P_Real_gfx10_gfx11_gfx12<0x0c>;
-defm V_PK_MIN_U16 : VOP3P_Real_gfx10_gfx11_gfx12<0x0d>;
-defm V_PK_FMA_F16 : VOP3P_Real_gfx10_gfx11_gfx12<0x0e>;
-defm V_PK_ADD_F16 : VOP3P_Real_gfx10_gfx11_gfx12<0x0f>;
-defm V_PK_MUL_F16 : VOP3P_Real_gfx10_gfx11_gfx12<0x10>;
+multiclass VOP3P_Real_gfx10_gfx11_gfx12_gfx13_Triple<bits<8> op> :
+ VOP3P_Real_gfx10_gfx11_gfx12_Triple<op>,
+ VOP3P_Realtriple<GFX13Gen, op>;
+
+defm V_PK_MAD_I16 : VOP3P_Real_gfx10_gfx11_gfx12_gfx13<0x00>;
+defm V_PK_MUL_LO_U16 : VOP3P_Real_gfx10_gfx11_gfx12_gfx13<0x01>;
+defm V_PK_ADD_I16 : VOP3P_Real_gfx10_gfx11_gfx12_gfx13<0x02>;
+defm V_PK_SUB_I16 : VOP3P_Real_gfx10_gfx11_gfx12_gfx13<0x03>;
+defm V_PK_LSHLREV_B16 : VOP3P_Real_gfx10_gfx11_gfx12_gfx13<0x04>;
+defm V_PK_LSHRREV_B16 : VOP3P_Real_gfx10_gfx11_gfx12_gfx13<0x05>;
+defm V_PK_ASHRREV_I16 : VOP3P_Real_gfx10_gfx11_gfx12_gfx13<0x06>;
+defm V_PK_MAX_I16 : VOP3P_Real_gfx10_gfx11_gfx12_gfx13<0x07>;
+defm V_PK_MIN_I16 : VOP3P_Real_gfx10_gfx11_gfx12_gfx13<0x08>;
+defm V_PK_MAD_U16 : VOP3P_Real_gfx10_gfx11_gfx12_gfx13<0x09>;
+defm V_PK_ADD_U16 : VOP3P_Real_gfx10_gfx11_gfx12_gfx13<0x0a>;
+defm V_PK_SUB_U16 : VOP3P_Real_gfx10_gfx11_gfx12_gfx13<0x0b>;
+defm V_PK_MAX_U16 : VOP3P_Real_gfx10_gfx11_gfx12_gfx13<0x0c>;
+defm V_PK_MIN_U16 : VOP3P_Real_gfx10_gfx11_gfx12_gfx13<0x0d>;
+defm V_PK_FMA_F16 : VOP3P_Real_gfx10_gfx11_gfx12_gfx13<0x0e>;
+defm V_PK_ADD_F16 : VOP3P_Real_gfx10_gfx11_gfx12_gfx13<0x0f>;
+defm V_PK_MUL_F16 : VOP3P_Real_gfx10_gfx11_gfx12_gfx13<0x10>;
defm V_PK_MIN_F16 : VOP3P_Real_gfx10_gfx11_not_gfx1170<0x11>;
defm V_PK_MAX_F16 : VOP3P_Real_gfx10_gfx11_not_gfx1170<0x12>;
-defm V_FMA_MIX_F32 : VOP3P_Real_gfx10_gfx11_gfx12_Triple<0x20>;
-defm V_FMA_MIXLO_F16 : VOP3P_Real_gfx10_gfx11_gfx12_Triple<0x21>;
-defm V_FMA_MIXHI_F16 : VOP3P_Real_gfx10_gfx11_gfx12_Triple<0x22>;
+defm V_FMA_MIX_F32 : VOP3P_Real_gfx10_gfx11_gfx12_gfx13_Triple<0x20>;
+defm V_FMA_MIXLO_F16 : VOP3P_Real_gfx10_gfx11_gfx12_gfx13_Triple<0x21>;
+defm V_FMA_MIXHI_F16 : VOP3P_Real_gfx10_gfx11_gfx12_gfx13_Triple<0x22>;
defm V_DOT2_I32_I16 : VOP3P_Real_gfx10 <0x14>;
defm V_DOT2_U32_U16 : VOP3P_Real_gfx10 <0x15>;
defm V_DOT2_F32_F16 : VOP3P_Real_gfx10_gfx11_gfx12_Triple<0x13>;
-defm V_DOT4_U32_U8 : VOP3P_Real_gfx10_gfx11_gfx12<0x17>;
-defm V_DOT8_U32_U4 : VOP3P_Real_gfx10_gfx11_gfx12<0x19>;
+defm V_DOT4_U32_U8 : VOP3P_Real_gfx10_gfx11_gfx12_gfx13<0x17>;
+defm V_DOT8_U32_U4 : VOP3P_Real_gfx10_gfx11_gfx12_gfx13<0x19>;
defm V_DOT4_I32_I8 : VOP3P_Real_gfx10 <0x16>;
defm V_DOT8_I32_I4 : VOP3P_Real_gfx10 <0x18>;
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3p_aliases.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3p_aliases.s
index f7ee690c79211..566978544c596 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3p_aliases.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3p_aliases.s
@@ -1,5 +1,6 @@
// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --unique --sort --version 6
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1310 -mattr=+wavefrontsize32 -show-encoding %s | FileCheck --check-prefixes=GFX12 %s
v_dot4_i32_i8 v5, v1, v2, s3
// GFX12: v_dot4_i32_iu8 v5, v1, v2, s3 ; encoding: [0x05,0x40,0x16,0xcc,0x01,0x05,0x0e,0x18]
diff --git a/llvm/test/MC/AMDGPU/gfx13_asm_vop3p.s b/llvm/test/MC/AMDGPU/gfx13_asm_vop3p.s
new file mode 100644
index 0000000000000..3055a0fe43206
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx13_asm_vop3p.s
@@ -0,0 +1,1608 @@
+// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6
+// RUN: llvm-mc -triple=amdgcn -show-encoding -mcpu=gfx1310 %s | FileCheck --check-prefix=GFX13 %s
+// RUN: llvm-mc -triple=amdgcn -show-encoding -mcpu=gfx1310 %s | %extract-encodings | llvm-mc -triple=amdgcn -show-encoding -mcpu=gfx1310 -disassemble | FileCheck --check-prefix=GFX13 %s
+
+v_dot4_i32_iu8 v255, 0xaf123456, vcc_hi, null neg_lo:[0,0,0]
+// GFX13: v_dot4_i32_iu8 v255, 0xaf123456, vcc_hi, null ; encoding: [0xff,0x40,0x16,0xcc,0xff,0xd6,0xf0,0x19,0x56,0x34,0x12,0xaf]
+
+v_dot4_i32_iu8 v5, -1, exec_hi, src_scc
+// GFX13: v_dot4_i32_iu8 v5, -1, exec_hi, src_scc ; encoding: [0x05,0x40,0x16,0xcc,0xc1,0xfe,0xf4,0x1b]
+
+v_dot4_i32_iu8 v5, 0.5, m0, 0.5 neg_lo:[1,0,0]
+// GFX13: v_dot4_i32_iu8 v5, 0.5, m0, 0.5 neg_lo:[1,0,0] ; encoding: [0x05,0x40,0x16,0xcc,0xf0,0xfa,0xc0,0x3b]
+
+v_dot4_i32_iu8 v5, exec_hi, null, vcc_lo
+// GFX13: v_dot4_i32_iu8 v5, exec_hi, null, vcc_lo ; encoding: [0x05,0x40,0x16,0xcc,0x7f,0xf8,0xa8,0x19]
+
+v_dot4_i32_iu8 v5, exec_lo, -1, vcc_hi
+// GFX13: v_dot4_i32_iu8 v5, exec_lo, -1, vcc_hi ; encoding: [0x05,0x40,0x16,0xcc,0x7e,0x82,0xad,0x19]
+
+v_dot4_i32_iu8 v5, m0, 0.5, m0
+// GFX13: v_dot4_i32_iu8 v5, m0, 0.5, m0 ; encoding: [0x05,0x40,0x16,0xcc,0x7d,0xe0,0xf5,0x19]
+
+v_dot4_i32_iu8 v5, null, exec_lo, 0xaf123456
+// GFX13: v_dot4_i32_iu8 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x40,0x16,0xcc,0x7c,0xfc,0xfc,0x1b,0x56,0x34,0x12,0xaf]
+
+v_dot4_i32_iu8 v5, s1, v255, exec_hi
+// GFX13: v_dot4_i32_iu8 v5, s1, v255, exec_hi ; encoding: [0x05,0x40,0x16,0xcc,0x01,0xfe,0xff,0x19]
+
+v_dot4_i32_iu8 v5, s105, s105, exec_lo
+// GFX13: v_dot4_i32_iu8 v5, s105, s105, exec_lo ; encoding: [0x05,0x40,0x16,0xcc,0x69,0xd2,0xf8,0x19]
+
+v_dot4_i32_iu8 v5, src_scc, vcc_lo, -1 neg_lo:[0,1,0]
+// GFX13: v_dot4_i32_iu8 v5, src_scc, vcc_lo, -1 neg_lo:[0,1,0] ; encoding: [0x05,0x40,0x16,0xcc,0xfd,0xd4,0x04,0x5b]
+
+v_dot4_i32_iu8 v5, ttmp15, src_scc, ttmp15
+// GFX13: v_dot4_i32_iu8 v5, ttmp15, src_scc, ttmp15 ; encoding: [0x05,0x40,0x16,0xcc,0x7b,0xfa,0xed,0x19]
+
+v_dot4_i32_iu8 v5, v1, v2, s3
+// GFX13: v_dot4_i32_iu8 v5, v1, v2, s3 ; encoding: [0x05,0x40,0x16,0xcc,0x01,0x05,0x0e,0x18]
+
+v_dot4_i32_iu8 v5, v255, s2, s105
+// GFX13: v_dot4_i32_iu8 v5, v255, s2, s105 ; encoding: [0x05,0x40,0x16,0xcc,0xff,0x05,0xa4,0x19]
+
+v_dot4_i32_iu8 v5, vcc_hi, 0xaf123456, v255
+// GFX13: v_dot4_i32_iu8 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x40,0x16,0xcc,0x6b,0xfe,0xfd,0x1f,0x56,0x34,0x12,0xaf]
+
+v_dot4_i32_iu8 v5, vcc_lo, ttmp15, v3
+// GFX13: v_dot4_i32_iu8 v5, vcc_lo, ttmp15, v3 ; encoding: [0x05,0x40,0x16,0xcc,0x6a,0xf6,0x0c,0x1c]
+
+v_dot4_u32_u8 v255, 0xaf123456, vcc_hi, null
+// GFX13: v_dot4_u32_u8 v255, 0xaf123456, vcc_hi, null ; encoding: [0xff,0x40,0x17,0xcc,0xff,0xd6,0xf0,0x19,0x56,0x34,0x12,0xaf]
+
+v_dot4_u32_u8 v5, -1, exec_hi, src_scc
+// GFX13: v_dot4_u32_u8 v5, -1, exec_hi, src_scc ; encoding: [0x05,0x40,0x17,0xcc,0xc1,0xfe,0xf4,0x1b]
+
+v_dot4_u32_u8 v5, 0.5, m0, 0.5
+// GFX13: v_dot4_u32_u8 v5, 0.5, m0, 0.5 ; encoding: [0x05,0x40,0x17,0xcc,0xf0,0xfa,0xc0,0x1b]
+
+v_dot4_u32_u8 v5, exec_hi, null, vcc_lo
+// GFX13: v_dot4_u32_u8 v5, exec_hi, null, vcc_lo ; encoding: [0x05,0x40,0x17,0xcc,0x7f,0xf8,0xa8,0x19]
+
+v_dot4_u32_u8 v5, exec_lo, -1, vcc_hi
+// GFX13: v_dot4_u32_u8 v5, exec_lo, -1, vcc_hi ; encoding: [0x05,0x40,0x17,0xcc,0x7e,0x82,0xad,0x19]
+
+v_dot4_u32_u8 v5, m0, 0.5, m0
+// GFX13: v_dot4_u32_u8 v5, m0, 0.5, m0 ; encoding: [0x05,0x40,0x17,0xcc,0x7d,0xe0,0xf5,0x19]
+
+v_dot4_u32_u8 v5, null, exec_lo, 0xaf123456
+// GFX13: v_dot4_u32_u8 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x40,0x17,0xcc,0x7c,0xfc,0xfc,0x1b,0x56,0x34,0x12,0xaf]
+
+v_dot4_u32_u8 v5, s1, v255, exec_hi
+// GFX13: v_dot4_u32_u8 v5, s1, v255, exec_hi ; encoding: [0x05,0x40,0x17,0xcc,0x01,0xfe,0xff,0x19]
+
+v_dot4_u32_u8 v5, s105, s105, exec_lo
+// GFX13: v_dot4_u32_u8 v5, s105, s105, exec_lo ; encoding: [0x05,0x40,0x17,0xcc,0x69,0xd2,0xf8,0x19]
+
+v_dot4_u32_u8 v5, src_scc, vcc_lo, -1
+// GFX13: v_dot4_u32_u8 v5, src_scc, vcc_lo, -1 ; encoding: [0x05,0x40,0x17,0xcc,0xfd,0xd4,0x04,0x1b]
+
+v_dot4_u32_u8 v5, ttmp15, src_scc, ttmp15
+// GFX13: v_dot4_u32_u8 v5, ttmp15, src_scc, ttmp15 ; encoding: [0x05,0x40,0x17,0xcc,0x7b,0xfa,0xed,0x19]
+
+v_dot4_u32_u8 v5, v1, v2, s3
+// GFX13: v_dot4_u32_u8 v5, v1, v2, s3 ; encoding: [0x05,0x40,0x17,0xcc,0x01,0x05,0x0e,0x18]
+
+v_dot4_u32_u8 v5, v255, s2, s105
+// GFX13: v_dot4_u32_u8 v5, v255, s2, s105 ; encoding: [0x05,0x40,0x17,0xcc,0xff,0x05,0xa4,0x19]
+
+v_dot4_u32_u8 v5, vcc_hi, 0xaf123456, v255
+// GFX13: v_dot4_u32_u8 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x40,0x17,0xcc,0x6b,0xfe,0xfd,0x1f,0x56,0x34,0x12,0xaf]
+
+v_dot4_u32_u8 v5, vcc_lo, ttmp15, v3
+// GFX13: v_dot4_u32_u8 v5, vcc_lo, ttmp15, v3 ; encoding: [0x05,0x40,0x17,0xcc,0x6a,0xf6,0x0c,0x1c]
+
+v_dot8_i32_iu4 v255, 0xaf123456, vcc_hi, null neg_lo:[0,0,0] clamp
+// GFX13: v_dot8_i32_iu4 v255, 0xaf123456, vcc_hi, null clamp ; encoding: [0xff,0xc0,0x18,0xcc,0xff,0xd6,0xf0,0x19,0x56,0x34,0x12,0xaf]
+
+v_dot8_i32_iu4 v5, -1, exec_hi, src_scc
+// GFX13: v_dot8_i32_iu4 v5, -1, exec_hi, src_scc ; encoding: [0x05,0x40,0x18,0xcc,0xc1,0xfe,0xf4,0x1b]
+
+v_dot8_i32_iu4 v5, 0.5, m0, 0.5 neg_lo:[1,0,0]
+// GFX13: v_dot8_i32_iu4 v5, 0.5, m0, 0.5 neg_lo:[1,0,0] ; encoding: [0x05,0x40,0x18,0xcc,0xf0,0xfa,0xc0,0x3b]
+
+v_dot8_i32_iu4 v5, exec_hi, null, vcc_lo
+// GFX13: v_dot8_i32_iu4 v5, exec_hi, null, vcc_lo ; encoding: [0x05,0x40,0x18,0xcc,0x7f,0xf8,0xa8,0x19]
+
+v_dot8_i32_iu4 v5, exec_lo, -1, vcc_hi
+// GFX13: v_dot8_i32_iu4 v5, exec_lo, -1, vcc_hi ; encoding: [0x05,0x40,0x18,0xcc,0x7e,0x82,0xad,0x19]
+
+v_dot8_i32_iu4 v5, m0, 0.5, m0
+// GFX13: v_dot8_i32_iu4 v5, m0, 0.5, m0 ; encoding: [0x05,0x40,0x18,0xcc,0x7d,0xe0,0xf5,0x19]
+
+v_dot8_i32_iu4 v5, null, exec_lo, 0xaf123456
+// GFX13: v_dot8_i32_iu4 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x40,0x18,0xcc,0x7c,0xfc,0xfc,0x1b,0x56,0x34,0x12,0xaf]
+
+v_dot8_i32_iu4 v5, s1, v255, exec_hi
+// GFX13: v_dot8_i32_iu4 v5, s1, v255, exec_hi ; encoding: [0x05,0x40,0x18,0xcc,0x01,0xfe,0xff,0x19]
+
+v_dot8_i32_iu4 v5, s105, s105, exec_lo
+// GFX13: v_dot8_i32_iu4 v5, s105, s105, exec_lo ; encoding: [0x05,0x40,0x18,0xcc,0x69,0xd2,0xf8,0x19]
+
+v_dot8_i32_iu4 v5, src_scc, vcc_lo, -1 neg_lo:[0,1,0]
+// GFX13: v_dot8_i32_iu4 v5, src_scc, vcc_lo, -1 neg_lo:[0,1,0] ; encoding: [0x05,0x40,0x18,0xcc,0xfd,0xd4,0x04,0x5b]
+
+v_dot8_i32_iu4 v5, ttmp15, src_scc, ttmp15
+// GFX13: v_dot8_i32_iu4 v5, ttmp15, src_scc, ttmp15 ; encoding: [0x05,0x40,0x18,0xcc,0x7b,0xfa,0xed,0x19]
+
+v_dot8_i32_iu4 v5, v1, v2, s3
+// GFX13: v_dot8_i32_iu4 v5, v1, v2, s3 ; encoding: [0x05,0x40,0x18,0xcc,0x01,0x05,0x0e,0x18]
+
+v_dot8_i32_iu4 v5, v255, s2, s105
+// GFX13: v_dot8_i32_iu4 v5, v255, s2, s105 ; encoding: [0x05,0x40,0x18,0xcc,0xff,0x05,0xa4,0x19]
+
+v_dot8_i32_iu4 v5, vcc_hi, 0xaf123456, v255
+// GFX13: v_dot8_i32_iu4 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x40,0x18,0xcc,0x6b,0xfe,0xfd,0x1f,0x56,0x34,0x12,0xaf]
+
+v_dot8_i32_iu4 v5, vcc_lo, ttmp15, v3
+// GFX13: v_dot8_i32_iu4 v5, vcc_lo, ttmp15, v3 ; encoding: [0x05,0x40,0x18,0xcc,0x6a,0xf6,0x0c,0x1c]
+
+v_dot8_u32_u4 v255, 0xaf123456, vcc_hi, null clamp
+// GFX13: v_dot8_u32_u4 v255, 0xaf123456, vcc_hi, null clamp ; encoding: [0xff,0xc0,0x19,0xcc,0xff,0xd6,0xf0,0x19,0x56,0x34,0x12,0xaf]
+
+v_dot8_u32_u4 v5, -1, exec_hi, src_scc
+// GFX13: v_dot8_u32_u4 v5, -1, exec_hi, src_scc ; encoding: [0x05,0x40,0x19,0xcc,0xc1,0xfe,0xf4,0x1b]
+
+v_dot8_u32_u4 v5, 0.5, m0, 0.5
+// GFX13: v_dot8_u32_u4 v5, 0.5, m0, 0.5 ; encoding: [0x05,0x40,0x19,0xcc,0xf0,0xfa,0xc0,0x1b]
+
+v_dot8_u32_u4 v5, exec_hi, null, vcc_lo
+// GFX13: v_dot8_u32_u4 v5, exec_hi, null, vcc_lo ; encoding: [0x05,0x40,0x19,0xcc,0x7f,0xf8,0xa8,0x19]
+
+v_dot8_u32_u4 v5, exec_lo, -1, vcc_hi
+// GFX13: v_dot8_u32_u4 v5, exec_lo, -1, vcc_hi ; encoding: [0x05,0x40,0x19,0xcc,0x7e,0x82,0xad,0x19]
+
+v_dot8_u32_u4 v5, m0, 0.5, m0
+// GFX13: v_dot8_u32_u4 v5, m0, 0.5, m0 ; encoding: [0x05,0x40,0x19,0xcc,0x7d,0xe0,0xf5,0x19]
+
+v_dot8_u32_u4 v5, null, exec_lo, 0xaf123456
+// GFX13: v_dot8_u32_u4 v5, null, exec_lo, 0xaf123456 ; encoding: [0x05,0x40,0x19,0xcc,0x7c,0xfc,0xfc,0x1b,0x56,0x34,0x12,0xaf]
+
+v_dot8_u32_u4 v5, s1, v255, exec_hi
+// GFX13: v_dot8_u32_u4 v5, s1, v255, exec_hi ; encoding: [0x05,0x40,0x19,0xcc,0x01,0xfe,0xff,0x19]
+
+v_dot8_u32_u4 v5, s105, s105, exec_lo
+// GFX13: v_dot8_u32_u4 v5, s105, s105, exec_lo ; encoding: [0x05,0x40,0x19,0xcc,0x69,0xd2,0xf8,0x19]
+
+v_dot8_u32_u4 v5, src_scc, vcc_lo, -1
+// GFX13: v_dot8_u32_u4 v5, src_scc, vcc_lo, -1 ; encoding: [0x05,0x40,0x19,0xcc,0xfd,0xd4,0x04,0x1b]
+
+v_dot8_u32_u4 v5, ttmp15, src_scc, ttmp15
+// GFX13: v_dot8_u32_u4 v5, ttmp15, src_scc, ttmp15 ; encoding: [0x05,0x40,0x19,0xcc,0x7b,0xfa,0xed,0x19]
+
+v_dot8_u32_u4 v5, v1, v2, s3
+// GFX13: v_dot8_u32_u4 v5, v1, v2, s3 ; encoding: [0x05,0x40,0x19,0xcc,0x01,0x05,0x0e,0x18]
+
+v_dot8_u32_u4 v5, v255, s2, s105
+// GFX13: v_dot8_u32_u4 v5, v255, s2, s105 ; encoding: [0x05,0x40,0x19,0xcc,0xff,0x05,0xa4,0x19]
+
+v_dot8_u32_u4 v5, vcc_hi, 0xaf123456, v255
+// GFX13: v_dot8_u32_u4 v5, vcc_hi, 0xaf123456, v255 ; encoding: [0x05,0x40,0x19,0xcc,0x6b,0xfe,0xfd,0x1f,0x56,0x34,0x12,0xaf]
+
+v_dot8_u32_u4 v5, vcc_lo, ttmp15, v3
+// GFX13: v_dot8_u32_u4 v5, vcc_lo, ttmp15, v3 ; encoding: [0x05,0x40,0x19,0xcc,0x6a,0xf6,0x0c,0x1c]
+
+v_fma_mix_f32 v255, -|src_scc|, -|vcc_hi|, null op_sel:[0,0,1] op_sel_hi:[0,0,0] clamp
+// GFX13: v_fma_mix_f32 v255, -|src_scc|, -|vcc_hi|, null op_sel:[0,0,1] clamp ; encoding: [0xff,0xa3,0x20,0xcc,0xfd,0xd6,0xf0,0x61]
+
+v_fma_mix_f32 v5, -1, -|m0|, -1 op_sel:[1,0,0] op_sel_hi:[0,1,0]
+// GFX13: v_fma_mix_f32 v5, -1, -|m0|, -1 op_sel:[1,0,0] op_sel_hi:[0,1,0] ; encoding: [0x05,0x0a,0x20,0xcc,0xc1,0xfa,0x04,0x53]
+
+v_fma_mix_f32 v5, -m0, -1, |vcc_lo|
+// GFX13: v_fma_mix_f32 v5, -m0, -1, |vcc_lo| ; encoding: [0x05,0x04,0x20,0xcc,0x7d,0x82,0xa9,0x21]
+
+v_fma_mix_f32 v5, -|exec_hi|, -|exec_lo|, -|exec_lo| op_sel:[1,1,1] op_sel_hi:[1,1,1]
+// GFX13: v_fma_mix_f32 v5, -|exec_hi|, -|exec_lo|, -|exec_lo| op_sel:[1,1,1] op_sel_hi:[1,1,1] ; encoding: [0x05,0x7f,0x20,0xcc,0x7f,0xfc,0xf8,0xf9]
+
+v_f...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/196252
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