[llvm] [UniformityAnalysis] Rename public api's in UA (NFC) (PR #196251)
Pankaj Dwivedi via llvm-commits
llvm-commits at lists.llvm.org
Thu May 7 00:06:49 PDT 2026
https://github.com/PankajDwivedi-25 created https://github.com/llvm/llvm-project/pull/196251
Rename isUniform to isUniformDef and isDivergent to isDivergentDef on GenericUniformityInfo. The existing names are ambiguous.
REF: https://github.com/llvm/llvm-project/pull/175167#discussion_r3199029395
>From 018cab758b3586b7e85281eb4e7d0cb566f661dc Mon Sep 17 00:00:00 2001
From: padivedi <padivedi at amd.com>
Date: Thu, 7 May 2026 12:31:04 +0530
Subject: [PATCH] [NFC] rename public api's in UA
---
llvm/include/llvm/ADT/GenericUniformityImpl.h | 5 +-
llvm/include/llvm/ADT/GenericUniformityInfo.h | 10 +-
.../SelectionDAG/FunctionLoweringInfo.cpp | 2 +-
.../AMDGPU/AMDGPUAnnotateUniformValues.cpp | 4 +-
.../Target/AMDGPU/AMDGPUCodeGenPrepare.cpp | 4 +-
.../AMDGPUGlobalISelDivergenceLowering.cpp | 4 +-
.../AMDGPU/AMDGPULateCodeGenPrepare.cpp | 2 +-
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 115 ++++++++++--------
.../lib/Target/AMDGPU/AMDGPURegBankSelect.cpp | 2 +-
.../AMDGPU/AMDGPURewriteUndefForPHI.cpp | 4 +-
.../AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp | 2 +-
.../Target/AMDGPU/SIAnnotateControlFlow.cpp | 2 +-
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 2 +-
llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp | 2 +-
llvm/lib/Transforms/Scalar/StructurizeCFG.cpp | 2 +-
.../Target/AMDGPU/UniformityAnalysisTest.cpp | 8 +-
16 files changed, 89 insertions(+), 81 deletions(-)
diff --git a/llvm/include/llvm/ADT/GenericUniformityImpl.h b/llvm/include/llvm/ADT/GenericUniformityImpl.h
index a363b2a3c1702..850ccecc01b5f 100644
--- a/llvm/include/llvm/ADT/GenericUniformityImpl.h
+++ b/llvm/include/llvm/ADT/GenericUniformityImpl.h
@@ -1292,12 +1292,13 @@ GenericUniformityInfo<ContextT>::getFunction() const {
/// A default-constructed instance (no analysis computed) reports everything
/// as uniform, which is conservatively correct for non-divergent targets.
template <typename ContextT>
-bool GenericUniformityInfo<ContextT>::isDivergent(ConstValueRefT V) const {
+bool GenericUniformityInfo<ContextT>::isDivergentDef(ConstValueRefT V) const {
return DA && DA->isDivergent(V);
}
template <typename ContextT>
-bool GenericUniformityInfo<ContextT>::isDivergent(const InstructionT *I) const {
+bool GenericUniformityInfo<ContextT>::isDivergentDef(
+ const InstructionT *I) const {
return DA && DA->isDivergent(*I);
}
diff --git a/llvm/include/llvm/ADT/GenericUniformityInfo.h b/llvm/include/llvm/ADT/GenericUniformityInfo.h
index a504335ec078e..46f260717ad15 100644
--- a/llvm/include/llvm/ADT/GenericUniformityInfo.h
+++ b/llvm/include/llvm/ADT/GenericUniformityInfo.h
@@ -58,17 +58,17 @@ template <typename ContextT> class GenericUniformityInfo {
const FunctionT &getFunction() const;
/// Whether \p V is divergent at its definition.
- bool isDivergent(ConstValueRefT V) const;
+ bool isDivergentDef(ConstValueRefT V) const;
- /// Whether \p V is uniform/non-divergent.
- bool isUniform(ConstValueRefT V) const { return !isDivergent(V); }
+ /// Whether \p V is uniform/non-divergent at its definition.
+ bool isUniformDef(ConstValueRefT V) const { return !isDivergentDef(V); }
// Similar queries for InstructionT. These accept a pointer argument so that
// in LLVM IR, they overload the equivalent queries for Value*. For example,
// if querying whether a CondBrInst is divergent, it should not be treated as
// a Value in LLVM IR.
- bool isUniform(const InstructionT *I) const { return !isDivergent(I); };
- bool isDivergent(const InstructionT *I) const;
+ bool isUniformDef(const InstructionT *I) const { return !isDivergentDef(I); };
+ bool isDivergentDef(const InstructionT *I) const;
/// \brief Whether \p U is divergent. Uses of a uniform value can be
/// divergent.
diff --git a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
index 5edb992e68f4c..067295d05cc2f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
@@ -385,7 +385,7 @@ Register FunctionLoweringInfo::CreateRegs(Type *Ty, bool isDivergent) {
}
Register FunctionLoweringInfo::CreateRegs(const Value *V) {
- return CreateRegs(V->getType(), UA && UA->isDivergent(V) &&
+ return CreateRegs(V->getType(), UA && UA->isDivergentDef(V) &&
!TLI->requiresUniformRegister(*MF, V));
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAnnotateUniformValues.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAnnotateUniformValues.cpp
index 77b042c8e7076..2924a5d6b40bb 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAnnotateUniformValues.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAnnotateUniformValues.cpp
@@ -60,13 +60,13 @@ class AMDGPUAnnotateUniformValues
} // End anonymous namespace
void AMDGPUAnnotateUniformValues::visitCondBrInst(CondBrInst &I) {
- if (UA->isUniform(&I))
+ if (UA->isUniformDef(&I))
setUniformMetadata(&I);
}
void AMDGPUAnnotateUniformValues::visitLoadInst(LoadInst &I) {
Value *Ptr = I.getPointerOperand();
- if (!UA->isUniform(Ptr))
+ if (!UA->isUniformDef(Ptr))
return;
Instruction *PtrI = dyn_cast<Instruction>(Ptr);
if (PtrI)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
index 915d2116bd268..f4268133f05ce 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
@@ -318,7 +318,7 @@ bool AMDGPUCodeGenPrepareImpl::canWidenScalarExtLoad(LoadInst &I) const {
int TySize = DL.getTypeSizeInBits(Ty);
Align Alignment = DL.getValueOrABITypeAlignment(I.getAlign(), Ty);
- return I.isSimple() && TySize < 32 && Alignment >= 4 && UA.isUniform(&I);
+ return I.isSimple() && TySize < 32 && Alignment >= 4 && UA.isUniformDef(&I);
}
unsigned
@@ -370,7 +370,7 @@ bool AMDGPUCodeGenPrepareImpl::replaceMulWithMul24(BinaryOperator &I) const {
return false;
// Prefer scalar if this could be s_mul_i32
- if (UA.isUniform(&I))
+ if (UA.isUniformDef(&I))
return false;
Value *LHS = I.getOperand(0);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
index 6d4487935e260..94aa168a6fef5 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
@@ -111,7 +111,7 @@ void DivergenceLoweringHelper::getCandidatesForLowering(
if (MI.getOpcode() != TargetOpcode::G_PHI)
continue;
Register Dst = MI.getOperand(0).getReg();
- if (MRI->getType(Dst) == S1 && MUI->isDivergent(Dst))
+ if (MRI->getType(Dst) == S1 && MUI->isDivergentDef(Dst))
Vreg1Phis.push_back(&MI);
}
}
@@ -207,7 +207,7 @@ bool DivergenceLoweringHelper::lowerTemporalDivergence() {
DenseMap<Register, Register> TDCache;
for (auto [Reg, UseInst, _] : MUI->getTemporalDivergenceList()) {
- if (MRI->getType(Reg) == LLT::scalar(1) || MUI->isDivergent(Reg) ||
+ if (MRI->getType(Reg) == LLT::scalar(1) || MUI->isDivergentDef(Reg) ||
ILMA.isS32S64LaneMask(Reg))
continue;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp b/llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
index 63e265612cbf7..13b2eb6d927fd 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
@@ -493,7 +493,7 @@ bool AMDGPULateCodeGenPrepare::canWidenScalarExtLoad(LoadInst &LI) const {
if (LI.getAlign() < DL.getABITypeAlign(Ty))
return false;
// It should be uniform, i.e. a scalar load.
- return UA.isUniform(&LI);
+ return UA.isUniformDef(&LI);
}
bool AMDGPULateCodeGenPrepare::visitLoadInst(LoadInst &LI) {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 33611ee8e2768..a98beb8847e4a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -99,57 +99,59 @@ bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID,
case B512:
return MRI.getType(Reg).getSizeInBits() == 512;
case DivAnyTy:
- return MUI.isDivergent(Reg);
+ return MUI.isDivergentDef(Reg);
case UniS1:
- return MRI.getType(Reg) == LLT::scalar(1) && MUI.isUniform(Reg);
+ return MRI.getType(Reg) == LLT::scalar(1) && MUI.isUniformDef(Reg);
case UniS16:
- return MRI.getType(Reg) == LLT::scalar(16) && MUI.isUniform(Reg);
+ return MRI.getType(Reg) == LLT::scalar(16) && MUI.isUniformDef(Reg);
case UniS32:
- return MRI.getType(Reg) == LLT::scalar(32) && MUI.isUniform(Reg);
+ return MRI.getType(Reg) == LLT::scalar(32) && MUI.isUniformDef(Reg);
case UniS64:
- return MRI.getType(Reg) == LLT::scalar(64) && MUI.isUniform(Reg);
+ return MRI.getType(Reg) == LLT::scalar(64) && MUI.isUniformDef(Reg);
case UniS128:
- return MRI.getType(Reg) == LLT::scalar(128) && MUI.isUniform(Reg);
+ return MRI.getType(Reg) == LLT::scalar(128) && MUI.isUniformDef(Reg);
case UniP0:
- return MRI.getType(Reg) == LLT::pointer(0, 64) && MUI.isUniform(Reg);
+ return MRI.getType(Reg) == LLT::pointer(0, 64) && MUI.isUniformDef(Reg);
case UniP1:
- return MRI.getType(Reg) == LLT::pointer(1, 64) && MUI.isUniform(Reg);
+ return MRI.getType(Reg) == LLT::pointer(1, 64) && MUI.isUniformDef(Reg);
case UniP2:
- return MRI.getType(Reg) == LLT::pointer(2, 32) && MUI.isUniform(Reg);
+ return MRI.getType(Reg) == LLT::pointer(2, 32) && MUI.isUniformDef(Reg);
case UniP3:
- return MRI.getType(Reg) == LLT::pointer(3, 32) && MUI.isUniform(Reg);
+ return MRI.getType(Reg) == LLT::pointer(3, 32) && MUI.isUniformDef(Reg);
case UniP4:
- return MRI.getType(Reg) == LLT::pointer(4, 64) && MUI.isUniform(Reg);
+ return MRI.getType(Reg) == LLT::pointer(4, 64) && MUI.isUniformDef(Reg);
case UniP5:
- return MRI.getType(Reg) == LLT::pointer(5, 32) && MUI.isUniform(Reg);
+ return MRI.getType(Reg) == LLT::pointer(5, 32) && MUI.isUniformDef(Reg);
case UniP8:
- return MRI.getType(Reg) == LLT::pointer(8, 128) && MUI.isUniform(Reg);
+ return MRI.getType(Reg) == LLT::pointer(8, 128) && MUI.isUniformDef(Reg);
case UniPtr32:
- return isAnyPtr(MRI.getType(Reg), 32) && MUI.isUniform(Reg);
+ return isAnyPtr(MRI.getType(Reg), 32) && MUI.isUniformDef(Reg);
case UniPtr64:
- return isAnyPtr(MRI.getType(Reg), 64) && MUI.isUniform(Reg);
+ return isAnyPtr(MRI.getType(Reg), 64) && MUI.isUniformDef(Reg);
case UniPtr128:
- return isAnyPtr(MRI.getType(Reg), 128) && MUI.isUniform(Reg);
+ return isAnyPtr(MRI.getType(Reg), 128) && MUI.isUniformDef(Reg);
case UniV2S16:
- return MRI.getType(Reg) == LLT::fixed_vector(2, 16) && MUI.isUniform(Reg);
+ return MRI.getType(Reg) == LLT::fixed_vector(2, 16) &&
+ MUI.isUniformDef(Reg);
case UniV2S32:
- return MRI.getType(Reg) == LLT::fixed_vector(2, 32) && MUI.isUniform(Reg);
+ return MRI.getType(Reg) == LLT::fixed_vector(2, 32) &&
+ MUI.isUniformDef(Reg);
case UniB32:
- return MRI.getType(Reg).getSizeInBits() == 32 && MUI.isUniform(Reg);
+ return MRI.getType(Reg).getSizeInBits() == 32 && MUI.isUniformDef(Reg);
case UniB64:
- return MRI.getType(Reg).getSizeInBits() == 64 && MUI.isUniform(Reg);
+ return MRI.getType(Reg).getSizeInBits() == 64 && MUI.isUniformDef(Reg);
case UniB96:
- return MRI.getType(Reg).getSizeInBits() == 96 && MUI.isUniform(Reg);
+ return MRI.getType(Reg).getSizeInBits() == 96 && MUI.isUniformDef(Reg);
case UniB128:
- return MRI.getType(Reg).getSizeInBits() == 128 && MUI.isUniform(Reg);
+ return MRI.getType(Reg).getSizeInBits() == 128 && MUI.isUniformDef(Reg);
case UniB160:
- return MRI.getType(Reg).getSizeInBits() == 160 && MUI.isUniform(Reg);
+ return MRI.getType(Reg).getSizeInBits() == 160 && MUI.isUniformDef(Reg);
case UniB256:
- return MRI.getType(Reg).getSizeInBits() == 256 && MUI.isUniform(Reg);
+ return MRI.getType(Reg).getSizeInBits() == 256 && MUI.isUniformDef(Reg);
case UniB512:
- return MRI.getType(Reg).getSizeInBits() == 512 && MUI.isUniform(Reg);
+ return MRI.getType(Reg).getSizeInBits() == 512 && MUI.isUniformDef(Reg);
case UniBRC: {
- if (!MUI.isUniform(Reg))
+ if (!MUI.isUniformDef(Reg))
return false;
// Check if there is SGPR register class of same size as the LLT.
const SIRegisterInfo *TRI =
@@ -160,59 +162,64 @@ bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID,
return LLTSize >= 32 && TRI->getSGPRClassForBitWidth(LLTSize);
}
case DivS1:
- return MRI.getType(Reg) == LLT::scalar(1) && MUI.isDivergent(Reg);
+ return MRI.getType(Reg) == LLT::scalar(1) && MUI.isDivergentDef(Reg);
case DivS16:
- return MRI.getType(Reg) == LLT::scalar(16) && MUI.isDivergent(Reg);
+ return MRI.getType(Reg) == LLT::scalar(16) && MUI.isDivergentDef(Reg);
case DivS32:
- return MRI.getType(Reg) == LLT::scalar(32) && MUI.isDivergent(Reg);
+ return MRI.getType(Reg) == LLT::scalar(32) && MUI.isDivergentDef(Reg);
case DivS64:
- return MRI.getType(Reg) == LLT::scalar(64) && MUI.isDivergent(Reg);
+ return MRI.getType(Reg) == LLT::scalar(64) && MUI.isDivergentDef(Reg);
case DivS128:
- return MRI.getType(Reg) == LLT::scalar(128) && MUI.isDivergent(Reg);
+ return MRI.getType(Reg) == LLT::scalar(128) && MUI.isDivergentDef(Reg);
case DivP0:
- return MRI.getType(Reg) == LLT::pointer(0, 64) && MUI.isDivergent(Reg);
+ return MRI.getType(Reg) == LLT::pointer(0, 64) && MUI.isDivergentDef(Reg);
case DivP1:
- return MRI.getType(Reg) == LLT::pointer(1, 64) && MUI.isDivergent(Reg);
+ return MRI.getType(Reg) == LLT::pointer(1, 64) && MUI.isDivergentDef(Reg);
case DivP2:
- return MRI.getType(Reg) == LLT::pointer(2, 32) && MUI.isDivergent(Reg);
+ return MRI.getType(Reg) == LLT::pointer(2, 32) && MUI.isDivergentDef(Reg);
case DivP3:
- return MRI.getType(Reg) == LLT::pointer(3, 32) && MUI.isDivergent(Reg);
+ return MRI.getType(Reg) == LLT::pointer(3, 32) && MUI.isDivergentDef(Reg);
case DivP4:
- return MRI.getType(Reg) == LLT::pointer(4, 64) && MUI.isDivergent(Reg);
+ return MRI.getType(Reg) == LLT::pointer(4, 64) && MUI.isDivergentDef(Reg);
case DivP5:
- return MRI.getType(Reg) == LLT::pointer(5, 32) && MUI.isDivergent(Reg);
+ return MRI.getType(Reg) == LLT::pointer(5, 32) && MUI.isDivergentDef(Reg);
case DivPtr32:
- return isAnyPtr(MRI.getType(Reg), 32) && MUI.isDivergent(Reg);
+ return isAnyPtr(MRI.getType(Reg), 32) && MUI.isDivergentDef(Reg);
case DivPtr64:
- return isAnyPtr(MRI.getType(Reg), 64) && MUI.isDivergent(Reg);
+ return isAnyPtr(MRI.getType(Reg), 64) && MUI.isDivergentDef(Reg);
case DivPtr128:
- return isAnyPtr(MRI.getType(Reg), 128) && MUI.isDivergent(Reg);
+ return isAnyPtr(MRI.getType(Reg), 128) && MUI.isDivergentDef(Reg);
case DivV2S16:
- return MRI.getType(Reg) == LLT::fixed_vector(2, 16) && MUI.isDivergent(Reg);
+ return MRI.getType(Reg) == LLT::fixed_vector(2, 16) &&
+ MUI.isDivergentDef(Reg);
case DivV2S32:
- return MRI.getType(Reg) == LLT::fixed_vector(2, 32) && MUI.isDivergent(Reg);
+ return MRI.getType(Reg) == LLT::fixed_vector(2, 32) &&
+ MUI.isDivergentDef(Reg);
case DivV3S32:
- return MRI.getType(Reg) == LLT::fixed_vector(3, 32) && MUI.isDivergent(Reg);
+ return MRI.getType(Reg) == LLT::fixed_vector(3, 32) &&
+ MUI.isDivergentDef(Reg);
case DivV4S16:
- return MRI.getType(Reg) == LLT::fixed_vector(4, 16) && MUI.isDivergent(Reg);
+ return MRI.getType(Reg) == LLT::fixed_vector(4, 16) &&
+ MUI.isDivergentDef(Reg);
case DivV6S32:
- return MRI.getType(Reg) == LLT::fixed_vector(6, 32) && MUI.isDivergent(Reg);
+ return MRI.getType(Reg) == LLT::fixed_vector(6, 32) &&
+ MUI.isDivergentDef(Reg);
case DivB32:
- return MRI.getType(Reg).getSizeInBits() == 32 && MUI.isDivergent(Reg);
+ return MRI.getType(Reg).getSizeInBits() == 32 && MUI.isDivergentDef(Reg);
case DivB64:
- return MRI.getType(Reg).getSizeInBits() == 64 && MUI.isDivergent(Reg);
+ return MRI.getType(Reg).getSizeInBits() == 64 && MUI.isDivergentDef(Reg);
case DivB96:
- return MRI.getType(Reg).getSizeInBits() == 96 && MUI.isDivergent(Reg);
+ return MRI.getType(Reg).getSizeInBits() == 96 && MUI.isDivergentDef(Reg);
case DivB128:
- return MRI.getType(Reg).getSizeInBits() == 128 && MUI.isDivergent(Reg);
+ return MRI.getType(Reg).getSizeInBits() == 128 && MUI.isDivergentDef(Reg);
case DivB160:
- return MRI.getType(Reg).getSizeInBits() == 160 && MUI.isDivergent(Reg);
+ return MRI.getType(Reg).getSizeInBits() == 160 && MUI.isDivergentDef(Reg);
case DivB256:
- return MRI.getType(Reg).getSizeInBits() == 256 && MUI.isDivergent(Reg);
+ return MRI.getType(Reg).getSizeInBits() == 256 && MUI.isDivergentDef(Reg);
case DivB512:
- return MRI.getType(Reg).getSizeInBits() == 512 && MUI.isDivergent(Reg);
+ return MRI.getType(Reg).getSizeInBits() == 512 && MUI.isDivergentDef(Reg);
case DivBRC: {
- if (!MUI.isDivergent(Reg))
+ if (!MUI.isDivergentDef(Reg))
return false;
// Check if there is VGPR register class of same size as the LLT.
const SIRegisterInfo *TRI =
@@ -317,7 +324,7 @@ SetOfRulesForOpcode::findMappingForMI(const MachineInstr &MI,
Slot = getFastPredicateSlot(LLTToId(MRI.getType(Reg)));
if (Slot != -1)
- return MUI.isUniform(Reg) ? &Uni[Slot] : &Div[Slot];
+ return MUI.isUniformDef(Reg) ? &Uni[Slot] : &Div[Slot];
}
// Slow search for more complex rules.
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp
index 493b7541cdd81..ec32cba9b7e53 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp
@@ -111,7 +111,7 @@ class RegBankSelectHelper {
const RegisterBank *getRegBankToAssign(Register Reg) {
if (!isTemporalDivergenceCopy(Reg) &&
- (MUI.isUniform(Reg) || ILMA.isS32S64LaneMask(Reg)))
+ (MUI.isUniformDef(Reg) || ILMA.isS32S64LaneMask(Reg)))
return SgprRB;
if (MRI.getType(Reg) == LLT::scalar(1))
return VccRB;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURewriteUndefForPHI.cpp b/llvm/lib/Target/AMDGPU/AMDGPURewriteUndefForPHI.cpp
index 1c135f09080e1..05a3d86f539c4 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURewriteUndefForPHI.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURewriteUndefForPHI.cpp
@@ -102,7 +102,7 @@ bool rewritePHIs(Function &F, UniformityInfo &UA, DominatorTree *DT) {
SmallVector<PHINode *> ToBeDeleted;
for (auto &BB : F) {
for (auto &PHI : BB.phis()) {
- if (UA.isDivergent(&PHI))
+ if (UA.isDivergentDef(&PHI))
continue;
// The unique incoming value except undef/poison for the PHI node.
@@ -144,7 +144,7 @@ bool rewritePHIs(Function &F, UniformityInfo &UA, DominatorTree *DT) {
// TODO: We should still be able to replace undef value if the unique
// value is a Constant.
if (!UniqueDefinedIncoming || Undefs.empty() ||
- !UA.isDivergent(DominateBB->getTerminator()))
+ !UA.isDivergentDef(DominateBB->getTerminator()))
continue;
// We only replace the undef when DominateBB truly dominates all the
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp b/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp
index 36e51421c5ae4..2050dce0176b8 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp
@@ -123,7 +123,7 @@ static bool isUniformlyReached(const UniformityInfo &UA, BasicBlock &BB) {
while (!Stack.empty()) {
BasicBlock *Top = Stack.pop_back_val();
- if (!UA.isUniform(Top->getTerminator()))
+ if (!UA.isUniformDef(Top->getTerminator()))
return false;
for (BasicBlock *Pred : predecessors(Top)) {
diff --git a/llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp b/llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp
index 54ec4a51a4ab3..d6af5157886e5 100644
--- a/llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp
+++ b/llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp
@@ -128,7 +128,7 @@ void SIAnnotateControlFlow::initialize(const GCNSubtarget &ST) {
/// Is the branch condition uniform or did the StructurizeCFG pass
/// consider it as such?
bool SIAnnotateControlFlow::isUniform(CondBrInst *T) {
- return UA->isUniform(T) || T->hasMetadata("structurizecfg.uniform");
+ return UA->isUniformDef(T) || T->hasMetadata("structurizecfg.uniform");
}
/// Is BB the last block saved on the stack ?
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 20599228beea8..7799a6f461196 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -19790,7 +19790,7 @@ bool SITargetLowering::isSDNodeSourceOfDivergence(const SDNode *N,
return !TRI->isSGPRReg(MRI, Reg);
if (const Value *V = FLI->getValueFromVirtualReg(R->getReg()))
- return UA->isDivergent(V);
+ return UA->isDivergentDef(V);
assert(Reg == FLI->DemoteRegister || isCopyFromRegOfInlineAsm(N));
return !TRI->isSGPRReg(MRI, Reg);
diff --git a/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp b/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
index 0c5e3b5039309..76075bed8db45 100644
--- a/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
+++ b/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
@@ -780,7 +780,7 @@ static bool isSCEVUniform(const SCEV *S, UniformityInfo &UI) {
if (isa<SCEVConstant>(S))
return true;
if (auto *U = dyn_cast<SCEVUnknown>(S))
- return UI.isUniform(U->getValue());
+ return UI.isUniformDef(U->getValue());
for (const SCEV *Op : S->operands()) {
if (!isSCEVUniform(Op, UI))
return false;
diff --git a/llvm/lib/Transforms/Scalar/StructurizeCFG.cpp b/llvm/lib/Transforms/Scalar/StructurizeCFG.cpp
index 04ece92b74375..47327dd5edf43 100644
--- a/llvm/lib/Transforms/Scalar/StructurizeCFG.cpp
+++ b/llvm/lib/Transforms/Scalar/StructurizeCFG.cpp
@@ -1302,7 +1302,7 @@ static bool hasOnlyUniformBranches(Region *R, unsigned UniformMDKindID,
if (!Br)
continue;
- if (!UA.isUniform(Br))
+ if (!UA.isUniformDef(Br))
return false;
// One of our direct children is conditional.
diff --git a/llvm/unittests/Target/AMDGPU/UniformityAnalysisTest.cpp b/llvm/unittests/Target/AMDGPU/UniformityAnalysisTest.cpp
index ae44d3ef6cbf2..f220759347f79 100644
--- a/llvm/unittests/Target/AMDGPU/UniformityAnalysisTest.cpp
+++ b/llvm/unittests/Target/AMDGPU/UniformityAnalysisTest.cpp
@@ -80,9 +80,9 @@ TEST(UniformityAnalysis, NewValueIsConservativelyDivergent) {
// Existing values from the analysis are uniform (kernel args are inreg).
Instruction *AddInst = &*F->getEntryBlock().begin();
ASSERT_TRUE(isa<BinaryOperator>(AddInst));
- EXPECT_FALSE(UI.isDivergent(AddInst)) << "%add should be uniform";
- EXPECT_FALSE(UI.isDivergent(F->getArg(0))) << "%a should be uniform";
- EXPECT_FALSE(UI.isDivergent(F->getArg(1))) << "%b should be uniform";
+ EXPECT_FALSE(UI.isDivergentDef(AddInst)) << "%add should be uniform";
+ EXPECT_FALSE(UI.isDivergentDef(F->getArg(0))) << "%a should be uniform";
+ EXPECT_FALSE(UI.isDivergentDef(F->getArg(1))) << "%b should be uniform";
// Create a new instruction after analysis. It was not present during
// analysis, so it is not in UniformValues and must be conservatively
@@ -90,6 +90,6 @@ TEST(UniformityAnalysis, NewValueIsConservativelyDivergent) {
IRBuilder<> Builder(AddInst->getNextNode());
Value *NewInst = Builder.CreateMul(F->getArg(0), F->getArg(1), "new_mul");
- EXPECT_TRUE(UI.isDivergent(NewInst))
+ EXPECT_TRUE(UI.isDivergentDef(NewInst))
<< "New instruction created after analysis must be reported divergent";
}
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