[llvm] [RISCV][NFC] Add VPatUnaryVL_V class (PR #196229)

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llvmorg-github-actions[bot] wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Pengcheng Wang (wangpc-pp)

<details>
<summary>Changes</summary>

So that we can reuse it.


---
Full diff: https://github.com/llvm/llvm-project/pull/196229.diff


1 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td (+28-13) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index 15709c2bf7178..0264295c247fe 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -758,6 +758,30 @@ def sew16simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<16>", []>;
 def sew32simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<32>", []>;
 def sew64simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<64>", []>;
 
+class VPatUnaryVL_V<SDPatternOperator vop,
+                    string instruction_name,
+                    string suffix,
+                    ValueType result_type,
+                    ValueType op1_type,
+                    ValueType mask_type,
+                    int log2sew,
+                    LMULInfo vlmul,
+                    VReg result_reg_class,
+                    VReg op1_reg_class,
+                    bit isSEWAware = 0>
+    : Pat<(result_type (vop
+                       (op1_type op1_reg_class:$rs2),
+                       (result_type result_reg_class:$passthru),
+                       (mask_type VMV0:$vm),
+                       VLOpFrag)),
+      (!cast<Instruction>(
+                   !if(isSEWAware,
+                       instruction_name#"_"#suffix#"_"#vlmul.MX#"_E"#!shl(1, log2sew)#"_MASK",
+                       instruction_name#"_"#suffix#"_"#vlmul.MX#"_MASK"))
+                   result_reg_class:$passthru,
+                   op1_reg_class:$rs2,
+                   (mask_type VMV0:$vm), GPR:$vl, log2sew, TAIL_AGNOSTIC)>;
+
 class VPatBinaryVL_V<SDPatternOperator vop,
                      string instruction_name,
                      string suffix,
@@ -1990,19 +2014,10 @@ multiclass VPatUnaryVL_V<SDPatternOperator op, string instruction_name,
                          Predicate predicate = HasStdExtZvbb> {
   foreach vti = AllIntegerVectors in {
     let Predicates = !listconcat([predicate],
-                                 GetVTypePredicates<vti>.Predicates) in {
-      def : Pat<(vti.Vector (op (vti.Vector vti.RegClass:$rs1),
-                                (vti.Vector vti.RegClass:$passthru),
-                                (vti.Mask VMV0:$vm),
-                                VLOpFrag)),
-                (!cast<Instruction>(instruction_name#"_V_"#vti.LMul.MX#"_MASK")
-                   vti.RegClass:$passthru,
-                   vti.RegClass:$rs1,
-                   (vti.Mask VMV0:$vm),
-                   GPR:$vl,
-                   vti.Log2SEW,
-                   TAIL_AGNOSTIC)>;
-    }
+                                 GetVTypePredicates<vti>.Predicates) in
+    def : VPatUnaryVL_V<op, instruction_name, "V",
+                        vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW,
+                        vti.LMul, vti.RegClass, vti.RegClass>;
   }
 }
 

``````````

</details>


https://github.com/llvm/llvm-project/pull/196229