[llvm] 468dfaa - [Mips] Optimize instr cvt.s.d+mfc1+slti to mfhc1+slti (#194806)

[via llvm-commits]

Author: yingopq
Date: 2026-05-07T11:30:04+08:00
New Revision: 468dfaafe613415ed662f2abff9720f0fb1a1b8a

URL: https://github.com/llvm/llvm-project/commit/468dfaafe613415ed662f2abff9720f0fb1a1b8a
DIFF: https://github.com/llvm/llvm-project/commit/468dfaafe613415ed662f2abff9720f0fb1a1b8a.diff

LOG: [Mips] Optimize instr cvt.s.d+mfc1+slti to mfhc1+slti (#194806)

Fix #171262.

Added: 
    llvm/test/CodeGen/Mips/cvt-mfc1-slti.ll

Modified: 
    llvm/lib/Target/Mips/MipsInstrFPU.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/Mips/MipsInstrFPU.td b/llvm/lib/Target/Mips/MipsInstrFPU.td
index 36e22c7fecbb5..fa5bdca10f435 100644
--- a/llvm/lib/Target/Mips/MipsInstrFPU.td
+++ b/llvm/lib/Target/Mips/MipsInstrFPU.td
@@ -1020,6 +1020,14 @@ def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
 def : MipsPat<(MipsMTC1_D64 GPR32Opnd:$src),
               (MTC1_D64 GPR32Opnd:$src)>, ISA_MIPS1, FGR_64;
 
+def : MipsPat<(setlt (i32 (bitconvert (f32 (fpround AFGR64Opnd:$src)))), 0),
+           (SLTi (MFHC1_D32 AFGR64Opnd:$src), 0)>,
+           ISA_MIPS32R2, FGR_32;
+
+def : MipsPat<(setlt (i32 (bitconvert (f32 (fpround FGR64Opnd:$src)))), 0),
+          (SLTi (MFHC1_D64 FGR64Opnd:$src), 0)>,
+          ISA_MIPS32R2, FGR_64;
+
 def : MipsPat<(f64 (any_sint_to_fp GPR32Opnd:$src)),
               (PseudoCVT_D32_W GPR32Opnd:$src)>, FGR_32;
 let AdditionalPredicates = [NotInMicroMips] in {

diff  --git a/llvm/test/CodeGen/Mips/cvt-mfc1-slti.ll b/llvm/test/CodeGen/Mips/cvt-mfc1-slti.ll
new file mode 100644
index 0000000000000..9bea2d52d5227
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/cvt-mfc1-slti.ll
@@ -0,0 +1,37 @@
+; RUN: llc -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32 -verify-machineinstrs < %s | FileCheck %s -check-prefix=MIPS32
+; RUN: llc -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32r2 -verify-machineinstrs < %s | FileCheck %s -check-prefix=MIPS32R2
+; RUN: llc -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32r6 -verify-machineinstrs < %s | FileCheck %s -check-prefix=MIPS32R6
+
+define i32 @test_sign_bit(double %a) nounwind {
+; MIPS32-LABEL: test_sign_bit:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    cvt.s.d $f0, $f12
+; MIPS32-NEXT:    mfc1 $1, $f0
+; MIPS32-NEXT:    slti $1, $1, 0
+; MIPS32-NEXT:    addiu	$2, $zero, -4
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    or $2, $1, $2
+
+; MIPS32R2-LABEL: test_sign_bit:
+; MIPS32R2:       # %bb.0: # %entry
+; MIPS32R2-NEXT:    mfhc1 $1, $f12
+; MIPS32R2-NEXT:    slti $1, $1, 0
+; MIPS32R2-NEXT:    addiu $2, $zero, -4
+; MIPS32R2-NEXT:    jr $ra
+; MIPS32R2-NEXT:    or $2, $1, $2
+
+; MIPS32R6-LABEL: test_sign_bit:
+; MIPS32R6:       # %bb.0: # %entry
+; MIPS32R6-NEXT:    mfhc1 $1, $f12
+; MIPS32R6-NEXT:    slti $1, $1, 0
+; MIPS32R6-NEXT:    addiu $2, $zero, -4
+; MIPS32R6-NEXT:    jr $ra
+; MIPS32R6-NEXT:    or $2, $1, $2
+
+entry:
+  %conv = fptrunc double %a to float
+  %i_val = bitcast float %conv to i32
+  %1 = icmp slt i32 %i_val, 0
+  %2 = select i1 %1, i32 -3, i32 -4
+  ret i32 %2
+}