[llvm] AMDGPU/GlobalISel: RegBankLegalize rules for cvt_off_f32_i4 (PR #196190)

[via llvm-commits]

https://github.com/vangthao95 created https://github.com/llvm/llvm-project/pull/196190

None

>From b54cb1da2947334a67217ccc7f88bb54547bd5e5 Mon Sep 17 00:00:00 2001
From: Vang Thao <Vang.Thao at amd.com>
Date: Wed, 6 May 2026 17:24:36 -0400
Subject: [PATCH] AMDGPU/GlobalISel: RegBankLegalize rules for cvt_off_f32_i4

---
 .../Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp  |  3 ++-
 .../CodeGen/AMDGPU/llvm.amdgcn.cvt.off.f32.i4.ll  | 15 ++++++++++++---
 2 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 33611ee8e2768..d92f72ff2aba0 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1752,7 +1752,8 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
       .Uni(S32, {{UniInVgprS32}, {IntrId, Vgpr32, Vgpr32, Vgpr32}})
       .Div(S32, {{Vgpr32}, {IntrId, Vgpr32, Vgpr32, Vgpr32}});
 
-  addRulesForIOpcs({amdgcn_cvt_f32_bf8, amdgcn_cvt_f32_fp8}, Standard)
+  addRulesForIOpcs(
+      {amdgcn_cvt_off_f32_i4, amdgcn_cvt_f32_bf8, amdgcn_cvt_f32_fp8}, Standard)
       .Uni(S32, {{UniInVgprS32}, {IntrId, Vgpr32}})
       .Div(S32, {{Vgpr32}, {IntrId, Vgpr32}});
 
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.off.f32.i4.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.off.f32.i4.ll
index e504eb7a5a124..083324e8b68c8 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.off.f32.i4.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.off.f32.i4.ll
@@ -1,10 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc --global-isel=0 -mtriple=amdgcn -mcpu=tahiti %s -o - | FileCheck %s
-; RUN: llc --global-isel=1 -mtriple=amdgcn -mcpu=tahiti %s -o - | FileCheck %s
+; RUN: llc --global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=tahiti %s -o - | FileCheck %s
 ; RUN: llc --global-isel=0 -mtriple=amdgcn -mcpu=tonga %s -o - | FileCheck %s
-; RUN: llc --global-isel=1 -mtriple=amdgcn -mcpu=tonga %s -o - | FileCheck %s
+; RUN: llc --global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=tonga %s -o - | FileCheck %s
 ; RUN: llc --global-isel=0 -mtriple=amdgcn -mcpu=gfx90a %s -o - | FileCheck %s
-; RUN: llc --global-isel=1 -mtriple=amdgcn -mcpu=gfx90a %s -o - | FileCheck %s
+; RUN: llc --global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx90a %s -o - | FileCheck %s
 
 declare float @llvm.amdgcn.cvt.off.f32.i4(i32)
 
@@ -17,6 +17,15 @@ define amdgpu_cs float @cvt_var(i32 %a) {
   ret float %ret
 }
 
+define amdgpu_ps float @cvt_var_s(i32 inreg %a) {
+; CHECK-LABEL: cvt_var_s:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    v_cvt_off_f32_i4_e32 v0, s0
+; CHECK-NEXT:    ; return to shader part epilog
+  %ret = call float @llvm.amdgcn.cvt.off.f32.i4(i32 %a)
+  ret float %ret
+}
+
 define amdgpu_cs float @cvt_imm() {
 ; CHECK-LABEL: cvt_imm:
 ; CHECK:       ; %bb.0: