[llvm] [AArch64] Add tests for sqabs and sqneg patterns. NFC (PR #196156)
David Green via llvm-commits
llvm-commits at lists.llvm.org
Wed May 6 12:48:43 PDT 2026
https://github.com/davemgreen created https://github.com/llvm/llvm-project/pull/196156
None
>From 9f69e9fe6c60a8c24bdfa256bec28804fa1227c6 Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Wed, 6 May 2026 20:48:32 +0100
Subject: [PATCH] [AArch64] Add tests for sqabs and sqneg patterns. NFC
---
llvm/test/CodeGen/AArch64/vqabs.ll | 222 +++++++++++++++++++++++++++++
llvm/test/CodeGen/AArch64/vqneg.ll | 171 ++++++++++++++++++++++
2 files changed, 393 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/vqabs.ll
create mode 100644 llvm/test/CodeGen/AArch64/vqneg.ll
diff --git a/llvm/test/CodeGen/AArch64/vqabs.ll b/llvm/test/CodeGen/AArch64/vqabs.ll
new file mode 100644
index 0000000000000..a05bed23b14e2
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/vqabs.ll
@@ -0,0 +1,222 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=aarch64 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc -mtriple=aarch64 -global-isel %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+
+define <16 x i8> @vqabs_test16(<16 x i8> %A) nounwind {
+; CHECK-LABEL: vqabs_test16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.16b, #128
+; CHECK-NEXT: movi v2.16b, #127
+; CHECK-NEXT: neg v3.16b, v0.16b
+; CHECK-NEXT: cmeq v1.16b, v0.16b, v1.16b
+; CHECK-NEXT: bsl v1.16b, v2.16b, v3.16b
+; CHECK-NEXT: cmgt v2.16b, v0.16b, #0
+; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-NEXT: ret
+entry:
+ %0 = icmp sgt <16 x i8> %A, zeroinitializer
+ %1 = icmp eq <16 x i8> %A, <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>
+ %2 = sub nsw <16 x i8> zeroinitializer, %A
+ %3 = select <16 x i1> %1, <16 x i8> <i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127>, <16 x i8> %2
+ %4 = select <16 x i1> %0, <16 x i8> %A, <16 x i8> %3
+ ret <16 x i8> %4
+}
+
+define <8 x i16> @vqabs_test8(<8 x i16> %A) nounwind {
+; CHECK-SD-LABEL: vqabs_test8:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v1.8h, #128, lsl #8
+; CHECK-SD-NEXT: neg v2.8h, v0.8h
+; CHECK-SD-NEXT: cmgt v3.8h, v0.8h, #0
+; CHECK-SD-NEXT: cmeq v1.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: bic v2.16b, v2.16b, v1.16b
+; CHECK-SD-NEXT: bic v1.8h, #128, lsl #8
+; CHECK-SD-NEXT: orr v1.16b, v1.16b, v2.16b
+; CHECK-SD-NEXT: bif v0.16b, v1.16b, v3.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vqabs_test8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v1.8h, #128, lsl #8
+; CHECK-GI-NEXT: mvni v2.8h, #128, lsl #8
+; CHECK-GI-NEXT: neg v3.8h, v0.8h
+; CHECK-GI-NEXT: cmeq v1.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: bsl v1.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: cmgt v2.8h, v0.8h, #0
+; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-GI-NEXT: ret
+entry:
+ %0 = icmp sgt <8 x i16> %A, zeroinitializer
+ %1 = icmp eq <8 x i16> %A, <i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768>
+ %2 = sub nsw <8 x i16> zeroinitializer, %A
+ %3 = select <8 x i1> %1, <8 x i16> <i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767>, <8 x i16> %2
+ %4 = select <8 x i1> %0, <8 x i16> %A, <8 x i16> %3
+ ret <8 x i16> %4
+}
+
+define <4 x i32> @vqabs_test4(<4 x i32> %A) nounwind {
+; CHECK-SD-LABEL: vqabs_test4:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v1.4s, #128, lsl #24
+; CHECK-SD-NEXT: neg v2.4s, v0.4s
+; CHECK-SD-NEXT: cmgt v3.4s, v0.4s, #0
+; CHECK-SD-NEXT: cmeq v1.4s, v0.4s, v1.4s
+; CHECK-SD-NEXT: bic v2.16b, v2.16b, v1.16b
+; CHECK-SD-NEXT: bic v1.4s, #128, lsl #24
+; CHECK-SD-NEXT: orr v1.16b, v1.16b, v2.16b
+; CHECK-SD-NEXT: bif v0.16b, v1.16b, v3.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vqabs_test4:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v1.4s, #128, lsl #24
+; CHECK-GI-NEXT: mvni v2.4s, #128, lsl #24
+; CHECK-GI-NEXT: neg v3.4s, v0.4s
+; CHECK-GI-NEXT: cmeq v1.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: bsl v1.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: cmgt v2.4s, v0.4s, #0
+; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-GI-NEXT: ret
+entry:
+ %0 = icmp sgt <4 x i32> %A, zeroinitializer
+ %1 = icmp eq <4 x i32> %A, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
+ %2 = sub nsw <4 x i32> zeroinitializer, %A
+ %3 = select <4 x i1> %1, <4 x i32> <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>, <4 x i32> %2
+ %4 = select <4 x i1> %0, <4 x i32> %A, <4 x i32> %3
+ ret <4 x i32> %4
+}
+
+define <16 x i8> @vqabs_sat_v16i8(<16 x i8> %A) {
+; CHECK-LABEL: vqabs_sat_v16i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.2d, #0000000000000000
+; CHECK-NEXT: cmgt v2.16b, v0.16b, #0
+; CHECK-NEXT: sqsub v1.16b, v1.16b, v0.16b
+; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-NEXT: ret
+entry:
+ %0 = icmp sgt <16 x i8> %A, zeroinitializer
+ %1 = tail call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> zeroinitializer, <16 x i8> %A)
+ %2 = select <16 x i1> %0, <16 x i8> %A, <16 x i8> %1
+ ret <16 x i8> %2
+}
+
+define <8 x i16> @vqabs_sat_v8i16(<8 x i16> %A) {
+; CHECK-LABEL: vqabs_sat_v8i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.2d, #0000000000000000
+; CHECK-NEXT: cmgt v2.8h, v0.8h, #0
+; CHECK-NEXT: sqsub v1.8h, v1.8h, v0.8h
+; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-NEXT: ret
+entry:
+ %0 = icmp sgt <8 x i16> %A, zeroinitializer
+ %1 = tail call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> zeroinitializer, <8 x i16> %A)
+ %2 = select <8 x i1> %0, <8 x i16> %A, <8 x i16> %1
+ ret <8 x i16> %2
+}
+
+define <4 x i32> @vqabs_sat_v4i32(<4 x i32> %A) {
+; CHECK-LABEL: vqabs_sat_v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.2d, #0000000000000000
+; CHECK-NEXT: cmgt v2.4s, v0.4s, #0
+; CHECK-NEXT: sqsub v1.4s, v1.4s, v0.4s
+; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-NEXT: ret
+entry:
+ %0 = icmp sgt <4 x i32> %A, zeroinitializer
+ %1 = tail call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> zeroinitializer, <4 x i32> %A)
+ %2 = select <4 x i1> %0, <4 x i32> %A, <4 x i32> %1
+ ret <4 x i32> %2
+}
+
+define <2 x i64> @vqabs_sat_v2i64(<2 x i64> %A) {
+; CHECK-LABEL: vqabs_sat_v2i64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.2d, #0000000000000000
+; CHECK-NEXT: cmgt v2.2d, v0.2d, #0
+; CHECK-NEXT: sqsub v1.2d, v1.2d, v0.2d
+; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-NEXT: ret
+entry:
+ %0 = icmp sgt <2 x i64> %A, zeroinitializer
+ %1 = tail call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> zeroinitializer, <2 x i64> %A)
+ %2 = select <2 x i1> %0, <2 x i64> %A, <2 x i64> %1
+ ret <2 x i64> %2
+}
+
+define <8 x i8> @vqabs_sat_v8i8(<8 x i8> %A) {
+; CHECK-LABEL: vqabs_sat_v8i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.2d, #0000000000000000
+; CHECK-NEXT: cmgt v2.8b, v0.8b, #0
+; CHECK-NEXT: sqsub v1.8b, v1.8b, v0.8b
+; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b
+; CHECK-NEXT: ret
+entry:
+ %0 = icmp sgt <8 x i8> %A, zeroinitializer
+ %1 = tail call <8 x i8> @llvm.ssub.sat.v8i8(<8 x i8> zeroinitializer, <8 x i8> %A)
+ %2 = select <8 x i1> %0, <8 x i8> %A, <8 x i8> %1
+ ret <8 x i8> %2
+}
+
+define <4 x i16> @vqabs_sat_v4i16(<4 x i16> %A) {
+; CHECK-LABEL: vqabs_sat_v4i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.2d, #0000000000000000
+; CHECK-NEXT: cmgt v2.4h, v0.4h, #0
+; CHECK-NEXT: sqsub v1.4h, v1.4h, v0.4h
+; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b
+; CHECK-NEXT: ret
+entry:
+ %0 = icmp sgt <4 x i16> %A, zeroinitializer
+ %1 = tail call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> zeroinitializer, <4 x i16> %A)
+ %2 = select <4 x i1> %0, <4 x i16> %A, <4 x i16> %1
+ ret <4 x i16> %2
+}
+
+define <2 x i32> @vqabs_sat_v2i32(<2 x i32> %A) {
+; CHECK-LABEL: vqabs_sat_v2i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.2d, #0000000000000000
+; CHECK-NEXT: cmgt v2.2s, v0.2s, #0
+; CHECK-NEXT: sqsub v1.2s, v1.2s, v0.2s
+; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b
+; CHECK-NEXT: ret
+entry:
+ %0 = icmp sgt <2 x i32> %A, zeroinitializer
+ %1 = tail call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> zeroinitializer, <2 x i32> %A)
+ %2 = select <2 x i1> %0, <2 x i32> %A, <2 x i32> %1
+ ret <2 x i32> %2
+}
+
+define <1 x i64> @vqabs_sat_v1i64(<1 x i64> %A) {
+; CHECK-SD-LABEL: vqabs_sat_v1i64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v1.2d, #0000000000000000
+; CHECK-SD-NEXT: cmgt d2, d0, #0
+; CHECK-SD-NEXT: sqsub d1, d1, d0
+; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vqabs_sat_v1i64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fmov x9, d0
+; CHECK-GI-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000
+; CHECK-GI-NEXT: negs x9, x9
+; CHECK-GI-NEXT: cset w10, vs
+; CHECK-GI-NEXT: add x8, x8, x9, asr #63
+; CHECK-GI-NEXT: tst w10, #0x1
+; CHECK-GI-NEXT: fmov x10, d0
+; CHECK-GI-NEXT: csel x8, x8, x9, ne
+; CHECK-GI-NEXT: fmov d1, x8
+; CHECK-GI-NEXT: cmp x10, #0
+; CHECK-GI-NEXT: fcsel d0, d0, d1, gt
+; CHECK-GI-NEXT: ret
+entry:
+ %0 = icmp sgt <1 x i64> %A, zeroinitializer
+ %1 = tail call <1 x i64> @llvm.ssub.sat.v1i64(<1 x i64> zeroinitializer, <1 x i64> %A)
+ %2 = select <1 x i1> %0, <1 x i64> %A, <1 x i64> %1
+ ret <1 x i64> %2
+}
diff --git a/llvm/test/CodeGen/AArch64/vqneg.ll b/llvm/test/CodeGen/AArch64/vqneg.ll
new file mode 100644
index 0000000000000..7e91ea5a48289
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/vqneg.ll
@@ -0,0 +1,171 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=aarch64 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc -mtriple=aarch64 -global-isel %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+
+define <16 x i8> @vqneg_test16(<16 x i8> %A) nounwind {
+; CHECK-LABEL: vqneg_test16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.16b, #128
+; CHECK-NEXT: movi v2.16b, #127
+; CHECK-NEXT: cmeq v1.16b, v0.16b, v1.16b
+; CHECK-NEXT: neg v0.16b, v0.16b
+; CHECK-NEXT: bit v0.16b, v2.16b, v1.16b
+; CHECK-NEXT: ret
+entry:
+ %0 = icmp eq <16 x i8> %A, <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>
+ %1 = sub nsw <16 x i8> zeroinitializer, %A
+ %2 = select <16 x i1> %0, <16 x i8> <i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127>, <16 x i8> %1
+ ret <16 x i8> %2
+}
+
+define <8 x i16> @vqneg_test8(<8 x i16> %A) nounwind {
+; CHECK-SD-LABEL: vqneg_test8:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v1.8h, #128, lsl #8
+; CHECK-SD-NEXT: neg v2.8h, v0.8h
+; CHECK-SD-NEXT: cmeq v0.8h, v0.8h, v1.8h
+; CHECK-SD-NEXT: bic v1.16b, v2.16b, v0.16b
+; CHECK-SD-NEXT: bic v0.8h, #128, lsl #8
+; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vqneg_test8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v1.8h, #128, lsl #8
+; CHECK-GI-NEXT: mvni v2.8h, #128, lsl #8
+; CHECK-GI-NEXT: cmeq v1.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: neg v0.8h, v0.8h
+; CHECK-GI-NEXT: bit v0.16b, v2.16b, v1.16b
+; CHECK-GI-NEXT: ret
+entry:
+ %0 = icmp eq <8 x i16> %A, <i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768>
+ %1 = sub nsw <8 x i16> zeroinitializer, %A
+ %2 = select <8 x i1> %0, <8 x i16> <i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767>, <8 x i16> %1
+ ret <8 x i16> %2
+}
+
+define <4 x i32> @vqneg_test4(<4 x i32> %A) nounwind {
+; CHECK-SD-LABEL: vqneg_test4:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v1.4s, #128, lsl #24
+; CHECK-SD-NEXT: neg v2.4s, v0.4s
+; CHECK-SD-NEXT: cmeq v0.4s, v0.4s, v1.4s
+; CHECK-SD-NEXT: bic v1.16b, v2.16b, v0.16b
+; CHECK-SD-NEXT: bic v0.4s, #128, lsl #24
+; CHECK-SD-NEXT: orr v0.16b, v0.16b, v1.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vqneg_test4:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v1.4s, #128, lsl #24
+; CHECK-GI-NEXT: mvni v2.4s, #128, lsl #24
+; CHECK-GI-NEXT: cmeq v1.4s, v0.4s, v1.4s
+; CHECK-GI-NEXT: neg v0.4s, v0.4s
+; CHECK-GI-NEXT: bit v0.16b, v2.16b, v1.16b
+; CHECK-GI-NEXT: ret
+entry:
+ %0 = icmp eq <4 x i32> %A, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
+ %1 = sub nsw <4 x i32> zeroinitializer, %A
+ %2 = select <4 x i1> %0, <4 x i32> <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>, <4 x i32> %1
+ ret <4 x i32> %2
+}
+
+define <16 x i8> @vqneg_sat_v16i8(<16 x i8> %A) {
+; CHECK-LABEL: vqneg_sat_v16i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.2d, #0000000000000000
+; CHECK-NEXT: sqsub v0.16b, v1.16b, v0.16b
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> zeroinitializer, <16 x i8> %A)
+ ret <16 x i8> %0
+}
+
+define <8 x i16> @vqneg_sat_v8i16(<8 x i16> %A) {
+; CHECK-LABEL: vqneg_sat_v8i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.2d, #0000000000000000
+; CHECK-NEXT: sqsub v0.8h, v1.8h, v0.8h
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> zeroinitializer, <8 x i16> %A)
+ ret <8 x i16> %0
+}
+
+define <4 x i32> @vqneg_sat_v4i32(<4 x i32> %A) {
+; CHECK-LABEL: vqneg_sat_v4i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.2d, #0000000000000000
+; CHECK-NEXT: sqsub v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> zeroinitializer, <4 x i32> %A)
+ ret <4 x i32> %0
+}
+
+define <2 x i64> @vqneg_sat_v2i64(<2 x i64> %A) {
+; CHECK-LABEL: vqneg_sat_v2i64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.2d, #0000000000000000
+; CHECK-NEXT: sqsub v0.2d, v1.2d, v0.2d
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> zeroinitializer, <2 x i64> %A)
+ ret <2 x i64> %0
+}
+
+define <8 x i8> @vqneg_sat_v8i8(<8 x i8> %A) {
+; CHECK-LABEL: vqneg_sat_v8i8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.2d, #0000000000000000
+; CHECK-NEXT: sqsub v0.8b, v1.8b, v0.8b
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call <8 x i8> @llvm.ssub.sat.v8i8(<8 x i8> zeroinitializer, <8 x i8> %A)
+ ret <8 x i8> %0
+}
+
+define <4 x i16> @vqneg_sat_v4i16(<4 x i16> %A) {
+; CHECK-LABEL: vqneg_sat_v4i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.2d, #0000000000000000
+; CHECK-NEXT: sqsub v0.4h, v1.4h, v0.4h
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> zeroinitializer, <4 x i16> %A)
+ ret <4 x i16> %0
+}
+
+define <2 x i32> @vqneg_sat_v2i32(<2 x i32> %A) {
+; CHECK-LABEL: vqneg_sat_v2i32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v1.2d, #0000000000000000
+; CHECK-NEXT: sqsub v0.2s, v1.2s, v0.2s
+; CHECK-NEXT: ret
+entry:
+ %0 = tail call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> zeroinitializer, <2 x i32> %A)
+ ret <2 x i32> %0
+}
+
+define <1 x i64> @vqneg_sat_v1i64(<1 x i64> %A) {
+; CHECK-SD-LABEL: vqneg_sat_v1i64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v1.2d, #0000000000000000
+; CHECK-SD-NEXT: sqsub d0, d1, d0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: vqneg_sat_v1i64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fmov x9, d0
+; CHECK-GI-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000
+; CHECK-GI-NEXT: negs x9, x9
+; CHECK-GI-NEXT: cset w10, vs
+; CHECK-GI-NEXT: add x8, x8, x9, asr #63
+; CHECK-GI-NEXT: tst w10, #0x1
+; CHECK-GI-NEXT: csel x8, x8, x9, ne
+; CHECK-GI-NEXT: fmov d0, x8
+; CHECK-GI-NEXT: ret
+entry:
+ %0 = tail call <1 x i64> @llvm.ssub.sat.v1i64(<1 x i64> zeroinitializer, <1 x i64> %A)
+ ret <1 x i64> %0
+}
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