[llvm] [AMDGPU] Optimize fsub and fneg when packed fp32 ops are supported (PR #195962)

[Matt Arsenault via llvm-commits]

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@@ -872,7 +872,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
     if (Subtarget->hasPackedFP32Ops()) {
       setOperationAction({ISD::FADD, ISD::FMUL, ISD::FMA, ISD::FNEG},
                          MVT::v2f32, Legal);
-      setOperationAction({ISD::FADD, ISD::FMUL, ISD::FMA},
+      setOperationAction({ISD::FADD, ISD::FMUL, ISD::FMA, ISD::FNEG},
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arsenm wrote:

Yes. If you can't directly handle this for VALU it's a bit trickier 

https://github.com/llvm/llvm-project/pull/195962