[llvm] [LoadStoreVectorizer] Support vectorization of mixed-type contiguous accesses (PR #177908)

[Anshil Gandhi via llvm-commits]

gandhi56 wrote:

> I implemented a patch to use the bN if N >= 8, iN otherwise. I was able to update all AMDGPU, NVPTX and X86 tests but one. AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll fails because the gMIR instruction `%_(p1) = G_BITCAST %_(s64)` is identified as illegal, even though it is correct as p1 is 64 bits wide. I will create a separate patch for it.

https://github.com/llvm/llvm-project/pull/196125

https://github.com/llvm/llvm-project/pull/177908