[llvm] [GlobalISel] Lower ptr/int bitcasts to INTTOPTR/PTRTOINT in IRTranslator (PR #196125)
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Wed May 6 10:23:15 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-globalisel
Author: Anshil Gandhi (gandhi56)
<details>
<summary>Changes</summary>
MachineVerifier rejects G_BITCAST between pointer and non-pointer LLTs.
translateBitCast now emits G_INTTOPTR / G_PTRTOINT when LLVM IR bitcast
crosses that boundary (e.g. b64 <-> ptr), matching inttoptr/ptrtoint
semantics. Same-total-size asserts guard the lowering.
Add AMDGPU irtranslator tests (b64->p1, p1->b64, v2i16->i32).
Co-authored-by: Cursor
---
Full diff: https://github.com/llvm/llvm-project/pull/196125.diff
2 Files Affected:
- (modified) llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp (+12-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll (+62)
``````````diff
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 7db3e2d4e02b7..bdd27b7fc7a56 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -1583,9 +1583,11 @@ bool IRTranslator::translateCopy(const User &U, const Value &V,
bool IRTranslator::translateBitCast(const User &U,
MachineIRBuilder &MIRBuilder) {
+ Type *SrcTy = U.getOperand(0)->getType();
+ Type *DstTy = U.getType();
+
// If we're bitcasting to the source type, we can reuse the source vreg.
- if (getLLTForType(*U.getOperand(0)->getType(), *DL) ==
- getLLTForType(*U.getType(), *DL)) {
+ if (getLLTForType(*SrcTy, *DL) == getLLTForType(*DstTy, *DL)) {
// If the source is a ConstantInt then it was probably created by
// ConstantHoisting and we should leave it alone.
if (isa<ConstantInt>(U.getOperand(0)))
@@ -1594,6 +1596,14 @@ bool IRTranslator::translateBitCast(const User &U,
return translateCopy(U, *U.getOperand(0), MIRBuilder);
}
+ // MachineVerifier only allows G_BITCAST when both operands are pointers or
+ // both are non-pointers. Integer / byte / FP to pointer (and the inverse)
+ // must use G_INTTOPTR / G_PTRTOINT (same as the IR inttoptr/ptrtoint ops).
+ if (DstTy->isPtrOrPtrVectorTy() && !SrcTy->isPtrOrPtrVectorTy())
+ return translateCast(TargetOpcode::G_INTTOPTR, U, MIRBuilder);
+ if (SrcTy->isPtrOrPtrVectorTy() && !DstTy->isPtrOrPtrVectorTy())
+ return translateCast(TargetOpcode::G_PTRTOINT, U, MIRBuilder);
+
return translateCast(TargetOpcode::G_BITCAST, U, MIRBuilder);
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll
index fc236147f1238..2d0d0b1537adc 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll
@@ -20,3 +20,65 @@ define void @addi32(i32 %arg1, i32 %arg2) {
store i32 %res, ptr addrspace(1) poison
ret void
}
+
+; Bitcast from b64 (as produced e.g. by load/store vectorization) to a flat ptr
+; must become G_INTTOPTR, not G_BITCAST, so -verify-machineinstrs accepts gMIR
+; (see llvm.amdgcn.mfma.gfx90a.ll after IRTranslator). This IR exercises
+; IRTranslator::translateBitCast's non-pointer-to-pointer branch (assert-guarded).
+define void @bitcast_b64_to_p1(ptr addrspace(4) %kernarg_pack) {
+ ; CHECK-LABEL: name: bitcast_b64_to_p1
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK-NEXT: liveins: $vgpr0, $vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<3 x s64>) = G_LOAD [[MV]](p4) :: (load (<3 x s64>) from %ir.kernarg_pack, align 8, addrspace 4)
+ ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[LOAD]](<3 x s64>), [[C]](s32)
+ ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[EVEC]](s64)
+ ; CHECK-NEXT: G_STORE [[C1]](s64), [[INTTOPTR]](p1) :: (store (s64) into %ir.ptr, addrspace 1)
+ ; CHECK-NEXT: SI_RETURN
+ %pack = load <3 x b64>, ptr addrspace(4) %kernarg_pack, align 8
+ %bits = extractelement <3 x b64> %pack, i32 0
+ %ptr = bitcast b64 %bits to ptr addrspace(1)
+ store i64 0, ptr addrspace(1) %ptr
+ ret void
+}
+
+; Pointer to byte: IRTranslator::translateBitCast uses G_PTRTOINT (assert-guarded
+; equal total sizes).
+define void @bitcast_p1_to_b64(ptr addrspace(1) %p) {
+ ; CHECK-LABEL: name: bitcast_p1_to_b64
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK-NEXT: liveins: $vgpr0, $vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; CHECK-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[MV]](p1)
+ ; CHECK-NEXT: G_STORE [[PTRTOINT]](s64), [[DEF]](p0) :: (store (s64) into `ptr poison`)
+ ; CHECK-NEXT: SI_RETURN
+ %b = bitcast ptr addrspace(1) %p to b64
+ store b64 %b, ptr poison
+ ret void
+}
+
+; Non-pointer to non-pointer (different LLTs): must lower to G_BITCAST, not
+; G_INTTOPTR/G_PTRTOINT (final assert in translateBitCast).
+define void @bitcast_v2i16_to_i32(<2 x i16> %v) {
+ ; CHECK-LABEL: name: bitcast_v2i16_to_i32
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK-NEXT: liveins: $vgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
+ ; CHECK-NEXT: G_STORE [[BITCAST]](s32), [[DEF]](p1) :: (store (s32) into `ptr addrspace(1) poison`, addrspace 1)
+ ; CHECK-NEXT: SI_RETURN
+ %i = bitcast <2 x i16> %v to i32
+ store i32 %i, ptr addrspace(1) poison
+ ret void
+}
``````````
</details>
https://github.com/llvm/llvm-project/pull/196125
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