[llvm] [RegAllocFast] Eliminate copies with dead defs (PR #196056)
via llvm-commits
llvm-commits at lists.llvm.org
Wed May 6 05:35:39 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-x86
Author: mkovacevic99
<details>
<summary>Changes</summary>
github issue: https://github.com/llvm/llvm-project/issues/168201
This patch extends copy elimination in **RegAllocFast** to catch an additional class of redundant copies. Previously, only identity copies (where source and destination registers are the same) were marked for removal.
Now, we track whether the current instruction defines a new register (**HasMIDefinedNewReg**). Using this, we also identify and remove copies where the destination operand is marked dead and the instruction defines a new register—i.e., cases where the copy has no observable effect.
The change:
- Introduces HasMIDefinedNewReg to detect when the instruction defines a register.
- Updates the copy-elimination condition to include dead destination operands when a new register is defined.
- Improves debug output to distinguish between identity copies and dead copies.
This reduces unnecessary instructions and can lead to slightly better codegen by eliminating no-op copies earlier in the fast register allocation pass.
---
Patch is 509.92 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/196056.diff
41 Files Affected:
- (modified) llvm/lib/CodeGen/RegAllocFast.cpp (+12-2)
- (modified) llvm/test/CodeGen/AArch64/fast-isel-atomic-fallback.ll (-1)
- (modified) llvm/test/CodeGen/AArch64/swifterror.ll (-5)
- (modified) llvm/test/CodeGen/AMDGPU/div_i128.ll (-18)
- (modified) llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll (+64-80)
- (modified) llvm/test/CodeGen/AMDGPU/fix-crash-valu-hazard.ll (-1)
- (modified) llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll (-1)
- (modified) llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll (+109-125)
- (modified) llvm/test/CodeGen/AMDGPU/memory-legalizer-buffer-atomics.ll (-18)
- (modified) llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll (-100)
- (modified) llvm/test/CodeGen/AMDGPU/memory-legalizer-local-cluster.ll (-100)
- (modified) llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll (-5)
- (modified) llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll (-100)
- (modified) llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll (-100)
- (modified) llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll (-7)
- (modified) llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll (-100)
- (modified) llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll (-100)
- (modified) llvm/test/CodeGen/AMDGPU/rem_i128.ll (-1)
- (modified) llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll (-3)
- (modified) llvm/test/CodeGen/AMDGPU/wwm-reserved.ll (-2)
- (modified) llvm/test/CodeGen/ARM/legalize-bitcast.ll (-2)
- (modified) llvm/test/CodeGen/LoongArch/spill-ra-without-kill.ll (-1)
- (modified) llvm/test/CodeGen/Mips/atomic-min-max.ll (-80)
- (modified) llvm/test/CodeGen/Mips/atomic.ll (-12)
- (modified) llvm/test/CodeGen/Mips/implicit-sret.ll (-2)
- (modified) llvm/test/CodeGen/PowerPC/aix-p9-insert-extract.ll (-24)
- (modified) llvm/test/CodeGen/PowerPC/aix-small-local-dynamic-tls-types.ll (-2)
- (modified) llvm/test/CodeGen/PowerPC/aix-tls-le-ldst-O0.ll (-6)
- (modified) llvm/test/CodeGen/PowerPC/ppcsoftops.ll (-6)
- (modified) llvm/test/CodeGen/RISCV/constpool-known-bits.ll (-2)
- (modified) llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll (+12-14)
- (modified) llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll (+12-14)
- (modified) llvm/test/CodeGen/RISCV/xcvalu.ll (-4)
- (modified) llvm/test/CodeGen/X86/AMX/amx-configO0toO0.ll (-2)
- (modified) llvm/test/CodeGen/X86/avx512-mask-zext-bugfix.ll (+1-3)
- (modified) llvm/test/CodeGen/X86/avxneconvert-intrinsics-shared.ll (-2)
- (modified) llvm/test/CodeGen/X86/bug47278.mir (-3)
- (modified) llvm/test/CodeGen/X86/huge-stack.ll (-1)
- (modified) llvm/test/CodeGen/X86/pcsections-atomics.ll (+625-725)
- (modified) llvm/test/CodeGen/X86/pr32451.ll (-1)
- (modified) llvm/test/CodeGen/X86/pr41678.ll (-1)
``````````diff
diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp
index 7998b87a59c96..0ff8048167cc9 100644
--- a/llvm/lib/CodeGen/RegAllocFast.cpp
+++ b/llvm/lib/CodeGen/RegAllocFast.cpp
@@ -1484,6 +1484,7 @@ void RegAllocFastImpl::allocateInstruction(MachineInstr &MI) {
RegMasks.clear();
BundleVirtRegsMap.clear();
+ bool HasMIDefinedNewReg = false;
// Scan for special cases; Apply pre-assigned register defs to state.
bool HasPhysRegUse = false;
bool HasRegMask = false;
@@ -1512,6 +1513,7 @@ void RegAllocFastImpl::allocateInstruction(MachineInstr &MI) {
if (MO.isDef()) {
HasDef = true;
bool displacedAny = definePhysReg(MI, Reg);
+ HasMIDefinedNewReg = true;
if (MO.isEarlyClobber())
HasEarlyClobber = true;
if (!displacedAny)
@@ -1554,6 +1556,7 @@ void RegAllocFastImpl::allocateInstruction(MachineInstr &MI) {
} else {
ReArrangedImplicitOps = defineVirtReg(MI, OpIdx, Reg);
}
+ HasMIDefinedNewReg = true;
// Implicit operands of MI were re-arranged,
// re-compute DefOperandIndexes.
if (ReArrangedImplicitOps)
@@ -1569,6 +1572,7 @@ void RegAllocFastImpl::allocateInstruction(MachineInstr &MI) {
if (Reg.isVirtual()) {
ReArrangedImplicitOps =
defineVirtReg(MI, MI.getOperandNo(&MO), Reg);
+ HasMIDefinedNewReg = true;
if (ReArrangedImplicitOps)
break;
}
@@ -1715,9 +1719,15 @@ void RegAllocFastImpl::allocateInstruction(MachineInstr &MI) {
}
LLVM_DEBUG(dbgs() << "<< " << MI);
- if (MI.isCopy() && MI.getOperand(0).getReg() == MI.getOperand(1).getReg() &&
+ if (MI.isCopy() &&
+ (MI.getOperand(0).getReg() == MI.getOperand(1).getReg() ||
+ (MI.getOperand(0).isDead() && HasMIDefinedNewReg)) &&
MI.getNumOperands() == 2) {
- LLVM_DEBUG(dbgs() << "Mark identity copy for removal\n");
+ if (MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
+ LLVM_DEBUG(dbgs() << "Mark identity copy for removal\n");
+ } else {
+ LLVM_DEBUG(dbgs() << "Mark dead copy for removal\n");
+ }
Coalesced.push_back(&MI);
}
}
diff --git a/llvm/test/CodeGen/AArch64/fast-isel-atomic-fallback.ll b/llvm/test/CodeGen/AArch64/fast-isel-atomic-fallback.ll
index 16ef0cbc8a810..c0b79af962228 100644
--- a/llvm/test/CodeGen/AArch64/fast-isel-atomic-fallback.ll
+++ b/llvm/test/CodeGen/AArch64/fast-isel-atomic-fallback.ll
@@ -36,7 +36,6 @@ define i32 @cmpxchg_cstexpr_addr(i32 %cmp, i32 %new, ptr %ps) #0 {
; CHECK-NEXT: LBB1_3:
; CHECK-NEXT: subs w8, w0, w8
; CHECK-NEXT: cset w8, eq
-; CHECK-NEXT: ; kill: def $w1 killed $w8
; CHECK-NEXT: str w8, [x2]
; CHECK-NEXT: ret
%tmp0 = cmpxchg ptr inttoptr (i32 ptrtoint (ptr @g to i32) to ptr), i32 %cmp, i32 %new seq_cst seq_cst
diff --git a/llvm/test/CodeGen/AArch64/swifterror.ll b/llvm/test/CodeGen/AArch64/swifterror.ll
index 867e89748d86d..1ef88cfc16069 100644
--- a/llvm/test/CodeGen/AArch64/swifterror.ll
+++ b/llvm/test/CodeGen/AArch64/swifterror.ll
@@ -183,7 +183,6 @@ define float @caller(ptr %error_ref) {
; CHECK-O0-ARM64_32-NEXT: ldr x9, [sp, #8] ; 8-byte Reload
; CHECK-O0-ARM64_32-NEXT: ldr x8, [sp, #16] ; 8-byte Reload
; CHECK-O0-ARM64_32-NEXT: ldrb w8, [x8, #8]
-; CHECK-O0-ARM64_32-NEXT: ; kill: def $w0 killed $w8
; CHECK-O0-ARM64_32-NEXT: strb w8, [x9]
; CHECK-O0-ARM64_32-NEXT: LBB1_2: ; %handler
; CHECK-O0-ARM64_32-NEXT: ldr x0, [sp, #16] ; 8-byte Reload
@@ -368,7 +367,6 @@ define float @caller2(ptr %error_ref) {
; CHECK-O0-ARM64_32-NEXT: ldr x9, [sp, #16] ; 8-byte Reload
; CHECK-O0-ARM64_32-NEXT: ldr x8, [sp, #8] ; 8-byte Reload
; CHECK-O0-ARM64_32-NEXT: ldrb w8, [x8, #8]
-; CHECK-O0-ARM64_32-NEXT: ; kill: def $w0 killed $w8
; CHECK-O0-ARM64_32-NEXT: strb w8, [x9]
; CHECK-O0-ARM64_32-NEXT: LBB2_4: ; %handler
; CHECK-O0-ARM64_32-NEXT: ldr x0, [sp, #8] ; 8-byte Reload
@@ -606,7 +604,6 @@ define float @foo_loop(ptr swifterror %error_ptr_ref, i32 %cc, float %cc2) {
; CHECK-O0-ARM64_32-NEXT: mov w0, w8
; CHECK-O0-ARM64_32-NEXT: bl _malloc
; CHECK-O0-ARM64_32-NEXT: mov x9, x0
-; CHECK-O0-ARM64_32-NEXT: ; kill: def $x0 killed $x9
; CHECK-O0-ARM64_32-NEXT: mov x0, x9
; CHECK-O0-ARM64_32-NEXT: mov w8, #1 ; =0x1
; CHECK-O0-ARM64_32-NEXT: strb w8, [x9, #8]
@@ -863,7 +860,6 @@ define float @caller3(ptr %error_ref) {
; CHECK-O0-ARM64_32-NEXT: ldr x9, [sp] ; 8-byte Reload
; CHECK-O0-ARM64_32-NEXT: ldr x8, [sp, #8] ; 8-byte Reload
; CHECK-O0-ARM64_32-NEXT: ldrb w8, [x8, #8]
-; CHECK-O0-ARM64_32-NEXT: ; kill: def $w0 killed $w8
; CHECK-O0-ARM64_32-NEXT: strb w8, [x9]
; CHECK-O0-ARM64_32-NEXT: LBB6_2: ; %handler
; CHECK-O0-ARM64_32-NEXT: ldr x0, [sp, #8] ; 8-byte Reload
@@ -1223,7 +1219,6 @@ define float @caller4(ptr %error_ref) {
; CHECK-O0-ARM64_32-NEXT: ldr x9, [sp, #16] ; 8-byte Reload
; CHECK-O0-ARM64_32-NEXT: ldr x8, [sp, #24] ; 8-byte Reload
; CHECK-O0-ARM64_32-NEXT: ldrb w8, [x8, #8]
-; CHECK-O0-ARM64_32-NEXT: ; kill: def $w0 killed $w8
; CHECK-O0-ARM64_32-NEXT: strb w8, [x9]
; CHECK-O0-ARM64_32-NEXT: LBB8_2: ; %handler
; CHECK-O0-ARM64_32-NEXT: ldr x0, [sp, #24] ; 8-byte Reload
diff --git a/llvm/test/CodeGen/AMDGPU/div_i128.ll b/llvm/test/CodeGen/AMDGPU/div_i128.ll
index 581f7a2b83ceb..cabe0000bddc6 100644
--- a/llvm/test/CodeGen/AMDGPU/div_i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/div_i128.ll
@@ -1415,29 +1415,23 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: v_mov_b32_e32 v15, v7
; GFX9-G-O0-NEXT: s_mov_b64 s[4:5], 0
; GFX9-G-O0-NEXT: s_mov_b64 s[8:9], 0x7f
-; GFX9-G-O0-NEXT: ; kill: def $vgpr0_vgpr1 killed $vgpr3_vgpr4 killed $exec
; GFX9-G-O0-NEXT: s_waitcnt vmcnt(0)
; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v5
; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v6
-; GFX9-G-O0-NEXT: ; kill: def $vgpr2 killed $vgpr0 killed $exec
; GFX9-G-O0-NEXT: v_mov_b32_e32 v7, v1
; GFX9-G-O0-NEXT: s_mov_b32 s6, 31
; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, s6
; GFX9-G-O0-NEXT: v_ashrrev_i32_e64 v11, v2, v7
-; GFX9-G-O0-NEXT: ; kill: def $vgpr2 killed $vgpr0 killed $exec
; GFX9-G-O0-NEXT: ; kill: def $vgpr1 killed $vgpr1 killed $vgpr0_vgpr1 killed $exec
; GFX9-G-O0-NEXT: s_mov_b32 s6, 31
; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s6
; GFX9-G-O0-NEXT: v_ashrrev_i32_e64 v9, v0, v1
-; GFX9-G-O0-NEXT: ; kill: def $vgpr0_vgpr1 killed $vgpr12_vgpr13 killed $exec
; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v14
; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v15
-; GFX9-G-O0-NEXT: ; kill: def $vgpr2 killed $vgpr0 killed $exec
; GFX9-G-O0-NEXT: v_mov_b32_e32 v7, v1
; GFX9-G-O0-NEXT: s_mov_b32 s6, 31
; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, s6
; GFX9-G-O0-NEXT: v_ashrrev_i32_e64 v10, v2, v7
-; GFX9-G-O0-NEXT: ; kill: def $vgpr2 killed $vgpr0 killed $exec
; GFX9-G-O0-NEXT: ; kill: def $vgpr1 killed $vgpr1 killed $vgpr0_vgpr1 killed $exec
; GFX9-G-O0-NEXT: s_mov_b32 s6, 31
; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s6
@@ -1712,7 +1706,6 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: v_lshlrev_b64 v[9:10], v0, v[2:3]
; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s4
; GFX9-G-O0-NEXT: v_lshlrev_b64 v[0:1], v0, v[4:5]
-; GFX9-G-O0-NEXT: ; kill: def $vgpr4 killed $vgpr2 killed $exec
; GFX9-G-O0-NEXT: ; kill: def $vgpr3 killed $vgpr3 killed $vgpr2_vgpr3 killed $exec
; GFX9-G-O0-NEXT: s_mov_b32 s4, 31
; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, s4
@@ -1820,7 +1813,6 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: v_lshlrev_b64 v[2:3], v2, v[0:1]
; GFX9-G-O0-NEXT: v_mov_b32_e32 v4, s8
; GFX9-G-O0-NEXT: v_lshlrev_b64 v[4:5], v4, v[14:15]
-; GFX9-G-O0-NEXT: ; kill: def $vgpr7 killed $vgpr0 killed $exec
; GFX9-G-O0-NEXT: ; kill: def $vgpr1 killed $vgpr1 killed $vgpr0_vgpr1 killed $exec
; GFX9-G-O0-NEXT: s_mov_b32 s9, 31
; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s9
@@ -1828,10 +1820,8 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v4
; GFX9-G-O0-NEXT: ; kill: def $vgpr5 killed $vgpr5 killed $vgpr4_vgpr5 killed $exec
; GFX9-G-O0-NEXT: v_or_b32_e64 v7, v0, v1
-; GFX9-G-O0-NEXT: ; kill: def $vgpr0_vgpr1 killed $vgpr22_vgpr23 killed $exec
; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v24
; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v25
-; GFX9-G-O0-NEXT: ; kill: def $vgpr4 killed $vgpr0 killed $exec
; GFX9-G-O0-NEXT: ; kill: def $vgpr1 killed $vgpr1 killed $vgpr0_vgpr1 killed $exec
; GFX9-G-O0-NEXT: s_mov_b32 s9, 31
; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s9
@@ -1847,7 +1837,6 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: v_lshlrev_b64 v[25:26], v0, v[2:3]
; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s8
; GFX9-G-O0-NEXT: v_lshlrev_b64 v[0:1], v0, v[14:15]
-; GFX9-G-O0-NEXT: ; kill: def $vgpr14 killed $vgpr2 killed $exec
; GFX9-G-O0-NEXT: ; kill: def $vgpr3 killed $vgpr3 killed $vgpr2_vgpr3 killed $exec
; GFX9-G-O0-NEXT: s_mov_b32 s8, 31
; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, s8
@@ -3771,7 +3760,6 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: v_lshlrev_b64 v[9:10], v0, v[2:3]
; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s4
; GFX9-G-O0-NEXT: v_lshlrev_b64 v[0:1], v0, v[4:5]
-; GFX9-G-O0-NEXT: ; kill: def $vgpr4 killed $vgpr2 killed $exec
; GFX9-G-O0-NEXT: ; kill: def $vgpr3 killed $vgpr3 killed $vgpr2_vgpr3 killed $exec
; GFX9-G-O0-NEXT: s_mov_b32 s4, 31
; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, s4
@@ -3879,7 +3867,6 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: v_lshlrev_b64 v[2:3], v2, v[0:1]
; GFX9-G-O0-NEXT: v_mov_b32_e32 v4, s8
; GFX9-G-O0-NEXT: v_lshlrev_b64 v[4:5], v4, v[20:21]
-; GFX9-G-O0-NEXT: ; kill: def $vgpr7 killed $vgpr0 killed $exec
; GFX9-G-O0-NEXT: ; kill: def $vgpr1 killed $vgpr1 killed $vgpr0_vgpr1 killed $exec
; GFX9-G-O0-NEXT: s_mov_b32 s9, 31
; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s9
@@ -3887,10 +3874,8 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v4
; GFX9-G-O0-NEXT: ; kill: def $vgpr5 killed $vgpr5 killed $vgpr4_vgpr5 killed $exec
; GFX9-G-O0-NEXT: v_or_b32_e64 v7, v0, v1
-; GFX9-G-O0-NEXT: ; kill: def $vgpr0_vgpr1 killed $vgpr12_vgpr13 killed $exec
; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v14
; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v15
-; GFX9-G-O0-NEXT: ; kill: def $vgpr4 killed $vgpr0 killed $exec
; GFX9-G-O0-NEXT: ; kill: def $vgpr1 killed $vgpr1 killed $vgpr0_vgpr1 killed $exec
; GFX9-G-O0-NEXT: s_mov_b32 s9, 31
; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s9
@@ -3906,7 +3891,6 @@ define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
; GFX9-G-O0-NEXT: v_lshlrev_b64 v[22:23], v0, v[2:3]
; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s8
; GFX9-G-O0-NEXT: v_lshlrev_b64 v[0:1], v0, v[12:13]
-; GFX9-G-O0-NEXT: ; kill: def $vgpr12 killed $vgpr2 killed $exec
; GFX9-G-O0-NEXT: ; kill: def $vgpr3 killed $vgpr3 killed $vgpr2_vgpr3 killed $exec
; GFX9-G-O0-NEXT: s_mov_b32 s8, 31
; GFX9-G-O0-NEXT: v_mov_b32_e32 v2, s8
@@ -4423,10 +4407,8 @@ define i128 @v_sdiv_i128_v_pow2k(i128 %lhs) {
; GFX9-G-O0-NEXT: v_mov_b32_e32 v9, v1
; GFX9-G-O0-NEXT: v_mov_b32_e32 v10, v2
; GFX9-G-O0-NEXT: v_mov_b32_e32 v11, v3
-; GFX9-G-O0-NEXT: ; kill: def $vgpr0_vgpr1 killed $vgpr8_vgpr9 killed $exec
; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, v10
; GFX9-G-O0-NEXT: v_mov_b32_e32 v1, v11
-; GFX9-G-O0-NEXT: ; kill: def $vgpr2 killed $vgpr0 killed $exec
; GFX9-G-O0-NEXT: ; kill: def $vgpr1 killed $vgpr1 killed $vgpr0_vgpr1 killed $exec
; GFX9-G-O0-NEXT: s_mov_b32 s4, 31
; GFX9-G-O0-NEXT: v_mov_b32_e32 v0, s4
diff --git a/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll b/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
index bf84e32de657b..e2fad14e84666 100644
--- a/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
+++ b/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
@@ -3680,7 +3680,6 @@ define i32 @extract_dyn_i32_3(<3 x i32> inreg %arg, i32 %idx) {
; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6
; GCN-O0-NEXT: s_mov_b32 s5, s17
; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: ; kill: def $sgpr8_sgpr9_sgpr10 killed $sgpr4_sgpr5_sgpr6
; GCN-O0-NEXT: v_mov_b32_e32 v0, s4
; GCN-O0-NEXT: v_mov_b32_e32 v1, s5
; GCN-O0-NEXT: v_mov_b32_e32 v2, s6
@@ -3691,15 +3690,15 @@ define i32 @extract_dyn_i32_3(<3 x i32> inreg %arg, i32 %idx) {
; GCN-O0-NEXT: ; implicit-def: $vgpr5 : SGPR spill to VGPR lane
; GCN-O0-NEXT: v_writelane_b32 v5, s4, 0
; GCN-O0-NEXT: v_writelane_b32 v5, s5, 1
-; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
; GCN-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b64 exec, s[14:15]
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: ; implicit-def: $vgpr0
; GCN-O0-NEXT: ; implicit-def: $sgpr4_sgpr5
; GCN-O0-NEXT: .LBB22_1: ; =>This Inner Loop Header: Depth=1
-; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
; GCN-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 ; 4-byte Folded Reload
-; GCN-O0-NEXT: s_mov_b64 exec, s[14:15]
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
; GCN-O0-NEXT: v_readlane_b32 s4, v5, 2
; GCN-O0-NEXT: v_readlane_b32 s5, v5, 3
@@ -3719,15 +3718,15 @@ define i32 @extract_dyn_i32_3(<3 x i32> inreg %arg, i32 %idx) {
; GCN-O0-NEXT: s_mov_b64 s[6:7], s[4:5]
; GCN-O0-NEXT: v_writelane_b32 v5, s6, 2
; GCN-O0-NEXT: v_writelane_b32 v5, s7, 3
-; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
; GCN-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b64 exec, s[14:15]
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_xor_b64 exec, exec, s[4:5]
; GCN-O0-NEXT: s_cbranch_execnz .LBB22_1
; GCN-O0-NEXT: ; %bb.2:
-; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
; GCN-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 ; 4-byte Folded Reload
-; GCN-O0-NEXT: s_mov_b64 exec, s[14:15]
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
; GCN-O0-NEXT: v_readlane_b32 s4, v5, 0
; GCN-O0-NEXT: v_readlane_b32 s5, v5, 1
@@ -3761,7 +3760,6 @@ define i32 @extract_dyn_inreg_i32_3(<3 x i32> inreg %arg, i32 inreg %idx) {
; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6
; GCN-O0-NEXT: s_mov_b32 s5, s17
; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: ; kill: def $sgpr8_sgpr9_sgpr10 killed $sgpr4_sgpr5_sgpr6
; GCN-O0-NEXT: v_mov_b32_e32 v0, s4
; GCN-O0-NEXT: v_mov_b32_e32 v1, s5
; GCN-O0-NEXT: v_mov_b32_e32 v2, s6
@@ -3796,7 +3794,6 @@ define float @extract_dyn_float_3(<3 x float> inreg %arg, i32 %idx) {
; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6
; GCN-O0-NEXT: s_mov_b32 s5, s17
; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: ; kill: def $sgpr8_sgpr9_sgpr10 killed $sgpr4_sgpr5_sgpr6
; GCN-O0-NEXT: v_mov_b32_e32 v0, s4
; GCN-O0-NEXT: v_mov_b32_e32 v1, s5
; GCN-O0-NEXT: v_mov_b32_e32 v2, s6
@@ -3807,15 +3804,15 @@ define float @extract_dyn_float_3(<3 x float> inreg %arg, i32 %idx) {
; GCN-O0-NEXT: ; implicit-def: $vgpr5 : SGPR spill to VGPR lane
; GCN-O0-NEXT: v_writelane_b32 v5, s4, 0
; GCN-O0-NEXT: v_writelane_b32 v5, s5, 1
-; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
; GCN-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b64 exec, s[14:15]
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: ; implicit-def: $vgpr0
; GCN-O0-NEXT: ; implicit-def: $sgpr4_sgpr5
; GCN-O0-NEXT: .LBB24_1: ; =>This Inner Loop Header: Depth=1
-; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
; GCN-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 ; 4-byte Folded Reload
-; GCN-O0-NEXT: s_mov_b64 exec, s[14:15]
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
; GCN-O0-NEXT: v_readlane_b32 s4, v5, 2
; GCN-O0-NEXT: v_readlane_b32 s5, v5, 3
@@ -3835,15 +3832,15 @@ define float @extract_dyn_float_3(<3 x float> inreg %arg, i32 %idx) {
; GCN-O0-NEXT: s_mov_b64 s[6:7], s[4:5]
; GCN-O0-NEXT: v_writelane_b32 v5, s6, 2
; GCN-O0-NEXT: v_writelane_b32 v5, s7, 3
-; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
; GCN-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b64 exec, s[14:15]
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_xor_b64 exec, exec, s[4:5]
; GCN-O0-NEXT: s_cbranch_execnz .LBB24_1
; GCN-O0-NEXT: ; %bb.2:
-; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
; GCN-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 ; 4-byte Folded Reload
-; GCN-O0-NEXT: s_mov_b64 exec, s[14:15]
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
; GCN-O0-NEXT: v_readlane_b32 s4, v5, 0
; GCN-O0-NEXT: v_readlane_b32 s5, v5, 1
@@ -3881,7 +3878,6 @@ define float @extract_dyn_inreg_float_3(<3 x float> inreg %arg, i32 inreg %idx)
; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6
; GCN-O0-NEXT: s_mov_b32 s5, s17
; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: ; kill: def $sgpr8_sgpr9_sgpr10 killed $sgpr4_sgpr5_sgpr6
; GCN-O0-NEXT: v_mov_b32_e32 v0, s4
; GCN-O0-NEXT: v_mov_b32_e32 v1, s5
; GCN-O0-NEXT: v_mov_b32_e32 v2, s6
@@ -3924,7 +3920,6 @@ define i32 @extract_dyn_i32_5(<5 x i32> inreg %arg, i32 %idx) {
; GCN-O0-NEXT: s_mov_b32 s6, s18
; GCN-O0-NEXT: s_mov_b32 s7, s19
; GCN-O0-NEXT: s_mov_b32 s8, s20
-; GCN-O0-NEXT: ; kill: def $sgpr12_sgpr13_sgpr14_sgpr15_sgpr16 killed $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8
; GCN-O0-NEXT: v_mov_b32_e32 v0, s4
; GCN-O0-NEXT: v_mov_b32_e32 v1, s5
; GCN-O0-NEXT: v_mov_b32_e32 v2, s6
@@ -3939,15 +3934,15 @@ define i32 @extract_dyn_i32_5(<5 x i32> inreg %arg, i32 %idx) {
; GCN-O0-NEXT: ; implicit-def: $vgpr7 : SGPR spill to VGPR lane
; GCN-O0-NEXT: v_writelane_b32 v7, s4, 0
; GCN-O0-NEXT: v_writelane_b32 v7, s5, 1
-; GCN-O0-NEXT: s_or_saveexec_b64 s[22:23], -1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
; GCN-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b64 exec, s[22:23]
+; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
; GCN-O0-NEXT: ; implicit-def: $vgpr0
; GCN-O0-NEXT: ; implicit-def: $sgpr4_sgpr5
; GCN-O0-NEXT: .LBB26_1: ; =>This Inner Loop Header: Depth=1
-; GCN-O0-NEXT: s_or_saveexec_b64 s[22:23], -1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
; GCN-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 ; 4-byte Folded Reload
-; GCN-O0-NEXT: s_mov_b64 exec, s[22:23]
+; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
; GCN-O0-NEXT: v_readlane_b32 s4, v7, 2
; GCN-O0-NEXT: v_readlane_b32 s5, v7, 3
@@ -3969,15 +3964,15 @@ define i32 @extract_dyn_i32_5(<5 x i32> inreg %arg, i32 %idx) {
; GCN-O0-NEXT: s_mov_b64 s[6:7], s[4:5]
; GCN-O0-NEXT: v_writelane_b32 v7, s6, 2
; GCN-O0-NEXT: v_writelane_b32 v7, s7, 3
-; GCN-O0-NEXT: s_or_saveexec_b64 s[22:23], -1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
; GCN-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b64 exec, s[22:23]
+; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
; GCN-O0-NEXT: s_xor_b64 exec, exec, s[4:5]
; GCN-O0-NEXT: s_cbranch_execnz .LBB26_1
; GCN-O0-NEXT: ; %bb.2:
-; GCN-O0-NEXT: s_or_saveexec_b64 s[22:23], -1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
; GCN-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 ; 4-byte Folded Reload
-; GCN-O0-NEXT: s_mov_b64 exec, s[22:23]
+; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/196056
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