[llvm] [BOLT][AArch64] Add support for LDR relaxation on LDRSWl (PR #196051)

[Shanzhi Chen via llvm-commits]

chenshanzhi wrote:

When walking through AArch64RelaxationPass, I noticed this TODO, which this PR partially addresses.
https://github.com/llvm/llvm-project/blob/3ed76d05a78dd543a44abf0a152fe88d3a21bb1d/bolt/lib/Passes/AArch64RelaxationPass.cpp#L48-L50

AArch64 currently has 6 `LoadLiteral` instructions: 3 with GPR as destination register (`LDRWl`, `LDRXl`, `LDRSWl`) and 3 with FPR as destination register (`LDRSl`, `LDRDl`, `LDRQl`).

The `isLoadLiteralGPR` in this PR corresponds to the first three instructions.

For the latter three (planned to be represented by `isLoadLiteralFPR`), since AArch64 now supports LivenessAnalysis, we can leverage it to obtain available registers as the base register for LDR relaxation, enabling support for these instructions. This is planned for a follow-up PR. LDR relaxation for the 3 `isLoadLiteralFPR` instructions is planned to be controlled by a `cl::Hidden` option, as LivenessAnalysis may not always find available registers.

https://github.com/llvm/llvm-project/pull/196051