[llvm] [AArch64][ISel] Use SVE for fixed width vector reductions (PR #195806)
Harry Ramsey via llvm-commits
llvm-commits at lists.llvm.org
Wed May 6 03:11:39 PDT 2026
https://github.com/Harry-Ramsey updated https://github.com/llvm/llvm-project/pull/195806
>From 2462d23e4252bef5b4c7d6a53870317d61c832f9 Mon Sep 17 00:00:00 2001
From: Harry Ramsey <harry.ramsey at arm.com>
Date: Thu, 30 Apr 2026 13:24:04 +0000
Subject: [PATCH 1/3] [AArch64][ISel] Use SVE for fixed-width vector reductions
Enable custom lowering for v2i64 [s|u][min|max] reductions when only SVE
is. Allowing fixed-width SVE to use predicated reductions such as smaxv
where NEON has no native equivalent.
Remove the fixed-length vector preference to allow more SVE reduction
operations to be selected when appropriate.
---
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 15 +++++++--------
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index f5082b779d1db..80565d9baab1b 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1935,13 +1935,13 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
setOperationAction(ISD::MUL, MVT::v1i64, Custom);
setOperationAction(ISD::MUL, MVT::v2i64, Custom);
+ // NEON doesn't support 128-bit [s|u][min|max] operations.
+ // With SVE we can try lowering these to predicated operations (e.g. smaxv).
// With SVE2 we can try lowering these to pairwise operations (e.g. smaxp).
- if (Subtarget->hasSVE2() || Subtarget->isStreamingSVEAvailable()) {
- setOperationAction(ISD::VECREDUCE_SMAX, MVT::v2i64, Custom);
- setOperationAction(ISD::VECREDUCE_SMIN, MVT::v2i64, Custom);
- setOperationAction(ISD::VECREDUCE_UMAX, MVT::v2i64, Custom);
- setOperationAction(ISD::VECREDUCE_UMIN, MVT::v2i64, Custom);
- }
+ setOperationAction(ISD::VECREDUCE_SMAX, MVT::v2i64, Custom);
+ setOperationAction(ISD::VECREDUCE_SMIN, MVT::v2i64, Custom);
+ setOperationAction(ISD::VECREDUCE_UMAX, MVT::v2i64, Custom);
+ setOperationAction(ISD::VECREDUCE_UMIN, MVT::v2i64, Custom);
// NOTE: Currently this has to happen after computeRegisterProperties rather
// than the preferred option of combining it with the addRegisterClass call.
@@ -32147,8 +32147,7 @@ bool AArch64TargetLowering::shouldLowerReductionToSVE(
(RdxOp.getOpcode() != ISD::VECREDUCE_ADD &&
SrcVT.getVectorElementType() == MVT::i64);
- bool UseSVE = useSVEForFixedLengthVectorVT(
- SrcVT, OverrideNEON && Subtarget->useSVEForFixedLengthVectors());
+ bool UseSVE = useSVEForFixedLengthVectorVT(SrcVT, OverrideNEON);
// Always lower v2i64 vectors to pairwise SVE2 operations when possible as
// NEON does not natively support reductions on v2i64. Lower v2i32 to pairwise
>From 04a20de90269a5fe474618578f6ee4e3be259a96 Mon Sep 17 00:00:00 2001
From: Harry Ramsey <harry.ramsey at arm.com>
Date: Tue, 5 May 2026 08:54:22 +0000
Subject: [PATCH 2/3] fixup! [AArch64][ISel] Use SVE for fixed-width vector
reductions
---
llvm/test/CodeGen/AArch64/v2i64-min-max.ll | 42 ++++++++++++++++++-
.../AArch64/vector-extract-last-active.ll | 19 ++++-----
2 files changed, 50 insertions(+), 11 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/v2i64-min-max.ll b/llvm/test/CodeGen/AArch64/v2i64-min-max.ll
index 88c5e98cbdbe5..2c861e94d4ac1 100644
--- a/llvm/test/CodeGen/AArch64/v2i64-min-max.ll
+++ b/llvm/test/CodeGen/AArch64/v2i64-min-max.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64 -mattr=+sve2 | FileCheck %s -check-prefixes=CHECK-SVE2
-; RUN: llc < %s -mtriple=aarch64 -mattr=+sve | FileCheck %s -check-prefixes=CHECK
+; RUN: llc < %s -mtriple=aarch64 -mattr=+sve | FileCheck %s -check-prefixes=CHECK-SVE
; RUN: llc < %s -mtriple=aarch64 | FileCheck %s -check-prefixes=CHECK
define i64 @smax(<2 x i64> %0) {
@@ -12,6 +12,14 @@ define i64 @smax(<2 x i64> %0) {
; CHECK-SVE2-NEXT: fmov x0, d0
; CHECK-SVE2-NEXT: ret
;
+; CHECK-SVE-LABEL: smax:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.d, vl2
+; CHECK-SVE-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-SVE-NEXT: smaxv d0, p0, z0.d
+; CHECK-SVE-NEXT: fmov x0, d0
+; CHECK-SVE-NEXT: ret
+;
; CHECK-LABEL: smax:
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, v0.d[1]
@@ -34,6 +42,14 @@ define i64 @umax(<2 x i64> %0) {
; CHECK-SVE2-NEXT: fmov x0, d0
; CHECK-SVE2-NEXT: ret
;
+; CHECK-SVE-LABEL: umax:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.d, vl2
+; CHECK-SVE-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-SVE-NEXT: umaxv d0, p0, z0.d
+; CHECK-SVE-NEXT: fmov x0, d0
+; CHECK-SVE-NEXT: ret
+;
; CHECK-LABEL: umax:
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, v0.d[1]
@@ -56,6 +72,14 @@ define i64 @smin(<2 x i64> %0) {
; CHECK-SVE2-NEXT: fmov x0, d0
; CHECK-SVE2-NEXT: ret
;
+; CHECK-SVE-LABEL: smin:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.d, vl2
+; CHECK-SVE-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-SVE-NEXT: sminv d0, p0, z0.d
+; CHECK-SVE-NEXT: fmov x0, d0
+; CHECK-SVE-NEXT: ret
+;
; CHECK-LABEL: smin:
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, v0.d[1]
@@ -78,6 +102,14 @@ define i64 @umin(<2 x i64> %0) {
; CHECK-SVE2-NEXT: fmov x0, d0
; CHECK-SVE2-NEXT: ret
;
+; CHECK-SVE-LABEL: umin:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.d, vl2
+; CHECK-SVE-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-SVE-NEXT: uminv d0, p0, z0.d
+; CHECK-SVE-NEXT: fmov x0, d0
+; CHECK-SVE-NEXT: ret
+;
; CHECK-LABEL: umin:
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, v0.d[1]
@@ -100,6 +132,14 @@ define i64 @umin_different_vectors(<2 x i64> %0, <2 x i64> %1) {
; CHECK-SVE2-NEXT: csel x0, x9, x8, lo
; CHECK-SVE2-NEXT: ret
;
+; CHECK-SVE-LABEL: umin_different_vectors:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: mov x8, v1.d[1]
+; CHECK-SVE-NEXT: fmov x9, d0
+; CHECK-SVE-NEXT: cmp x9, x8
+; CHECK-SVE-NEXT: csel x0, x9, x8, lo
+; CHECK-SVE-NEXT: ret
+;
; CHECK-LABEL: umin_different_vectors:
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, v1.d[1]
diff --git a/llvm/test/CodeGen/AArch64/vector-extract-last-active.ll b/llvm/test/CodeGen/AArch64/vector-extract-last-active.ll
index 8147131c2def4..a99b4a5f477d9 100644
--- a/llvm/test/CodeGen/AArch64/vector-extract-last-active.ll
+++ b/llvm/test/CodeGen/AArch64/vector-extract-last-active.ll
@@ -527,24 +527,23 @@ define i32 @extract_last_active_v3i32(<3 x i32> %a, <3 x i1> %c) {
; SVE-FIXED-NEXT: .cfi_def_cfa_offset 16
; SVE-FIXED-NEXT: movi v1.2d, #0000000000000000
; SVE-FIXED-NEXT: index z3.h, #0, #1
-; SVE-FIXED-NEXT: mov x11, sp
+; SVE-FIXED-NEXT: ptrue p0.h, vl4
+; SVE-FIXED-NEXT: mov x9, sp
; SVE-FIXED-NEXT: str q0, [sp]
; SVE-FIXED-NEXT: mov v1.h[0], w0
; SVE-FIXED-NEXT: mov v1.h[1], w1
; SVE-FIXED-NEXT: mov v1.h[2], w2
; SVE-FIXED-NEXT: shl v2.4h, v1.4h, #15
-; SVE-FIXED-NEXT: fmov x8, d1
+; SVE-FIXED-NEXT: orv h1, p0, z1.h
; SVE-FIXED-NEXT: cmlt v2.4h, v2.4h, #0
-; SVE-FIXED-NEXT: lsr x9, x8, #32
-; SVE-FIXED-NEXT: orr w9, w8, w9
; SVE-FIXED-NEXT: and v2.8b, v2.8b, v3.8b
-; SVE-FIXED-NEXT: orr w8, w9, w8, lsr #16
-; SVE-FIXED-NEXT: tst w8, #0x1
; SVE-FIXED-NEXT: umaxv h2, v2.4h
-; SVE-FIXED-NEXT: fmov w10, s2
-; SVE-FIXED-NEXT: bfi x11, x10, #2, #2
-; SVE-FIXED-NEXT: ldr w9, [x11]
-; SVE-FIXED-NEXT: csinv w0, w9, wzr, ne
+; SVE-FIXED-NEXT: fmov w8, s2
+; SVE-FIXED-NEXT: bfi x9, x8, #2, #2
+; SVE-FIXED-NEXT: ldr w8, [x9]
+; SVE-FIXED-NEXT: fmov w9, s1
+; SVE-FIXED-NEXT: tst w9, #0x1
+; SVE-FIXED-NEXT: csinv w0, w8, wzr, ne
; SVE-FIXED-NEXT: add sp, sp, #16
; SVE-FIXED-NEXT: ret
%res = call i32 @llvm.experimental.vector.extract.last.active.v3i32(<3 x i32> %a, <3 x i1> %c, i32 -1)
>From 7e0e274d337c5ca17c30061bd5a9fc6812146300 Mon Sep 17 00:00:00 2001
From: Harry Ramsey <harry.ramsey at arm.com>
Date: Wed, 6 May 2026 09:57:20 +0000
Subject: [PATCH 3/3] fixup! [AArch64][ISel] Use SVE for fixed-width vector
reductions
---
.../AArch64/sve-fixed-length-reduce.ll | 284 ++++++++++++++++++
1 file changed, 284 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/sve-fixed-length-reduce.ll
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-reduce.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-reduce.ll
new file mode 100644
index 0000000000000..a3f0d50e5716a
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-reduce.ll
@@ -0,0 +1,284 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu -mattr=+sve | FileCheck %s --check-prefixes=CHECK-SVE
+
+define i8 @test_v8i8_and(<8 x i8> %a) {
+; CHECK-SVE-LABEL: test_v8i8_and:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.b, vl8
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 def $z0
+; CHECK-SVE-NEXT: andv b0, p0, z0.b
+; CHECK-SVE-NEXT: fmov w0, s0
+; CHECK-SVE-NEXT: ret
+ %r = call i8 @llvm.vector.reduce.and(<8 x i8> %a)
+ ret i8 %r
+}
+
+define i8 @test_v16i8_and(<16 x i8> %a) {
+; CHECK-SVE-LABEL: test_v16i8_and:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.b, vl16
+; CHECK-SVE-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-SVE-NEXT: andv b0, p0, z0.b
+; CHECK-SVE-NEXT: fmov w0, s0
+; CHECK-SVE-NEXT: ret
+ %r = call i8 @llvm.vector.reduce.and(<16 x i8> %a)
+ ret i8 %r
+}
+
+define i16 @test_v4i16_and(<4 x i16> %a) {
+; CHECK-SVE-LABEL: test_v4i16_and:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.h, vl4
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 def $z0
+; CHECK-SVE-NEXT: andv h0, p0, z0.h
+; CHECK-SVE-NEXT: fmov w0, s0
+; CHECK-SVE-NEXT: ret
+ %r = call i16 @llvm.vector.reduce.and(<4 x i16> %a)
+ ret i16 %r
+}
+
+define i16 @test_v8i16_and(<8 x i16> %a) {
+; CHECK-SVE-LABEL: test_v8i16_and:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.h, vl8
+; CHECK-SVE-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-SVE-NEXT: andv h0, p0, z0.h
+; CHECK-SVE-NEXT: fmov w0, s0
+; CHECK-SVE-NEXT: ret
+ %r = call i16 @llvm.vector.reduce.and(<8 x i16> %a)
+ ret i16 %r
+}
+
+define i32 @test_v2i32_and(<2 x i32> %a) {
+; CHECK-SVE-LABEL: test_v2i32_and:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.s, vl2
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 def $z0
+; CHECK-SVE-NEXT: andv s0, p0, z0.s
+; CHECK-SVE-NEXT: fmov w0, s0
+; CHECK-SVE-NEXT: ret
+ %r = call i32 @llvm.vector.reduce.and(<2 x i32> %a)
+ ret i32 %r
+}
+
+define i32 @test_v4i32_and(<4 x i32> %a) {
+; CHECK-SVE-LABEL: test_v4i32_and:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.s, vl4
+; CHECK-SVE-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-SVE-NEXT: andv s0, p0, z0.s
+; CHECK-SVE-NEXT: fmov w0, s0
+; CHECK-SVE-NEXT: ret
+ %r = call i32 @llvm.vector.reduce.and(<4 x i32> %a)
+ ret i32 %r
+}
+
+define i64 @test_v1i64_and(<1 x i64> %a) {
+; CHECK-SVE-LABEL: test_v1i64_and:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SVE-NEXT: fmov x0, d0
+; CHECK-SVE-NEXT: ret
+ %r = call i64 @llvm.vector.reduce.and(<1 x i64> %a)
+ ret i64 %r
+}
+
+define i64 @test_v2i64_and(<2 x i64> %a) {
+; CHECK-SVE-LABEL: test_v2i64_and:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.d, vl2
+; CHECK-SVE-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-SVE-NEXT: andv d0, p0, z0.d
+; CHECK-SVE-NEXT: fmov x0, d0
+; CHECK-SVE-NEXT: ret
+ %r = call i64 @llvm.vector.reduce.and(<2 x i64> %a)
+ ret i64 %r
+}
+
+define i8 @test_v8i8_or(<8 x i8> %a) {
+; CHECK-SVE-LABEL: test_v8i8_or:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.b, vl8
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 def $z0
+; CHECK-SVE-NEXT: orv b0, p0, z0.b
+; CHECK-SVE-NEXT: fmov w0, s0
+; CHECK-SVE-NEXT: ret
+ %r = call i8 @llvm.vector.reduce.or(<8 x i8> %a)
+ ret i8 %r
+}
+
+define i8 @test_v16i8_or(<16 x i8> %a) {
+; CHECK-SVE-LABEL: test_v16i8_or:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.b, vl16
+; CHECK-SVE-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-SVE-NEXT: orv b0, p0, z0.b
+; CHECK-SVE-NEXT: fmov w0, s0
+; CHECK-SVE-NEXT: ret
+ %r = call i8 @llvm.vector.reduce.or(<16 x i8> %a)
+ ret i8 %r
+}
+
+define i16 @test_v4i16_or(<4 x i16> %a) {
+; CHECK-SVE-LABEL: test_v4i16_or:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.h, vl4
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 def $z0
+; CHECK-SVE-NEXT: orv h0, p0, z0.h
+; CHECK-SVE-NEXT: fmov w0, s0
+; CHECK-SVE-NEXT: ret
+ %r = call i16 @llvm.vector.reduce.or(<4 x i16> %a)
+ ret i16 %r
+}
+
+define i16 @test_v8i16_or(<8 x i16> %a) {
+; CHECK-SVE-LABEL: test_v8i16_or:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.h, vl8
+; CHECK-SVE-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-SVE-NEXT: orv h0, p0, z0.h
+; CHECK-SVE-NEXT: fmov w0, s0
+; CHECK-SVE-NEXT: ret
+ %r = call i16 @llvm.vector.reduce.or(<8 x i16> %a)
+ ret i16 %r
+}
+
+define i32 @test_v2i32_or(<2 x i32> %a) {
+; CHECK-SVE-LABEL: test_v2i32_or:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.s, vl2
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 def $z0
+; CHECK-SVE-NEXT: orv s0, p0, z0.s
+; CHECK-SVE-NEXT: fmov w0, s0
+; CHECK-SVE-NEXT: ret
+ %r = call i32 @llvm.vector.reduce.or(<2 x i32> %a)
+ ret i32 %r
+}
+
+define i32 @test_v4i32_or(<4 x i32> %a) {
+; CHECK-SVE-LABEL: test_v4i32_or:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.s, vl4
+; CHECK-SVE-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-SVE-NEXT: orv s0, p0, z0.s
+; CHECK-SVE-NEXT: fmov w0, s0
+; CHECK-SVE-NEXT: ret
+ %r = call i32 @llvm.vector.reduce.or(<4 x i32> %a)
+ ret i32 %r
+}
+
+define i64 @test_v1i64_or(<1 x i64> %a) {
+; CHECK-SVE-LABEL: test_v1i64_or:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SVE-NEXT: fmov x0, d0
+; CHECK-SVE-NEXT: ret
+ %r = call i64 @llvm.vector.reduce.or(<1 x i64> %a)
+ ret i64 %r
+}
+
+define i64 @test_v2i64_or(<2 x i64> %a) {
+; CHECK-SVE-LABEL: test_v2i64_or:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.d, vl2
+; CHECK-SVE-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-SVE-NEXT: orv d0, p0, z0.d
+; CHECK-SVE-NEXT: fmov x0, d0
+; CHECK-SVE-NEXT: ret
+ %r = call i64 @llvm.vector.reduce.or(<2 x i64> %a)
+ ret i64 %r
+}
+
+define i8 @test_v8i8_xor(<8 x i8> %a) {
+; CHECK-SVE-LABEL: test_v8i8_xor:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.b, vl8
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 def $z0
+; CHECK-SVE-NEXT: eorv b0, p0, z0.b
+; CHECK-SVE-NEXT: fmov w0, s0
+; CHECK-SVE-NEXT: ret
+ %r = call i8 @llvm.vector.reduce.xor(<8 x i8> %a)
+ ret i8 %r
+}
+
+define i8 @test_v16i8_xor(<16 x i8> %a) {
+; CHECK-SVE-LABEL: test_v16i8_xor:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.b, vl16
+; CHECK-SVE-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-SVE-NEXT: eorv b0, p0, z0.b
+; CHECK-SVE-NEXT: fmov w0, s0
+; CHECK-SVE-NEXT: ret
+ %r = call i8 @llvm.vector.reduce.xor(<16 x i8> %a)
+ ret i8 %r
+}
+
+define i16 @test_v4i16_xor(<4 x i16> %a) {
+; CHECK-SVE-LABEL: test_v4i16_xor:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.h, vl4
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 def $z0
+; CHECK-SVE-NEXT: eorv h0, p0, z0.h
+; CHECK-SVE-NEXT: fmov w0, s0
+; CHECK-SVE-NEXT: ret
+ %r = call i16 @llvm.vector.reduce.xor(<4 x i16> %a)
+ ret i16 %r
+}
+
+define i16 @test_v8i16_xor(<8 x i16> %a) {
+; CHECK-SVE-LABEL: test_v8i16_xor:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.h, vl8
+; CHECK-SVE-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-SVE-NEXT: eorv h0, p0, z0.h
+; CHECK-SVE-NEXT: fmov w0, s0
+; CHECK-SVE-NEXT: ret
+ %r = call i16 @llvm.vector.reduce.xor(<8 x i16> %a)
+ ret i16 %r
+}
+
+define i32 @test_v2i32_xor(<2 x i32> %a) {
+; CHECK-SVE-LABEL: test_v2i32_xor:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.s, vl2
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 def $z0
+; CHECK-SVE-NEXT: eorv s0, p0, z0.s
+; CHECK-SVE-NEXT: fmov w0, s0
+; CHECK-SVE-NEXT: ret
+ %r = call i32 @llvm.vector.reduce.xor(<2 x i32> %a)
+ ret i32 %r
+}
+
+define i32 @test_v4i32_xor(<4 x i32> %a) {
+; CHECK-SVE-LABEL: test_v4i32_xor:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.s, vl4
+; CHECK-SVE-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-SVE-NEXT: eorv s0, p0, z0.s
+; CHECK-SVE-NEXT: fmov w0, s0
+; CHECK-SVE-NEXT: ret
+ %r = call i32 @llvm.vector.reduce.xor(<4 x i32> %a)
+ ret i32 %r
+}
+
+define i64 @test_v1i64_xor(<1 x i64> %a) {
+; CHECK-SVE-LABEL: test_v1i64_xor:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SVE-NEXT: fmov x0, d0
+; CHECK-SVE-NEXT: ret
+ %r = call i64 @llvm.vector.reduce.xor(<1 x i64> %a)
+ ret i64 %r
+}
+
+define i64 @test_v2i64_xor(<2 x i64> %a) {
+; CHECK-SVE-LABEL: test_v2i64_xor:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.d, vl2
+; CHECK-SVE-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-SVE-NEXT: eorv d0, p0, z0.d
+; CHECK-SVE-NEXT: fmov x0, d0
+; CHECK-SVE-NEXT: ret
+ %r = call i64 @llvm.vector.reduce.xor(<2 x i64> %a)
+ ret i64 %r
+}
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