[llvm] [NFC][AArch64] Extract MOVaddr* expansion model into common header (PR #183503)
Guy David via llvm-commits
llvm-commits at lists.llvm.org
Wed May 6 03:05:59 PDT 2026
https://github.com/guy-david updated https://github.com/llvm/llvm-project/pull/183503
>From a333270fb18914a7e8033b92f864f39507954bd7 Mon Sep 17 00:00:00 2001
From: Guy David <guyda96 at gmail.com>
Date: Thu, 26 Feb 2026 11:34:40 +0200
Subject: [PATCH] [NFC][AArch64] Extract MOVaddr* expansion model into common
header
This makes the expansion logic reusable by getInstSizeInBytes in a
follow-up patch.
---
...4ExpandImm.cpp => AArch64ExpandPseudo.cpp} | 78 ++++++----
...rch64ExpandImm.h => AArch64ExpandPseudo.h} | 21 ++-
.../AArch64/AArch64ExpandPseudoInsts.cpp | 133 ++++++++++--------
.../Target/AArch64/AArch64ISelLowering.cpp | 19 +--
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 10 +-
.../Target/AArch64/AArch64MIPeepholeOpt.cpp | 10 +-
.../AArch64/AArch64TargetTransformInfo.cpp | 6 +-
llvm/lib/Target/AArch64/CMakeLists.txt | 2 +-
.../GISel/AArch64PostLegalizerLowering.cpp | 6 +-
9 files changed, 166 insertions(+), 119 deletions(-)
rename llvm/lib/Target/AArch64/{AArch64ExpandImm.cpp => AArch64ExpandPseudo.cpp} (91%)
rename llvm/lib/Target/AArch64/{AArch64ExpandImm.h => AArch64ExpandPseudo.h} (50%)
diff --git a/llvm/lib/Target/AArch64/AArch64ExpandImm.cpp b/llvm/lib/Target/AArch64/AArch64ExpandPseudo.cpp
similarity index 91%
rename from llvm/lib/Target/AArch64/AArch64ExpandImm.cpp
rename to llvm/lib/Target/AArch64/AArch64ExpandPseudo.cpp
index f44cb8a0628d7..2f618b67f21ea 100644
--- a/llvm/lib/Target/AArch64/AArch64ExpandImm.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ExpandPseudo.cpp
@@ -1,4 +1,4 @@
-//===- AArch64ExpandImm.h - AArch64 Immediate Expansion -------------------===//
+//===- AArch64ExpandPseudo.cpp - AArch64 Pseudo Expansion -----------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -6,16 +6,16 @@
//
//===----------------------------------------------------------------------===//
//
-// This file implements the AArch64ExpandImm stuff.
+// This file implements the AArch64 pseudo-instruction expansion models.
//
//===----------------------------------------------------------------------===//
+#include "AArch64ExpandPseudo.h"
#include "AArch64.h"
-#include "AArch64ExpandImm.h"
#include "MCTargetDesc/AArch64AddressingModes.h"
using namespace llvm;
-using namespace llvm::AArch64_IMM;
+using namespace llvm::AArch64_ExpandPseudo;
/// Helper function which extracts the specified 16-bit chunk from a
/// 64-bit value.
@@ -41,7 +41,7 @@ static bool canUseOrr(uint64_t Chunk, uint64_t &Encoding) {
/// of the chunks doesn't matter), assuming |A|A|A|A| can be materialized with
/// an ORR instruction.
static bool tryToreplicateChunks(uint64_t UImm,
- SmallVectorImpl<ImmInsnModel> &Insn) {
+ SmallVectorImpl<ImmInsnModel> &Insn) {
using CountMap = DenseMap<uint64_t, unsigned>;
CountMap Counts;
@@ -64,7 +64,7 @@ static bool tryToreplicateChunks(uint64_t UImm,
const bool CountThree = Count == 3;
- Insn.push_back({ AArch64::ORRXri, 0, Encoding });
+ Insn.push_back({AArch64::ORRXri, 0, Encoding});
unsigned ShiftAmt = 0;
uint64_t Imm16 = 0;
@@ -77,8 +77,8 @@ static bool tryToreplicateChunks(uint64_t UImm,
}
// Create the first MOVK instruction.
- Insn.push_back({ AArch64::MOVKXi, Imm16,
- AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt) });
+ Insn.push_back({AArch64::MOVKXi, Imm16,
+ AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt)});
// In case we have three instances the whole constant is now materialized
// and we can exit.
@@ -92,8 +92,8 @@ static bool tryToreplicateChunks(uint64_t UImm,
if (Imm16 != ChunkVal)
break;
}
- Insn.push_back({ AArch64::MOVKXi, Imm16,
- AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt) });
+ Insn.push_back({AArch64::MOVKXi, Imm16,
+ AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt)});
return true;
}
@@ -220,21 +220,21 @@ static bool trySequenceOfOnes(uint64_t UImm,
// Create the ORR-immediate instruction.
uint64_t Encoding = 0;
AArch64_AM::processLogicalImmediate(OrrImm, 64, Encoding);
- Insn.push_back({ AArch64::ORRXri, 0, Encoding });
+ Insn.push_back({AArch64::ORRXri, 0, Encoding});
const bool SingleMovk = SecondMovkIdx == NotSet;
- Insn.push_back({ AArch64::MOVKXi, getChunk(UImm, FirstMovkIdx),
- AArch64_AM::getShifterImm(AArch64_AM::LSL,
- FirstMovkIdx * 16) });
+ Insn.push_back(
+ {AArch64::MOVKXi, getChunk(UImm, FirstMovkIdx),
+ AArch64_AM::getShifterImm(AArch64_AM::LSL, FirstMovkIdx * 16)});
// Early exit in case we only need to emit a single MOVK instruction.
if (SingleMovk)
return true;
// Create the second MOVK instruction.
- Insn.push_back({ AArch64::MOVKXi, getChunk(UImm, SecondMovkIdx),
- AArch64_AM::getShifterImm(AArch64_AM::LSL,
- SecondMovkIdx * 16) });
+ Insn.push_back(
+ {AArch64::MOVKXi, getChunk(UImm, SecondMovkIdx),
+ AArch64_AM::getShifterImm(AArch64_AM::LSL, SecondMovkIdx * 16)});
return true;
}
@@ -526,11 +526,31 @@ static bool tryEorOfLogicalImmediates(uint64_t Imm,
return false;
}
+/// Describe the expansion of a MOVaddr-family pseudo instruction.
+/// Returns a sequence of opcodes that the pseudo expands into.
+void AArch64_ExpandPseudo::expandMOVAddr(unsigned Opcode, unsigned TargetFlags,
+ bool IsTargetMachO,
+ SmallVectorImpl<AddrInsnModel> &Insn) {
+ if (Opcode == AArch64::MOVaddrBA && IsTargetMachO) {
+ // Block address on MachO goes through a constant pool.
+ Insn.push_back({AArch64::ADRP});
+ Insn.push_back({AArch64::LDRXui});
+ return;
+ }
+
+ Insn.push_back({AArch64::ADRP});
+
+ if (TargetFlags & AArch64II::MO_TAGGED)
+ Insn.push_back({AArch64::MOVKXi});
+
+ Insn.push_back({AArch64::ADDXri});
+}
+
/// \brief Expand a MOVi32imm or MOVi64imm pseudo instruction to a
/// MOVZ or MOVN of width BitSize followed by up to 3 MOVK instructions.
static inline void expandMOVImmSimple(uint64_t Imm, unsigned BitSize,
- unsigned OneChunks, unsigned ZeroChunks,
- SmallVectorImpl<ImmInsnModel> &Insn) {
+ unsigned OneChunks, unsigned ZeroChunks,
+ SmallVectorImpl<ImmInsnModel> &Insn) {
const unsigned Mask = 0xFFFF;
// Use a MOVZ or MOVN instruction to set the high bits, followed by one or
@@ -562,8 +582,8 @@ static inline void expandMOVImmSimple(uint64_t Imm, unsigned BitSize,
}
unsigned Imm16 = (Imm >> Shift) & Mask;
- Insn.push_back({ FirstOpc, Imm16,
- AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift) });
+ Insn.push_back(
+ {FirstOpc, Imm16, AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift)});
if (Shift == LastShift)
return;
@@ -580,8 +600,8 @@ static inline void expandMOVImmSimple(uint64_t Imm, unsigned BitSize,
if (Imm16 == (isNeg ? Mask : 0))
continue; // This 16-bit portion is already set correctly.
- Insn.push_back({ Opc, Imm16,
- AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift) });
+ Insn.push_back(
+ {Opc, Imm16, AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift)});
}
// Now, we get 16-bit divided Imm. If high and low bits are same in
@@ -595,8 +615,8 @@ static inline void expandMOVImmSimple(uint64_t Imm, unsigned BitSize,
/// Expand a MOVi32imm or MOVi64imm pseudo instruction to one or more
/// real move-immediate instructions to synthesize the immediate.
-void AArch64_IMM::expandMOVImm(uint64_t Imm, unsigned BitSize,
- SmallVectorImpl<ImmInsnModel> &Insn) {
+void AArch64_ExpandPseudo::expandMOVImm(uint64_t Imm, unsigned BitSize,
+ SmallVectorImpl<ImmInsnModel> &Insn) {
const unsigned Mask = 0xFFFF;
// Scan the immediate and count the number of 16-bit chunks which are either
@@ -624,7 +644,7 @@ void AArch64_IMM::expandMOVImm(uint64_t Imm, unsigned BitSize,
uint64_t Encoding;
if (AArch64_AM::processLogicalImmediate(UImm, BitSize, Encoding)) {
unsigned Opc = (BitSize == 32 ? AArch64::ORRWri : AArch64::ORRXri);
- Insn.push_back({ Opc, 0, Encoding });
+ Insn.push_back({Opc, 0, Encoding});
return;
}
@@ -659,12 +679,12 @@ void AArch64_IMM::expandMOVImm(uint64_t Imm, unsigned BitSize,
AArch64_AM::processLogicalImmediate(ReplicateChunk, BitSize,
Encoding)) {
// Create the ORR-immediate instruction.
- Insn.push_back({ AArch64::ORRXri, 0, Encoding });
+ Insn.push_back({AArch64::ORRXri, 0, Encoding});
// Create the MOVK instruction.
const unsigned Imm16 = getChunk(UImm, Shift / 16);
- Insn.push_back({ AArch64::MOVKXi, Imm16,
- AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift) });
+ Insn.push_back({AArch64::MOVKXi, Imm16,
+ AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift)});
return;
}
}
diff --git a/llvm/lib/Target/AArch64/AArch64ExpandImm.h b/llvm/lib/Target/AArch64/AArch64ExpandPseudo.h
similarity index 50%
rename from llvm/lib/Target/AArch64/AArch64ExpandImm.h
rename to llvm/lib/Target/AArch64/AArch64ExpandPseudo.h
index 42c97d2c3e9b5..af638b63fc856 100644
--- a/llvm/lib/Target/AArch64/AArch64ExpandImm.h
+++ b/llvm/lib/Target/AArch64/AArch64ExpandPseudo.h
@@ -1,4 +1,4 @@
-//===- AArch64ExpandImm.h - AArch64 Immediate Expansion ---------*- C++ -*-===//
+//===- AArch64ExpandPseudo.h - AArch64 Pseudo Expansion --------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -6,18 +6,18 @@
//
//===----------------------------------------------------------------------===//
//
-// This file contains the AArch64 immediate expansion stuff.
+// This file contains the AArch64 pseudo-instruction expansion models.
//
//===----------------------------------------------------------------------===//
-#ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64EXPANDIMM_H
-#define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64EXPANDIMM_H
+#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64EXPANDPSEUDO_H
+#define LLVM_LIB_TARGET_AARCH64_AARCH64EXPANDPSEUDO_H
#include "llvm/ADT/SmallVector.h"
namespace llvm {
-namespace AArch64_IMM {
+namespace AArch64_ExpandPseudo {
struct ImmInsnModel {
unsigned Opcode;
@@ -25,10 +25,17 @@ struct ImmInsnModel {
uint64_t Op2;
};
+struct AddrInsnModel {
+ unsigned Opcode;
+};
+
void expandMOVImm(uint64_t Imm, unsigned BitSize,
- SmallVectorImpl<ImmInsnModel> &Insn);
+ SmallVectorImpl<ImmInsnModel> &Insn);
+
+void expandMOVAddr(unsigned Opcode, unsigned TargetFlags, bool IsTargetMachO,
+ SmallVectorImpl<AddrInsnModel> &Insn);
-} // end namespace AArch64_IMM
+} // end namespace AArch64_ExpandPseudo
} // end namespace llvm
diff --git a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
index 535f9e4fac8c5..0aa6571d0f338 100644
--- a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
@@ -13,7 +13,7 @@
//
//===----------------------------------------------------------------------===//
-#include "AArch64ExpandImm.h"
+#include "AArch64ExpandPseudo.h"
#include "AArch64InstrInfo.h"
#include "AArch64MachineFunctionInfo.h"
#include "AArch64Subtarget.h"
@@ -155,8 +155,8 @@ bool AArch64ExpandPseudoImpl::expandMOVImm(MachineBasicBlock &MBB,
return true;
}
- SmallVector<AArch64_IMM::ImmInsnModel, 4> Insn;
- AArch64_IMM::expandMOVImm(Imm, BitSize, Insn);
+ SmallVector<AArch64_ExpandPseudo::ImmInsnModel, 4> Insn;
+ AArch64_ExpandPseudo::expandMOVImm(Imm, BitSize, Insn);
assert(Insn.size() != 0);
SmallVector<MachineInstrBuilder, 4> MIBS;
@@ -1539,70 +1539,89 @@ bool AArch64ExpandPseudoImpl::expandMI(MachineBasicBlock &MBB,
MI.eraseFromParent();
return true;
}
- case AArch64::MOVaddrBA: {
- MachineFunction &MF = *MI.getParent()->getParent();
- if (MF.getSubtarget<AArch64Subtarget>().isTargetMachO()) {
- // blockaddress expressions have to come from a constant pool because the
- // largest addend (and hence offset within a function) allowed for ADRP is
- // only 8MB.
- const BlockAddress *BA = MI.getOperand(1).getBlockAddress();
- assert(MI.getOperand(1).getOffset() == 0 && "unexpected offset");
-
- MachineConstantPool *MCP = MF.getConstantPool();
- unsigned CPIdx = MCP->getConstantPoolIndex(BA, Align(8));
-
- Register DstReg = MI.getOperand(0).getReg();
- auto MIB1 =
- BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADRP), DstReg)
- .addConstantPoolIndex(CPIdx, 0, AArch64II::MO_PAGE);
- auto MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
- TII->get(AArch64::LDRXui), DstReg)
- .addUse(DstReg)
- .addConstantPoolIndex(
- CPIdx, 0, AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
- transferImpOps(MI, MIB1, MIB2);
- MI.eraseFromParent();
- return true;
- }
- }
- [[fallthrough]];
+ case AArch64::MOVaddrBA:
case AArch64::MOVaddr:
case AArch64::MOVaddrJT:
case AArch64::MOVaddrCP:
case AArch64::MOVaddrTLS:
case AArch64::MOVaddrEXT: {
- // Expand into ADRP + ADD.
+ MachineFunction &MF = *MI.getParent()->getParent();
Register DstReg = MI.getOperand(0).getReg();
assert(DstReg != AArch64::XZR);
- MachineInstrBuilder MIB1 =
- BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADRP), DstReg)
- .add(MI.getOperand(1));
-
- if (MI.getOperand(1).getTargetFlags() & AArch64II::MO_TAGGED) {
- // MO_TAGGED on the page indicates a tagged address. Set the tag now.
- // We do so by creating a MOVK that sets bits 48-63 of the register to
- // (global address + 0x100000000 - PC) >> 48. This assumes that we're in
- // the small code model so we can assume a binary size of <= 4GB, which
- // makes the untagged PC relative offset positive. The binary must also be
- // loaded into address range [0, 2^48). Both of these properties need to
- // be ensured at runtime when using tagged addresses.
- auto Tag = MI.getOperand(1);
- Tag.setTargetFlags(AArch64II::MO_PREL | AArch64II::MO_G3);
- Tag.setOffset(0x100000000);
- BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi), DstReg)
- .addReg(DstReg)
- .add(Tag)
- .addImm(48);
+
+ SmallVector<AArch64_ExpandPseudo::AddrInsnModel, 3> Insn;
+ AArch64_ExpandPseudo::expandMOVAddr(
+ MI.getOpcode(), MI.getOperand(1).getTargetFlags(),
+ MF.getSubtarget<AArch64Subtarget>().isTargetMachO(), Insn);
+
+ // For MachO block addresses, we need to set up the constant pool entry
+ // before emitting instructions.
+ unsigned CPIdx = 0;
+ if (Insn.size() == 2 && Insn[1].Opcode == AArch64::LDRXui) {
+ // blockaddress expressions have to come from a constant pool because the
+ // largest addend (and hence offset within a function) allowed for ADRP is
+ // only 8MB.
+ const BlockAddress *BA = MI.getOperand(1).getBlockAddress();
+ assert(MI.getOperand(1).getOffset() == 0 && "unexpected offset");
+ MachineConstantPool *MCP = MF.getConstantPool();
+ CPIdx = MCP->getConstantPoolIndex(BA, Align(8));
}
- MachineInstrBuilder MIB2 =
- BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADDXri))
- .add(MI.getOperand(0))
- .addReg(DstReg)
- .add(MI.getOperand(2))
- .addImm(0);
+ MachineInstrBuilder FirstMIB;
+ MachineInstrBuilder LastMIB;
+ for (const auto &I : Insn) {
+ MachineInstrBuilder MIB;
+ switch (I.Opcode) {
+ case AArch64::ADRP:
+ MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADRP),
+ DstReg);
+ if (Insn[1].Opcode == AArch64::LDRXui)
+ MIB.addConstantPoolIndex(CPIdx, 0, AArch64II::MO_PAGE);
+ else
+ MIB.add(MI.getOperand(1));
+ break;
+ case AArch64::LDRXui:
+ MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::LDRXui),
+ DstReg)
+ .addUse(DstReg)
+ .addConstantPoolIndex(
+ CPIdx, 0, AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
+ break;
+ case AArch64::MOVKXi: {
+ // MO_TAGGED on the page indicates a tagged address. Set the tag now.
+ // We do so by creating a MOVK that sets bits 48-63 of the register to
+ // (global address + 0x100000000 - PC) >> 48. This assumes that we're in
+ // the small code model so we can assume a binary size of <= 4GB, which
+ // makes the untagged PC relative offset positive. The binary must also
+ // be loaded into address range [0, 2^48). Both of these properties need
+ // to be ensured at runtime when using tagged addresses.
+ auto Tag = MI.getOperand(1);
+ Tag.setTargetFlags(AArch64II::MO_PREL | AArch64II::MO_G3);
+ Tag.setOffset(0x100000000);
+ MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi),
+ DstReg)
+ .addReg(DstReg)
+ .add(Tag)
+ .addImm(48);
+ break;
+ }
+ case AArch64::ADDXri:
+ MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADDXri))
+ .add(MI.getOperand(0))
+ .addReg(DstReg)
+ .add(MI.getOperand(2))
+ .addImm(0);
+ break;
+ default:
+ llvm_unreachable("unexpected opcode in MOVaddr expansion");
+ }
+
+ if (!FirstMIB.getInstr())
+ FirstMIB = MIB;
+ LastMIB = MIB;
+ }
- transferImpOps(MI, MIB1, MIB2);
+ transferImpOps(MI, FirstMIB, LastMIB);
MI.eraseFromParent();
return true;
}
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 356ebdf407cff..8faa5442362c4 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -12,7 +12,7 @@
#include "AArch64ISelLowering.h"
#include "AArch64CallingConvention.h"
-#include "AArch64ExpandImm.h"
+#include "AArch64ExpandPseudo.h"
#include "AArch64MachineFunctionInfo.h"
#include "AArch64PerfectShuffle.h"
#include "AArch64RegisterInfo.h"
@@ -3704,8 +3704,8 @@ bool isLegalCmpImmed(APInt C) {
unsigned numberOfInstrToLoadImm(APInt C) {
uint64_t Imm = C.getZExtValue();
- SmallVector<AArch64_IMM::ImmInsnModel> Insn;
- AArch64_IMM::expandMOVImm(Imm, 32, Insn);
+ SmallVector<AArch64_ExpandPseudo::ImmInsnModel> Insn;
+ AArch64_ExpandPseudo::expandMOVImm(Imm, 32, Insn);
return Insn.size();
}
@@ -13104,8 +13104,9 @@ bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
// movw+movk+fmov vs. adrp+ldr (it's one instruction longer, but the
// movw+movk is fused). So by default we limit up to 2 instructions
// or 4 with hasFuseLiterals.
- SmallVector<AArch64_IMM::ImmInsnModel, 4> Insn;
- AArch64_IMM::expandMOVImm(ImmInt.getZExtValue(), VT.getSizeInBits(), Insn);
+ SmallVector<AArch64_ExpandPseudo::ImmInsnModel, 4> Insn;
+ AArch64_ExpandPseudo::expandMOVImm(ImmInt.getZExtValue(),
+ VT.getSizeInBits(), Insn);
assert(Insn.size() <= 4 &&
"Should be able to build any value with at most 4 moves");
unsigned Limit = (OptForSize ? 1 : (Subtarget->hasFuseLiterals() ? 4 : 2));
@@ -16342,8 +16343,8 @@ SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
// This optimization kicks in if the number of mov instructions
// is under 2
- SmallVector<AArch64_IMM::ImmInsnModel, 4> Insns;
- AArch64_IMM::expandMOVImm(PackedVal.getZExtValue(), 64, Insns);
+ SmallVector<AArch64_ExpandPseudo::ImmInsnModel, 4> Insns;
+ AArch64_ExpandPseudo::expandMOVImm(PackedVal.getZExtValue(), 64, Insns);
if (Insns.size() > 2)
return SDValue();
@@ -19102,10 +19103,10 @@ bool AArch64TargetLowering::isMulAddWithConstProfitable(
const APInt C1C2 = C1Node->getAPIntValue() * C2Node->getAPIntValue();
if (!isLegalAddImmediate(C1) || isLegalAddImmediate(C1C2.getSExtValue()))
return true;
- SmallVector<AArch64_IMM::ImmInsnModel, 4> Insn;
+ SmallVector<AArch64_ExpandPseudo::ImmInsnModel, 4> Insn;
// Adapt to the width of a register.
unsigned BitSize = VT.getSizeInBits() <= 32 ? 32 : 64;
- AArch64_IMM::expandMOVImm(C1C2.getZExtValue(), BitSize, Insn);
+ AArch64_ExpandPseudo::expandMOVImm(C1C2.getZExtValue(), BitSize, Insn);
if (Insn.size() > 1)
return false;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index c0a389f9b2d93..1efb848a6e67b 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -11,7 +11,7 @@
//===----------------------------------------------------------------------===//
#include "AArch64InstrInfo.h"
-#include "AArch64ExpandImm.h"
+#include "AArch64ExpandPseudo.h"
#include "AArch64MachineFunctionInfo.h"
#include "AArch64PointerAuth.h"
#include "AArch64Subtarget.h"
@@ -1257,8 +1257,8 @@ static bool isCheapImmediate(const MachineInstr &MI, unsigned BitSize) {
assert(BitSize == 64 && "Only bit sizes of 32 or 64 allowed");
uint64_t Imm = static_cast<uint64_t>(MI.getOperand(1).getImm());
- SmallVector<AArch64_IMM::ImmInsnModel, 4> Is;
- AArch64_IMM::expandMOVImm(Imm, BitSize, Is);
+ SmallVector<AArch64_ExpandPseudo::ImmInsnModel, 4> Is;
+ AArch64_ExpandPseudo::expandMOVImm(Imm, BitSize, Is);
return Is.size() <= 2;
}
@@ -8899,8 +8899,8 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
Pattern == AArch64MachineCombinerPattern::MULSUBXI_OP1;
uint64_t UImm = SignExtend64(IsSub ? -Imm : Imm, BitSize);
// Check that the immediate can be composed via a single instruction.
- SmallVector<AArch64_IMM::ImmInsnModel, 4> Insn;
- AArch64_IMM::expandMOVImm(UImm, BitSize, Insn);
+ SmallVector<AArch64_ExpandPseudo::ImmInsnModel, 4> Insn;
+ AArch64_ExpandPseudo::expandMOVImm(UImm, BitSize, Insn);
if (Insn.size() != 1)
return;
MachineInstrBuilder MIB1 =
diff --git a/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp b/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
index 900f22abcf8b0..cd0f069100422 100644
--- a/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
+++ b/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
@@ -69,7 +69,7 @@
//
//===----------------------------------------------------------------------===//
-#include "AArch64ExpandImm.h"
+#include "AArch64ExpandPseudo.h"
#include "AArch64InstrInfo.h"
#include "MCTargetDesc/AArch64AddressingModes.h"
#include "llvm/CodeGen/MachineDominators.h"
@@ -255,8 +255,8 @@ bool AArch64MIPeepholeOptImpl::trySplitLogicalImm(unsigned Opc,
return std::nullopt;
// If this immediate can be handled by one instruction, don't split it.
- SmallVector<AArch64_IMM::ImmInsnModel, 4> Insn;
- AArch64_IMM::expandMOVImm(Imm, RegSize, Insn);
+ SmallVector<AArch64_ExpandPseudo::ImmInsnModel, 4> Insn;
+ AArch64_ExpandPseudo::expandMOVImm(Imm, RegSize, Insn);
if (Insn.size() == 1)
return std::nullopt;
@@ -424,8 +424,8 @@ static bool splitAddSubImm(T Imm, unsigned RegSize, T &Imm0, T &Imm1) {
return false;
// The immediate can not be composed via a single instruction.
- SmallVector<AArch64_IMM::ImmInsnModel, 4> Insn;
- AArch64_IMM::expandMOVImm(Imm, RegSize, Insn);
+ SmallVector<AArch64_ExpandPseudo::ImmInsnModel, 4> Insn;
+ AArch64_ExpandPseudo::expandMOVImm(Imm, RegSize, Insn);
if (Insn.size() == 1)
return false;
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index aff89e00523c0..c0b74bc646942 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -7,7 +7,7 @@
//===----------------------------------------------------------------------===//
#include "AArch64TargetTransformInfo.h"
-#include "AArch64ExpandImm.h"
+#include "AArch64ExpandPseudo.h"
#include "AArch64PerfectShuffle.h"
#include "AArch64SMEAttributes.h"
#include "MCTargetDesc/AArch64AddressingModes.h"
@@ -407,8 +407,8 @@ InstructionCost AArch64TTIImpl::getIntImmCost(int64_t Val) const {
Val = ~Val;
// Calculate how many moves we will need to materialize this constant.
- SmallVector<AArch64_IMM::ImmInsnModel, 4> Insn;
- AArch64_IMM::expandMOVImm(Val, 64, Insn);
+ SmallVector<AArch64_ExpandPseudo::ImmInsnModel, 4> Insn;
+ AArch64_ExpandPseudo::expandMOVImm(Val, 64, Insn);
return Insn.size();
}
diff --git a/llvm/lib/Target/AArch64/CMakeLists.txt b/llvm/lib/Target/AArch64/CMakeLists.txt
index 80848845c2c24..441f2dce944cc 100644
--- a/llvm/lib/Target/AArch64/CMakeLists.txt
+++ b/llvm/lib/Target/AArch64/CMakeLists.txt
@@ -52,7 +52,7 @@ add_llvm_target(AArch64CodeGen
AArch64CondBrTuning.cpp
AArch64ConditionalCompares.cpp
AArch64DeadRegisterDefinitionsPass.cpp
- AArch64ExpandImm.cpp
+ AArch64ExpandPseudo.cpp
AArch64ExpandPseudoInsts.cpp
AArch64FalkorHWPFFix.cpp
AArch64FastISel.cpp
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
index f4e5649b9f449..24be86a3df3e7 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
@@ -20,7 +20,7 @@
//===----------------------------------------------------------------------===//
#include "AArch64.h"
-#include "AArch64ExpandImm.h"
+#include "AArch64ExpandPseudo.h"
#include "AArch64GlobalISelUtils.h"
#include "AArch64PerfectShuffle.h"
#include "AArch64Subtarget.h"
@@ -699,8 +699,8 @@ tryAdjustICmpImmAndPred(Register RHS, CmpInst::Predicate P,
return {{C, P}};
auto NumberOfInstrToLoadImm = [=](uint64_t Imm) {
- SmallVector<AArch64_IMM::ImmInsnModel> Insn;
- AArch64_IMM::expandMOVImm(Imm, 32, Insn);
+ SmallVector<AArch64_ExpandPseudo::ImmInsnModel> Insn;
+ AArch64_ExpandPseudo::expandMOVImm(Imm, 32, Insn);
return Insn.size();
};
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