[llvm] [AMDGPU] Add a mir test to verify register-coalesce works for eliminate-save-restore pattern (PR #191583)
Zeng Wu via llvm-commits
llvm-commits at lists.llvm.org
Tue May 5 22:26:33 PDT 2026
https://github.com/zwu-2025 updated https://github.com/llvm/llvm-project/pull/191583
>From b886e7af32f55518990c8a8a9c87717b9abf8d09 Mon Sep 17 00:00:00 2001
From: root <Zeng.Wu2 at amd.com>
Date: Sun, 26 Apr 2026 06:38:54 +0000
Subject: [PATCH 1/5] [AMDGPU] Add a mir test to verify register-coalesce works
for eliminate-save-restore pattern
---
.../AMDGPU/amdgcn-eliminate-save-restore.mir | 42 +++++++++++++++++++
1 file changed, 42 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/amdgcn-eliminate-save-restore.mir
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn-eliminate-save-restore.mir b/llvm/test/CodeGen/AMDGPU/amdgcn-eliminate-save-restore.mir
new file mode 100644
index 0000000000000..7184a70394171
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn-eliminate-save-restore.mir
@@ -0,0 +1,42 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -march=amdgcn -mcpu=gfx950 -run-pass='phi-node-elimination,register-coalescer' --verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name: test_basic_case
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: test_basic_case
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $vgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %other:vgpr_32 = V_MOV_B32_e32 42, implicit $exec
+ ; CHECK-NEXT: %orig:vgpr_32 = V_ADD_U32_e32 [[V_MOV_B32_e32_]], %other, implicit $exec
+ ; CHECK-NEXT: dead [[V_MUL_LO_U32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_LO_U32_e64 %orig, %orig, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 [[V_MOV_B32_e32_]], implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.1
+ bb.0:
+ successors: %bb.1(0x40000000)
+ liveins: $vgpr0
+
+ %orig_0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ S_BRANCH %bb.1
+
+ bb.1:
+ successors: %bb.1(0x40000000)
+ %tmp:vgpr_32 = PHI %orig_0, %bb.0, %orig_next, %bb.1
+
+ %other:vgpr_32 = V_MOV_B32_e32 42, implicit $exec
+ %orig:vgpr_32 = V_ADD_U32_e32 %tmp, %other, implicit $exec
+ %2:vgpr_32 = V_MUL_LO_U32_e64 %orig, %orig, implicit $exec
+ %orig_next:vgpr_32 = V_MOV_B32_e32 %tmp, implicit $exec
+
+ S_BRANCH %bb.1
+
+...
>From 5276e11598b4e64b97fb0a0fe67583357f33da3a Mon Sep 17 00:00:00 2001
From: root <Zeng.Wu2 at amd.com>
Date: Tue, 5 May 2026 18:28:50 +0000
Subject: [PATCH 2/5] update mir test: COPY instead of V_MOV if possible
---
llvm/test/CodeGen/AMDGPU/amdgcn-eliminate-save-restore.mir | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn-eliminate-save-restore.mir b/llvm/test/CodeGen/AMDGPU/amdgcn-eliminate-save-restore.mir
index 7184a70394171..cf2289e94f246 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn-eliminate-save-restore.mir
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn-eliminate-save-restore.mir
@@ -10,7 +10,7 @@ body: |
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 21, implicit $exec
; CHECK-NEXT: S_BRANCH %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
@@ -19,13 +19,12 @@ body: |
; CHECK-NEXT: %other:vgpr_32 = V_MOV_B32_e32 42, implicit $exec
; CHECK-NEXT: %orig:vgpr_32 = V_ADD_U32_e32 [[V_MOV_B32_e32_]], %other, implicit $exec
; CHECK-NEXT: dead [[V_MUL_LO_U32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_LO_U32_e64 %orig, %orig, implicit $exec
- ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 [[V_MOV_B32_e32_]], implicit $exec
; CHECK-NEXT: S_BRANCH %bb.1
bb.0:
successors: %bb.1(0x40000000)
liveins: $vgpr0
- %orig_0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ %orig_0:vgpr_32 = V_MOV_B32_e32 21, implicit $exec
S_BRANCH %bb.1
bb.1:
@@ -35,7 +34,7 @@ body: |
%other:vgpr_32 = V_MOV_B32_e32 42, implicit $exec
%orig:vgpr_32 = V_ADD_U32_e32 %tmp, %other, implicit $exec
%2:vgpr_32 = V_MUL_LO_U32_e64 %orig, %orig, implicit $exec
- %orig_next:vgpr_32 = V_MOV_B32_e32 %tmp, implicit $exec
+ %orig_next:vgpr_32 = COPY %tmp, implicit $exec
S_BRANCH %bb.1
>From 11af571d8cf86e4e46189d0d219cd7105a3f40e8 Mon Sep 17 00:00:00 2001
From: Zeng Wu <zengwu13 at amd.com>
Date: Tue, 5 May 2026 22:01:27 -0700
Subject: [PATCH 3/5] Update
llvm/test/CodeGen/AMDGPU/amdgcn-eliminate-save-restore.mir
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
---
llvm/test/CodeGen/AMDGPU/amdgcn-eliminate-save-restore.mir | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn-eliminate-save-restore.mir b/llvm/test/CodeGen/AMDGPU/amdgcn-eliminate-save-restore.mir
index cf2289e94f246..99c43a540c5a0 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn-eliminate-save-restore.mir
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn-eliminate-save-restore.mir
@@ -33,7 +33,7 @@ body: |
%other:vgpr_32 = V_MOV_B32_e32 42, implicit $exec
%orig:vgpr_32 = V_ADD_U32_e32 %tmp, %other, implicit $exec
- %2:vgpr_32 = V_MUL_LO_U32_e64 %orig, %orig, implicit $exec
+ %unused:vgpr_32 = V_MUL_LO_U32_e64 %orig, %orig, implicit $exec
%orig_next:vgpr_32 = COPY %tmp, implicit $exec
S_BRANCH %bb.1
>From 9185cc8f6ac002e5327b9772fadc264291096932 Mon Sep 17 00:00:00 2001
From: root <Zeng.Wu2 at amd.com>
Date: Wed, 6 May 2026 05:24:34 +0000
Subject: [PATCH 4/5] unresolved comments
---
.../AMDGPU/amdgcn-eliminate-save-restore.mir | 24 ++++++++++++++-----
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn-eliminate-save-restore.mir b/llvm/test/CodeGen/AMDGPU/amdgcn-eliminate-save-restore.mir
index 99c43a540c5a0..55f6adccd3f3b 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn-eliminate-save-restore.mir
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn-eliminate-save-restore.mir
@@ -1,11 +1,25 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -march=amdgcn -mcpu=gfx950 -run-pass='phi-node-elimination,register-coalescer' --verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx950 -run-pass='phi-node-elimination,register-coalescer' %s -o - | FileCheck %s
----
-name: test_basic_case
+# For now, the eliminate-save-restore pattern can be processed by `register-coalescer`.
+# For example, if the input is:
+# v_mov tmp, orig ; save
+# orig = op0(tmp) ... ; modify (overwrites orig, reads tmp)
+# op1(orig, ) ; uses of orig
+# v_mov orig, tmp ; restore
+#
+# then theoutput is transformed into:
+#
+# tmp = op0(orig, ) ; write to tmp instead
+# op1(tmp) ; replace uses of orig with tmp
+# save and restore movs are dead
+#
+# This mir test is added to make sure can if `register-coalescer` is changed in the future.
+
+name: eliminate_save_restore
tracksRegLiveness: true
body: |
- ; CHECK-LABEL: name: test_basic_case
+ ; CHECK-LABEL: name: eliminate_save_restore
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: liveins: $vgpr0
@@ -23,14 +37,12 @@ body: |
bb.0:
successors: %bb.1(0x40000000)
liveins: $vgpr0
-
%orig_0:vgpr_32 = V_MOV_B32_e32 21, implicit $exec
S_BRANCH %bb.1
bb.1:
successors: %bb.1(0x40000000)
%tmp:vgpr_32 = PHI %orig_0, %bb.0, %orig_next, %bb.1
-
%other:vgpr_32 = V_MOV_B32_e32 42, implicit $exec
%orig:vgpr_32 = V_ADD_U32_e32 %tmp, %other, implicit $exec
%unused:vgpr_32 = V_MUL_LO_U32_e64 %orig, %orig, implicit $exec
>From 59655667199c373b5657b6d58d011ec8d812684b Mon Sep 17 00:00:00 2001
From: root <Zeng.Wu2 at amd.com>
Date: Wed, 6 May 2026 05:26:15 +0000
Subject: [PATCH 5/5] extra blank line
---
llvm/test/CodeGen/AMDGPU/amdgcn-eliminate-save-restore.mir | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn-eliminate-save-restore.mir b/llvm/test/CodeGen/AMDGPU/amdgcn-eliminate-save-restore.mir
index 55f6adccd3f3b..83614cedcda8d 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn-eliminate-save-restore.mir
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn-eliminate-save-restore.mir
@@ -49,5 +49,4 @@ body: |
%orig_next:vgpr_32 = COPY %tmp, implicit $exec
S_BRANCH %bb.1
-
...
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