[llvm] [AArch64] Match vector neg(and X, 1) as CMTST (PR #194833)
Jiang Ning via llvm-commits
llvm-commits at lists.llvm.org
Tue May 5 18:58:01 PDT 2026
https://github.com/JiangNingHX updated https://github.com/llvm/llvm-project/pull/194833
>From 8679e972ddd50e9c000cc0c4a41f6c85b87117b6 Mon Sep 17 00:00:00 2001
From: JiangNing <jiangninghx at foxmail.com>
Date: Wed, 29 Apr 2026 18:48:57 +0800
Subject: [PATCH] [AArch64] Fold negated and-one vectors to cmtst
Recognize vector sub 0, (and X, splat(1)) as an all-ones compare
mask and lower it through the existing cmtst path.
Keep the fold limited to exact vector splat(1), excluding wider
bitcast constants, undef lanes, and splats such as 2/4/8.
Fixes #107093
---
.../Target/AArch64/AArch64ISelLowering.cpp | 25 ++++
.../test/CodeGen/AArch64/cmtst-neg-and-one.ll | 109 ++++++++++++++++++
2 files changed, 134 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/cmtst-neg-and-one.ll
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index f5082b779d1db..fb3a06a885a7b 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -3519,6 +3519,11 @@ static bool isZerosVector(const SDNode *N) {
return isNullConstant(Opnd0) || isNullFPConstant(Opnd0);
}
+static bool isOneVector(SDValue V) {
+ return isOneOrOneSplat(V) ||
+ (V.getOpcode() == AArch64ISD::DUP && isOneConstant(V.getOperand(0)));
+}
+
/// changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64
/// CC
static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC,
@@ -23225,6 +23230,24 @@ static SDValue performAddTruncShiftCombine(SDNode *N, SelectionDAG &DAG) {
return DAG.getNode(ISD::ADD, DL, VT, Trunc, Shift);
}
+static SDValue performSubNegAndOneCombine(SDNode *N, SelectionDAG &DAG) {
+ if (N->getOpcode() != ISD::SUB)
+ return SDValue();
+
+ EVT VT = N->getValueType(0);
+ if (!VT.isFixedLengthVector())
+ return SDValue();
+
+ SDValue Zero = N->getOperand(0);
+ SDValue And = N->getOperand(1);
+ if (!isZerosVector(Zero.getNode()) || And.getOpcode() != ISD::AND ||
+ !isOneVector(And.getOperand(1)))
+ return SDValue();
+
+ SDLoc DL(N);
+ return DAG.getSetCC(DL, VT, And, DAG.getConstant(0, DL, VT), ISD::SETNE);
+}
+
// Fold ADD(SBC(Y, 0, W), C) -> SBC(Y, -C, W)
// SBC(Y, 0, W) = Y - 0 - ~carry = Y + carry - 1
// Adding C: Y + carry - 1 + C = Y - (-C) - ~carry = SBC(Y, -C, W)
@@ -23275,6 +23298,8 @@ static SDValue performAddSubCombine(SDNode *N,
return Val;
if (SDValue Val = performAddTruncShiftCombine(N, DCI.DAG))
return Val;
+ if (SDValue Val = performSubNegAndOneCombine(N, DCI.DAG))
+ return Val;
if (SDValue Val = performAddWithSBCCombine(N, DCI.DAG))
return Val;
if (SDValue Val = performExtBinopLoadFold(N, DCI.DAG))
diff --git a/llvm/test/CodeGen/AArch64/cmtst-neg-and-one.ll b/llvm/test/CodeGen/AArch64/cmtst-neg-and-one.ll
new file mode 100644
index 0000000000000..c77c1a8b8b786
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/cmtst-neg-and-one.ll
@@ -0,0 +1,109 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon -verify-machineinstrs < %s | FileCheck %s
+
+define <16 x i8> @neg_and_one_v16i8(<16 x i8> %x) {
+; CHECK-LABEL: neg_and_one_v16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v1.16b, #1
+; CHECK-NEXT: cmtst v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
+ %and = and <16 x i8> %x, splat (i8 1)
+ %neg = sub <16 x i8> zeroinitializer, %and
+ ret <16 x i8> %neg
+}
+
+define <8 x i16> @neg_and_one_v8i16(<8 x i16> %x) {
+; CHECK-LABEL: neg_and_one_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v1.8h, #1
+; CHECK-NEXT: cmtst v0.8h, v0.8h, v1.8h
+; CHECK-NEXT: ret
+ %and = and <8 x i16> %x, splat (i16 1)
+ %neg = sub <8 x i16> zeroinitializer, %and
+ ret <8 x i16> %neg
+}
+
+define <4 x i32> @neg_and_one_v4i32(<4 x i32> %x) {
+; CHECK-LABEL: neg_and_one_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v1.4s, #1
+; CHECK-NEXT: cmtst v0.4s, v0.4s, v1.4s
+; CHECK-NEXT: ret
+ %and = and <4 x i32> %x, splat (i32 1)
+ %neg = sub <4 x i32> zeroinitializer, %and
+ ret <4 x i32> %neg
+}
+
+define <2 x i64> @neg_and_one_v2i64(<2 x i64> %x) {
+; CHECK-LABEL: neg_and_one_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #1 // =0x1
+; CHECK-NEXT: dup v1.2d, x8
+; CHECK-NEXT: cmtst v0.2d, v0.2d, v1.2d
+; CHECK-NEXT: ret
+ %and = and <2 x i64> %x, splat (i64 1)
+ %neg = sub <2 x i64> zeroinitializer, %and
+ ret <2 x i64> %neg
+}
+
+define <2 x i128> @neg_and_one_v2i128(<2 x i128> %x) {
+; CHECK-LABEL: neg_and_one_v2i128:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sbfx x0, x0, #0, #1
+; CHECK-NEXT: sbfx x2, x2, #0, #1
+; CHECK-NEXT: mov x1, x0
+; CHECK-NEXT: mov x3, x2
+; CHECK-NEXT: ret
+ %and = and <2 x i128> %x, splat (i128 1)
+ %neg = sub <2 x i128> zeroinitializer, %and
+ ret <2 x i128> %neg
+}
+
+define <16 x i8> @neg_and_two_v16i8(<16 x i8> %x) {
+; CHECK-LABEL: neg_and_two_v16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v1.16b, #2
+; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: neg v0.16b, v0.16b
+; CHECK-NEXT: ret
+ %and = and <16 x i8> %x, splat (i8 2)
+ %neg = sub <16 x i8> zeroinitializer, %and
+ ret <16 x i8> %neg
+}
+
+define <16 x i8> @sext_icmp_ne_and_one_v16i8(<16 x i8> %x) {
+; CHECK-LABEL: sext_icmp_ne_and_one_v16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v1.16b, #1
+; CHECK-NEXT: cmtst v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: ret
+ %and = and <16 x i8> %x, splat (i8 1)
+ %cmp = icmp ne <16 x i8> %and, zeroinitializer
+ %sext = sext <16 x i1> %cmp to <16 x i8>
+ ret <16 x i8> %sext
+}
+
+define <8 x i16> @neg_and_bitcast_splat_one_v8i16(<8 x i16> %x) {
+; CHECK-LABEL: neg_and_bitcast_splat_one_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v1.16b, #1
+; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: neg v0.8h, v0.8h
+; CHECK-NEXT: ret
+ %and = and <8 x i16> %x, bitcast (<16 x i8> splat (i8 1) to <8 x i16>)
+ %neg = sub <8 x i16> zeroinitializer, %and
+ ret <8 x i16> %neg
+}
+
+define <16 x i8> @neg_and_nonsplat_v16i8(<16 x i8> %x) {
+; CHECK-LABEL: neg_and_nonsplat_v16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, .LCPI8_0
+; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI8_0]
+; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT: neg v0.16b, v0.16b
+; CHECK-NEXT: ret
+ %and = and <16 x i8> %x, <i8 1, i8 0, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+ %neg = sub <16 x i8> zeroinitializer, %and
+ ret <16 x i8> %neg
+}
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