[llvm] [NVPTX] Add commutativity to SETP instructions to enable MachineCSE of inverted predicates (PR #191890)
via llvm-commits
llvm-commits at lists.llvm.org
Tue May 5 16:49:48 PDT 2026
https://github.com/modiking updated https://github.com/llvm/llvm-project/pull/191890
>From a849bfcc1cdb6182594ed0ac78691dc62c52298c Mon Sep 17 00:00:00 2001
From: root <mmo at nvidia.com>
Date: Mon, 13 Apr 2026 14:05:18 -0700
Subject: [PATCH 1/6] [NVPTX] Add commutativity to SETP instructions to enable
MachineCSE of inverted predicates
Inverted predicates can be used freely in PTX. If we can invert a
predicate and CSE the generating instruction we can save calculating
the inverse.
Teach the NVPTX commuteInstructionImpl that SETP instructions can be
inverted to allow CSEing with previous SETP that match the inverted
form. This also inverts the branch users of the predicate to maintain
correctness.
Currently only allow the SETP inversion if all users are branches.
Future work can extend this to sel and not instructions.
Made-with: Cursor
---
llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp | 166 +++++
llvm/lib/Target/NVPTX/NVPTXInstrInfo.h | 8 +
llvm/lib/Target/NVPTX/NVPTXInstrInfo.td | 7 +-
...achine-cse-predicate-inversion-bfloat16.ll | 695 ++++++++++++++++++
...machine-cse-predicate-inversion-float16.ll | 695 ++++++++++++++++++
...machine-cse-predicate-inversion-float32.ll | 663 +++++++++++++++++
...machine-cse-predicate-inversion-float64.ll | 679 +++++++++++++++++
.../machine-cse-predicate-inversion-int16.ll | 437 +++++++++++
.../machine-cse-predicate-inversion-int32.ll | 427 +++++++++++
.../machine-cse-predicate-inversion-int64.ll | 437 +++++++++++
...-cse-predicate-inversion-multiple-users.ll | 50 ++
...ne-cse-predicate-inversion-vector-float.ll | 100 +++
...ine-cse-predicate-no-inversion-bfloat16.ll | 224 ++++++
...hine-cse-predicate-no-inversion-float16.ll | 224 ++++++
...hine-cse-predicate-no-inversion-float32.ll | 214 ++++++
...hine-cse-predicate-no-inversion-float64.ll | 219 ++++++
...achine-cse-predicate-no-inversion-int16.ll | 224 ++++++
...achine-cse-predicate-no-inversion-int32.ll | 219 ++++++
...achine-cse-predicate-no-inversion-int64.ll | 224 ++++++
19 files changed, 5908 insertions(+), 4 deletions(-)
create mode 100644 llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-bfloat16.ll
create mode 100644 llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-float16.ll
create mode 100644 llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-float32.ll
create mode 100644 llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-float64.ll
create mode 100644 llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-int16.ll
create mode 100644 llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-int32.ll
create mode 100644 llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-int64.ll
create mode 100644 llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-multiple-users.ll
create mode 100644 llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-vector-float.ll
create mode 100644 llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-bfloat16.ll
create mode 100644 llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-float16.ll
create mode 100644 llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-float32.ll
create mode 100644 llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-float64.ll
create mode 100644 llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-int16.ll
create mode 100644 llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-int32.ll
create mode 100644 llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-int64.ll
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
index 8d33876b1f8ae..495dd2518bf4d 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
@@ -205,3 +205,169 @@ bool NVPTXInstrInfo::reverseBranchCondition(
Cond[1].setImm(!Cond[1].getImm());
return false;
}
+
+bool NVPTXInstrInfo::invertPredicateBranchInstr(MachineBasicBlock &MBB) const {
+ MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
+ SmallVector<MachineOperand, 4> Cond;
+ if (analyzeBranch(MBB, TBB, FBB, Cond, /*AllowModify=*/false))
+ return false;
+ if (Cond.empty())
+ return false;
+ if (reverseBranchCondition(Cond))
+ return false;
+ DebugLoc DL = MBB.findBranchDebugLoc();
+ removeBranch(MBB);
+ insertBranch(MBB, TBB, FBB, Cond, DL);
+ return true;
+}
+
+static bool isIntegerSetp(const MachineInstr &MI) {
+ switch (MI.getOpcode()) {
+ case NVPTX::SETP_i16rr:
+ case NVPTX::SETP_i16ri:
+ case NVPTX::SETP_i16ir:
+ case NVPTX::SETP_i32rr:
+ case NVPTX::SETP_i32ri:
+ case NVPTX::SETP_i32ir:
+ case NVPTX::SETP_i64rr:
+ case NVPTX::SETP_i64ri:
+ case NVPTX::SETP_i64ir:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool isScalarFloatSetp(const MachineInstr &MI) {
+ switch (MI.getOpcode()) {
+ case NVPTX::SETP_bf16rr:
+ case NVPTX::SETP_f16rr:
+ case NVPTX::SETP_f32rr:
+ case NVPTX::SETP_f32ri:
+ case NVPTX::SETP_f32ir:
+ case NVPTX::SETP_f64rr:
+ case NVPTX::SETP_f64ri:
+ case NVPTX::SETP_f64ir:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static int64_t invertIntegerCmpMode(int64_t Mode) {
+ switch (Mode) {
+ case NVPTX::PTXCmpMode::EQ:
+ return NVPTX::PTXCmpMode::NE;
+ case NVPTX::PTXCmpMode::NE:
+ return NVPTX::PTXCmpMode::EQ;
+ case NVPTX::PTXCmpMode::LT:
+ return NVPTX::PTXCmpMode::GE;
+ case NVPTX::PTXCmpMode::LE:
+ return NVPTX::PTXCmpMode::GT;
+ case NVPTX::PTXCmpMode::GT:
+ return NVPTX::PTXCmpMode::LE;
+ case NVPTX::PTXCmpMode::GE:
+ return NVPTX::PTXCmpMode::LT;
+ case NVPTX::PTXCmpMode::LTU:
+ return NVPTX::PTXCmpMode::GEU;
+ case NVPTX::PTXCmpMode::LEU:
+ return NVPTX::PTXCmpMode::GTU;
+ case NVPTX::PTXCmpMode::GTU:
+ return NVPTX::PTXCmpMode::LEU;
+ case NVPTX::PTXCmpMode::GEU:
+ return NVPTX::PTXCmpMode::LTU;
+ default:
+ llvm_unreachable("Invalid integer comparison mode");
+ }
+}
+
+static int64_t invertScalarFloatCmpMode(int64_t Mode) {
+ switch (Mode) {
+ case NVPTX::PTXCmpMode::EQ:
+ return NVPTX::PTXCmpMode::NEU;
+ case NVPTX::PTXCmpMode::NE:
+ return NVPTX::PTXCmpMode::EQU;
+ case NVPTX::PTXCmpMode::EQU:
+ return NVPTX::PTXCmpMode::NE;
+ case NVPTX::PTXCmpMode::NEU:
+ return NVPTX::PTXCmpMode::EQ;
+ case NVPTX::PTXCmpMode::LT:
+ return NVPTX::PTXCmpMode::GEU;
+ case NVPTX::PTXCmpMode::LE:
+ return NVPTX::PTXCmpMode::GTU;
+ case NVPTX::PTXCmpMode::GT:
+ return NVPTX::PTXCmpMode::LEU;
+ case NVPTX::PTXCmpMode::GE:
+ return NVPTX::PTXCmpMode::LTU;
+ case NVPTX::PTXCmpMode::LTU:
+ return NVPTX::PTXCmpMode::GE;
+ case NVPTX::PTXCmpMode::LEU:
+ return NVPTX::PTXCmpMode::GT;
+ case NVPTX::PTXCmpMode::GTU:
+ return NVPTX::PTXCmpMode::LE;
+ case NVPTX::PTXCmpMode::GEU:
+ return NVPTX::PTXCmpMode::LT;
+ case NVPTX::PTXCmpMode::NUM:
+ return NVPTX::PTXCmpMode::NotANumber;
+ case NVPTX::PTXCmpMode::NotANumber:
+ return NVPTX::PTXCmpMode::NUM;
+ default:
+ llvm_unreachable("Invalid scalar float comparison mode");
+ }
+}
+
+static void invertScalarCompareInstr(MachineInstr &MI) {
+ MachineOperand &ModeOp = MI.getOperand(3);
+
+ if (isIntegerSetp(MI))
+ ModeOp.setImm(invertIntegerCmpMode(ModeOp.getImm()));
+ else if (isScalarFloatSetp(MI))
+ ModeOp.setImm(invertScalarFloatCmpMode(ModeOp.getImm()));
+ else
+ llvm_unreachable("Invalid SETP instruction");
+}
+
+bool NVPTXInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
+ unsigned &SrcOpIdx1,
+ unsigned &SrcOpIdx2) const {
+ if (isIntegerSetp(MI) || isScalarFloatSetp(MI))
+ return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
+ return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
+}
+
+MachineInstr *NVPTXInstrInfo::commuteInstructionImpl(MachineInstr &MI,
+ bool NewMI,
+ unsigned OpIdx1,
+ unsigned OpIdx2) const {
+ assert(!NewMI && "this should never be used");
+
+ if (!isIntegerSetp(MI) && !isScalarFloatSetp(MI))
+ return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
+
+ invertScalarCompareInstr(MI);
+
+ // For now all users must be invertible conditional branches.
+ // TODO: Support other users such as selects.
+ bool AllInverted = true;
+ MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
+ for (MachineInstr &UseMI :
+ MRI.use_nodbg_instructions(MI.getOperand(0).getReg())) {
+ if (!(UseMI.isConditionalBranch() &&
+ invertPredicateBranchInstr(*UseMI.getParent()))) {
+ AllInverted = false;
+ break;
+ }
+ }
+
+ if (!AllInverted) {
+ for (MachineInstr &UseMI :
+ MRI.use_nodbg_instructions(MI.getOperand(0).getReg())) {
+ if (!(UseMI.isConditionalBranch() &&
+ invertPredicateBranchInstr(*UseMI.getParent())))
+ break;
+ }
+ invertScalarCompareInstr(MI);
+ return nullptr;
+ }
+ return &MI;
+}
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h
index c0b7e77cf63a5..957fcf5cae69a 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h
@@ -69,6 +69,14 @@ class NVPTXInstrInfo : public NVPTXGenInstrInfo {
int *BytesAdded = nullptr) const override;
bool
reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
+ bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
+ unsigned &SrcOpIdx2) const override;
+ MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
+ unsigned OpIdx1,
+ unsigned OpIdx2) const override;
+
+private:
+ bool invertPredicateBranchInstr(MachineBasicBlock &MBB) const;
};
} // namespace llvm
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
index 8b53cdf6c8798..e35a7e92cf31b 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
@@ -77,8 +77,7 @@ def FTZFlag : OperandWithDefaultOps<i1, (ops (getFTZFlag (i1 0)))> {
let PrintMethod = "printFTZFlag";
}
-// Flag to indicate predicate negation (@!p) for conditional branches.
-def BranchFlag : OperandWithDefaultOps<i1, (ops (i1 0))> {
+def BranchFlag : OperandWithDefaultOps<i32, (ops (i32 0))> {
let PrintMethod = "printNegatedPredicate";
}
@@ -1604,7 +1603,7 @@ multiclass FSETP<RegTyInfo t, bit allow_ftz = true> {
defvar ftz_str = !if(allow_ftz, "$ftz", "");
defvar op_str = "setp.${cmp:FCmp}" # ftz_str # "." # t.PtxType;
defvar flags = !con((ins CmpMode:$cmp), !if(allow_ftz, (ins FTZFlag:$ftz), (ins)));
- let hasSideEffects = false in {
+ let hasSideEffects = false, isCompare = 1, isCommutable = 1 in {
def rr :
BasicFlagsNVPTXInst<(outs B1:$dst), (ins t.RC:$a, t.RC:$b),
flags, op_str>;
@@ -1630,7 +1629,7 @@ multiclass FSETP<RegTyInfo t, bit allow_ftz = true> {
multiclass ISETP<RegTyInfo t> {
defvar op_str = "setp.${cmp:ICmp}.${cmp:IType}" # t.Size;
- let hasSideEffects = false in {
+ let hasSideEffects = false, isCompare = 1, isCommutable = 1 in {
def rr :
BasicFlagsNVPTXInst<(outs B1:$dst), (ins t.RC:$a, t.RC:$b),
(ins CmpMode:$cmp), op_str>;
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-bfloat16.ll b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-bfloat16.ll
new file mode 100644
index 0000000000000..b6b77e9c09108
--- /dev/null
+++ b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-bfloat16.ll
@@ -0,0 +1,695 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -march=nvptx64 -mcpu=sm_100 -O2 < %s | FileCheck %s
+; RUN: %if ptxas-sm_100 %{ llc < %s -march=nvptx64 -mcpu=sm_100 -O2 | %ptxas-verify -arch=sm_100 %}
+
+target triple = "nvptx64-nvidia-cuda"
+
+define i32 @test_bfloat16_eq(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_eq(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_eq_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_eq_param_0];
+; CHECK-NEXT: setp.eq.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB0_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB0_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB0_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB0_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oeq bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp une bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_ne(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_ne(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ne_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ne_param_0];
+; CHECK-NEXT: setp.ne.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB1_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB1_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB1_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB1_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp one bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ueq bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_oeq(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_oeq(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_oeq_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_oeq_param_0];
+; CHECK-NEXT: setp.eq.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB2_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB2_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB2_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB2_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oeq bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp une bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_one(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_one(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_one_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_one_param_0];
+; CHECK-NEXT: setp.ne.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB3_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB3_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB3_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB3_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp one bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ueq bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_ueq(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_ueq(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ueq_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ueq_param_0];
+; CHECK-NEXT: setp.equ.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB4_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB4_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB4_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB4_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ueq bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp one bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_une(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_une(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_une_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_une_param_0];
+; CHECK-NEXT: setp.neu.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB5_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB5_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB5_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB5_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp une bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp oeq bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_olt(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_olt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_olt_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_olt_param_0];
+; CHECK-NEXT: setp.lt.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB6_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB6_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB6_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB6_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp olt bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp uge bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_ole(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_ole(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ole_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ole_param_0];
+; CHECK-NEXT: setp.le.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB7_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB7_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB7_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB7_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ole bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ugt bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_ogt(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_ogt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ogt_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ogt_param_0];
+; CHECK-NEXT: setp.gt.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB8_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB8_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB8_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB8_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ogt bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ule bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_oge(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_oge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_oge_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_oge_param_0];
+; CHECK-NEXT: setp.ge.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB9_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB9_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB9_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB9_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oge bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ult bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_ult(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_ult(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ult_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ult_param_0];
+; CHECK-NEXT: setp.ltu.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB10_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB10_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB10_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB10_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ult bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp oge bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_ule(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_ule(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ule_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ule_param_0];
+; CHECK-NEXT: setp.leu.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB11_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB11_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB11_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB11_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ule bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ogt bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_ugt(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_ugt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ugt_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ugt_param_0];
+; CHECK-NEXT: setp.gtu.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB12_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB12_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB12_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB12_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ugt bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ole bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_uge(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_uge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_uge_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_uge_param_0];
+; CHECK-NEXT: setp.geu.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB13_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB13_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB13_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB13_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp uge bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp olt bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_ord(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_ord(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ord_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ord_param_0];
+; CHECK-NEXT: setp.num.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @!%p1 bra $L__BB14_1;
+; CHECK-NEXT: $L__BB14_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB14_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB14_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+; CHECK-NEXT: $L__BB14_1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: bra.uni $L__BB14_2;
+entry:
+ %cmp = fcmp ord bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp uno bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_uno(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_uno(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_uno_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_uno_param_0];
+; CHECK-NEXT: setp.nan.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB15_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB15_2: // %merge1
+; CHECK-NEXT: @%p1 bra $L__BB15_3;
+; CHECK-NEXT: $L__BB15_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+; CHECK-NEXT: $L__BB15_3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: bra.uni $L__BB15_4;
+entry:
+ %cmp = fcmp uno bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ord bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-float16.ll b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-float16.ll
new file mode 100644
index 0000000000000..42aa05da4c76a
--- /dev/null
+++ b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-float16.ll
@@ -0,0 +1,695 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -march=nvptx64 -mcpu=sm_100 -O2 < %s | FileCheck %s
+; RUN: %if ptxas-sm_100 %{ llc < %s -march=nvptx64 -mcpu=sm_100 -O2 | %ptxas-verify -arch=sm_100 %}
+
+target triple = "nvptx64-nvidia-cuda"
+
+define i32 @test_float16_eq(half %a, half %b) {
+; CHECK-LABEL: test_float16_eq(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_eq_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_eq_param_0];
+; CHECK-NEXT: setp.eq.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB0_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB0_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB0_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB0_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oeq half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp une half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_ne(half %a, half %b) {
+; CHECK-LABEL: test_float16_ne(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ne_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ne_param_0];
+; CHECK-NEXT: setp.ne.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB1_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB1_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB1_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB1_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp one half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ueq half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_oeq(half %a, half %b) {
+; CHECK-LABEL: test_float16_oeq(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_oeq_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_oeq_param_0];
+; CHECK-NEXT: setp.eq.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB2_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB2_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB2_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB2_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oeq half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp une half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_one(half %a, half %b) {
+; CHECK-LABEL: test_float16_one(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_one_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_one_param_0];
+; CHECK-NEXT: setp.ne.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB3_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB3_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB3_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB3_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp one half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ueq half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_ueq(half %a, half %b) {
+; CHECK-LABEL: test_float16_ueq(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ueq_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ueq_param_0];
+; CHECK-NEXT: setp.equ.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB4_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB4_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB4_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB4_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ueq half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp one half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_une(half %a, half %b) {
+; CHECK-LABEL: test_float16_une(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_une_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_une_param_0];
+; CHECK-NEXT: setp.neu.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB5_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB5_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB5_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB5_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp une half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp oeq half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_olt(half %a, half %b) {
+; CHECK-LABEL: test_float16_olt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_olt_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_olt_param_0];
+; CHECK-NEXT: setp.lt.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB6_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB6_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB6_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB6_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp olt half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp uge half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_ole(half %a, half %b) {
+; CHECK-LABEL: test_float16_ole(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ole_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ole_param_0];
+; CHECK-NEXT: setp.le.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB7_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB7_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB7_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB7_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ole half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ugt half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_ogt(half %a, half %b) {
+; CHECK-LABEL: test_float16_ogt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ogt_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ogt_param_0];
+; CHECK-NEXT: setp.gt.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB8_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB8_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB8_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB8_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ogt half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ule half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_oge(half %a, half %b) {
+; CHECK-LABEL: test_float16_oge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_oge_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_oge_param_0];
+; CHECK-NEXT: setp.ge.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB9_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB9_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB9_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB9_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oge half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ult half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_ult(half %a, half %b) {
+; CHECK-LABEL: test_float16_ult(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ult_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ult_param_0];
+; CHECK-NEXT: setp.ltu.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB10_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB10_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB10_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB10_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ult half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp oge half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_ule(half %a, half %b) {
+; CHECK-LABEL: test_float16_ule(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ule_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ule_param_0];
+; CHECK-NEXT: setp.leu.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB11_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB11_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB11_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB11_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ule half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ogt half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_ugt(half %a, half %b) {
+; CHECK-LABEL: test_float16_ugt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ugt_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ugt_param_0];
+; CHECK-NEXT: setp.gtu.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB12_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB12_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB12_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB12_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ugt half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ole half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_uge(half %a, half %b) {
+; CHECK-LABEL: test_float16_uge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_uge_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_uge_param_0];
+; CHECK-NEXT: setp.geu.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB13_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB13_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB13_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB13_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp uge half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp olt half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_ord(half %a, half %b) {
+; CHECK-LABEL: test_float16_ord(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ord_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ord_param_0];
+; CHECK-NEXT: setp.num.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @!%p1 bra $L__BB14_1;
+; CHECK-NEXT: $L__BB14_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB14_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB14_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+; CHECK-NEXT: $L__BB14_1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: bra.uni $L__BB14_2;
+entry:
+ %cmp = fcmp ord half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp uno half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_uno(half %a, half %b) {
+; CHECK-LABEL: test_float16_uno(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_uno_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_uno_param_0];
+; CHECK-NEXT: setp.nan.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB15_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB15_2: // %merge1
+; CHECK-NEXT: @%p1 bra $L__BB15_3;
+; CHECK-NEXT: $L__BB15_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+; CHECK-NEXT: $L__BB15_3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: bra.uni $L__BB15_4;
+entry:
+ %cmp = fcmp uno half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ord half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-float32.ll b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-float32.ll
new file mode 100644
index 0000000000000..a034ef25aea11
--- /dev/null
+++ b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-float32.ll
@@ -0,0 +1,663 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -march=nvptx64 -mcpu=sm_100 -O2 < %s | FileCheck %s
+; RUN: %if ptxas-sm_100 %{ llc < %s -march=nvptx64 -mcpu=sm_100 -O2 | %ptxas-verify -arch=sm_100 %}
+
+target triple = "nvptx64-nvidia-cuda"
+
+define i32 @test_float32_eq(float %arg) {
+; CHECK-LABEL: test_float32_eq(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_eq_param_0];
+; CHECK-NEXT: setp.eq.f32 %p1, %r1, 0f00000000;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB0_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB0_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB0_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB0_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oeq float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp une float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_ne(float %arg) {
+; CHECK-LABEL: test_float32_ne(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ne_param_0];
+; CHECK-NEXT: setp.ne.f32 %p1, %r1, 0f00000000;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB1_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB1_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB1_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB1_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp one float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ueq float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_oeq(float %arg) {
+; CHECK-LABEL: test_float32_oeq(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_oeq_param_0];
+; CHECK-NEXT: setp.eq.f32 %p1, %r1, 0f00000000;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB2_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB2_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB2_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB2_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oeq float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp une float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_one(float %arg) {
+; CHECK-LABEL: test_float32_one(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_one_param_0];
+; CHECK-NEXT: setp.ne.f32 %p1, %r1, 0f00000000;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB3_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB3_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB3_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB3_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp one float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ueq float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_ueq(float %arg) {
+; CHECK-LABEL: test_float32_ueq(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ueq_param_0];
+; CHECK-NEXT: setp.equ.f32 %p1, %r1, 0f00000000;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB4_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB4_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB4_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB4_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ueq float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp one float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_une(float %arg) {
+; CHECK-LABEL: test_float32_une(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_une_param_0];
+; CHECK-NEXT: setp.neu.f32 %p1, %r1, 0f00000000;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB5_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB5_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB5_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB5_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp une float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp oeq float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_olt(float %arg) {
+; CHECK-LABEL: test_float32_olt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_olt_param_0];
+; CHECK-NEXT: setp.lt.f32 %p1, %r1, 0f00000000;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB6_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB6_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB6_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB6_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp olt float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp uge float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_ole(float %arg) {
+; CHECK-LABEL: test_float32_ole(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ole_param_0];
+; CHECK-NEXT: setp.le.f32 %p1, %r1, 0f00000000;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB7_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB7_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB7_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB7_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ole float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ugt float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_ogt(float %arg) {
+; CHECK-LABEL: test_float32_ogt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ogt_param_0];
+; CHECK-NEXT: setp.gt.f32 %p1, %r1, 0f00000000;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB8_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB8_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB8_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB8_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ogt float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ule float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_oge(float %arg) {
+; CHECK-LABEL: test_float32_oge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_oge_param_0];
+; CHECK-NEXT: setp.ge.f32 %p1, %r1, 0f00000000;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB9_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB9_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB9_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB9_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oge float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ult float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_ult(float %arg) {
+; CHECK-LABEL: test_float32_ult(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ult_param_0];
+; CHECK-NEXT: setp.ltu.f32 %p1, %r1, 0f00000000;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB10_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB10_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB10_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB10_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ult float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp oge float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_ule(float %arg) {
+; CHECK-LABEL: test_float32_ule(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ule_param_0];
+; CHECK-NEXT: setp.leu.f32 %p1, %r1, 0f00000000;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB11_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB11_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB11_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB11_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ule float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ogt float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_ugt(float %arg) {
+; CHECK-LABEL: test_float32_ugt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ugt_param_0];
+; CHECK-NEXT: setp.gtu.f32 %p1, %r1, 0f00000000;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB12_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB12_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB12_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB12_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ugt float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ole float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_uge(float %arg) {
+; CHECK-LABEL: test_float32_uge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_uge_param_0];
+; CHECK-NEXT: setp.geu.f32 %p1, %r1, 0f00000000;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB13_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB13_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB13_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB13_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp uge float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp olt float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_ord(float %arg) {
+; CHECK-LABEL: test_float32_ord(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ord_param_0];
+; CHECK-NEXT: setp.num.f32 %p1, %r1, %r1;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @!%p1 bra $L__BB14_1;
+; CHECK-NEXT: $L__BB14_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB14_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB14_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+; CHECK-NEXT: $L__BB14_1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: bra.uni $L__BB14_2;
+entry:
+ %cmp = fcmp ord float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp uno float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_uno(float %arg) {
+; CHECK-LABEL: test_float32_uno(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_uno_param_0];
+; CHECK-NEXT: setp.nan.f32 %p1, %r1, %r1;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB15_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB15_2: // %merge1
+; CHECK-NEXT: @%p1 bra $L__BB15_3;
+; CHECK-NEXT: $L__BB15_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+; CHECK-NEXT: $L__BB15_3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: bra.uni $L__BB15_4;
+entry:
+ %cmp = fcmp uno float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ord float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-float64.ll b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-float64.ll
new file mode 100644
index 0000000000000..4106d7b9a9184
--- /dev/null
+++ b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-float64.ll
@@ -0,0 +1,679 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -march=nvptx64 -mcpu=sm_100 -O2 < %s | FileCheck %s
+; RUN: %if ptxas-sm_100 %{ llc < %s -march=nvptx64 -mcpu=sm_100 -O2 | %ptxas-verify -arch=sm_100 %}
+
+target triple = "nvptx64-nvidia-cuda"
+
+define i32 @test_float64_eq(double %arg) {
+; CHECK-LABEL: test_float64_eq(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_eq_param_0];
+; CHECK-NEXT: setp.eq.f64 %p1, %rd1, 0d0000000000000000;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB0_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB0_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB0_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB0_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oeq double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp une double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_ne(double %arg) {
+; CHECK-LABEL: test_float64_ne(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ne_param_0];
+; CHECK-NEXT: setp.ne.f64 %p1, %rd1, 0d0000000000000000;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB1_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB1_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB1_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB1_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp one double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ueq double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_oeq(double %arg) {
+; CHECK-LABEL: test_float64_oeq(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_oeq_param_0];
+; CHECK-NEXT: setp.eq.f64 %p1, %rd1, 0d0000000000000000;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB2_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB2_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB2_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB2_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oeq double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp une double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_one(double %arg) {
+; CHECK-LABEL: test_float64_one(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_one_param_0];
+; CHECK-NEXT: setp.ne.f64 %p1, %rd1, 0d0000000000000000;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB3_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB3_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB3_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB3_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp one double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ueq double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_ueq(double %arg) {
+; CHECK-LABEL: test_float64_ueq(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ueq_param_0];
+; CHECK-NEXT: setp.equ.f64 %p1, %rd1, 0d0000000000000000;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB4_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB4_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB4_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB4_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ueq double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp one double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_une(double %arg) {
+; CHECK-LABEL: test_float64_une(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_une_param_0];
+; CHECK-NEXT: setp.neu.f64 %p1, %rd1, 0d0000000000000000;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB5_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB5_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB5_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB5_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp une double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp oeq double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_olt(double %arg) {
+; CHECK-LABEL: test_float64_olt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_olt_param_0];
+; CHECK-NEXT: setp.lt.f64 %p1, %rd1, 0d0000000000000000;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB6_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB6_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB6_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB6_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp olt double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp uge double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_ole(double %arg) {
+; CHECK-LABEL: test_float64_ole(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ole_param_0];
+; CHECK-NEXT: setp.le.f64 %p1, %rd1, 0d0000000000000000;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB7_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB7_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB7_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB7_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ole double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ugt double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_ogt(double %arg) {
+; CHECK-LABEL: test_float64_ogt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ogt_param_0];
+; CHECK-NEXT: setp.gt.f64 %p1, %rd1, 0d0000000000000000;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB8_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB8_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB8_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB8_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ogt double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ule double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_oge(double %arg) {
+; CHECK-LABEL: test_float64_oge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_oge_param_0];
+; CHECK-NEXT: setp.ge.f64 %p1, %rd1, 0d0000000000000000;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB9_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB9_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB9_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB9_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oge double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ult double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_ult(double %arg) {
+; CHECK-LABEL: test_float64_ult(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ult_param_0];
+; CHECK-NEXT: setp.ltu.f64 %p1, %rd1, 0d0000000000000000;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB10_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB10_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB10_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB10_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ult double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp oge double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_ule(double %arg) {
+; CHECK-LABEL: test_float64_ule(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ule_param_0];
+; CHECK-NEXT: setp.leu.f64 %p1, %rd1, 0d0000000000000000;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB11_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB11_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB11_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB11_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ule double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ogt double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_ugt(double %arg) {
+; CHECK-LABEL: test_float64_ugt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ugt_param_0];
+; CHECK-NEXT: setp.gtu.f64 %p1, %rd1, 0d0000000000000000;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB12_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB12_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB12_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB12_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ugt double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ole double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_uge(double %arg) {
+; CHECK-LABEL: test_float64_uge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_uge_param_0];
+; CHECK-NEXT: setp.geu.f64 %p1, %rd1, 0d0000000000000000;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB13_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB13_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB13_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB13_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp uge double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp olt double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_ord(double %arg) {
+; CHECK-LABEL: test_float64_ord(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ord_param_0];
+; CHECK-NEXT: setp.num.f64 %p1, %rd1, %rd1;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @!%p1 bra $L__BB14_1;
+; CHECK-NEXT: $L__BB14_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB14_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB14_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+; CHECK-NEXT: $L__BB14_1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: bra.uni $L__BB14_2;
+entry:
+ %cmp = fcmp ord double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp uno double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_uno(double %arg) {
+; CHECK-LABEL: test_float64_uno(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_uno_param_0];
+; CHECK-NEXT: setp.nan.f64 %p1, %rd1, %rd1;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB15_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB15_2: // %merge1
+; CHECK-NEXT: @%p1 bra $L__BB15_3;
+; CHECK-NEXT: $L__BB15_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+; CHECK-NEXT: $L__BB15_3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: bra.uni $L__BB15_4;
+entry:
+ %cmp = fcmp uno double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ord double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-int16.ll b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-int16.ll
new file mode 100644
index 0000000000000..2cb3fa6110c18
--- /dev/null
+++ b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-int16.ll
@@ -0,0 +1,437 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -march=nvptx64 -mcpu=sm_100 -O2 < %s | FileCheck %s
+; RUN: %if ptxas-sm_100 %{ llc < %s -march=nvptx64 -mcpu=sm_100 -O2 | %ptxas-verify -arch=sm_100 %}
+
+target triple = "nvptx64-nvidia-cuda"
+
+; Test int16 integer comparison inversions
+
+define i32 @test_int16_eq(i16 %a, i16 %b) {
+; CHECK-LABEL: test_int16_eq(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_eq_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_eq_param_0];
+; CHECK-NEXT: setp.eq.b16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB0_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB0_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB0_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB0_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp eq i16 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp ne i16 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int16_ne(i16 %a, i16 %b) {
+; CHECK-LABEL: test_int16_ne(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_ne_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_ne_param_0];
+; CHECK-NEXT: setp.ne.b16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB1_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB1_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB1_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB1_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp ne i16 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp eq i16 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int16_slt(i16 %a, i16 %b) {
+; CHECK-LABEL: test_int16_slt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_slt_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_slt_param_0];
+; CHECK-NEXT: setp.lt.s16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB2_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB2_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB2_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB2_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp slt i16 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp sge i16 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int16_sle(i16 %a, i16 %b) {
+; CHECK-LABEL: test_int16_sle(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_sle_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_sle_param_0];
+; CHECK-NEXT: setp.le.s16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB3_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB3_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB3_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB3_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp sle i16 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp sgt i16 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int16_sgt(i16 %a, i16 %b) {
+; CHECK-LABEL: test_int16_sgt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_sgt_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_sgt_param_0];
+; CHECK-NEXT: setp.gt.s16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB4_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB4_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB4_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB4_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp sgt i16 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp sle i16 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int16_sge(i16 %a, i16 %b) {
+; CHECK-LABEL: test_int16_sge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_sge_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_sge_param_0];
+; CHECK-NEXT: setp.ge.s16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB5_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB5_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB5_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB5_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp sge i16 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp slt i16 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int16_ult(i16 %a, i16 %b) {
+; CHECK-LABEL: test_int16_ult(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_ult_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_ult_param_0];
+; CHECK-NEXT: setp.lt.u16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB6_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB6_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB6_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB6_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp ult i16 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp uge i16 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int16_ule(i16 %a, i16 %b) {
+; CHECK-LABEL: test_int16_ule(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_ule_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_ule_param_0];
+; CHECK-NEXT: setp.le.u16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB7_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB7_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB7_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB7_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp ule i16 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp ugt i16 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int16_ugt(i16 %a, i16 %b) {
+; CHECK-LABEL: test_int16_ugt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_ugt_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_ugt_param_0];
+; CHECK-NEXT: setp.gt.u16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB8_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB8_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB8_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB8_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp ugt i16 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp ule i16 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int16_uge(i16 %a, i16 %b) {
+; CHECK-LABEL: test_int16_uge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_uge_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_uge_param_0];
+; CHECK-NEXT: setp.ge.u16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB9_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB9_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB9_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB9_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp uge i16 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp ult i16 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-int32.ll b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-int32.ll
new file mode 100644
index 0000000000000..4d1f7c97fe594
--- /dev/null
+++ b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-int32.ll
@@ -0,0 +1,427 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -march=nvptx64 -mcpu=sm_100 -O2 < %s | FileCheck %s
+; RUN: %if ptxas-sm_100 %{ llc < %s -march=nvptx64 -mcpu=sm_100 -O2 | %ptxas-verify -arch=sm_100 %}
+
+target triple = "nvptx64-nvidia-cuda"
+
+; Test int32 integer comparison inversions
+
+define i32 @test_int32_eq(i32 %a, i32 %b) {
+; CHECK-LABEL: test_int32_eq(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r2, [test_int32_eq_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_int32_eq_param_0];
+; CHECK-NEXT: setp.eq.b32 %p1, %r1, %r2;
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: @%p1 bra $L__BB0_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r3, 1;
+; CHECK-NEXT: $L__BB0_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB0_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: $L__BB0_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp eq i32 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp ne i32 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int32_ne(i32 %a, i32 %b) {
+; CHECK-LABEL: test_int32_ne(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r2, [test_int32_ne_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_int32_ne_param_0];
+; CHECK-NEXT: setp.ne.b32 %p1, %r1, %r2;
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: @%p1 bra $L__BB1_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r3, 1;
+; CHECK-NEXT: $L__BB1_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB1_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: $L__BB1_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp ne i32 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp eq i32 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int32_slt(i32 %a, i32 %b) {
+; CHECK-LABEL: test_int32_slt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r2, [test_int32_slt_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_int32_slt_param_0];
+; CHECK-NEXT: setp.lt.s32 %p1, %r1, %r2;
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: @%p1 bra $L__BB2_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r3, 1;
+; CHECK-NEXT: $L__BB2_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB2_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: $L__BB2_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp slt i32 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp sge i32 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int32_sle(i32 %a, i32 %b) {
+; CHECK-LABEL: test_int32_sle(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r2, [test_int32_sle_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_int32_sle_param_0];
+; CHECK-NEXT: setp.le.s32 %p1, %r1, %r2;
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: @%p1 bra $L__BB3_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r3, 1;
+; CHECK-NEXT: $L__BB3_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB3_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: $L__BB3_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp sle i32 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp sgt i32 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int32_sgt(i32 %a, i32 %b) {
+; CHECK-LABEL: test_int32_sgt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r2, [test_int32_sgt_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_int32_sgt_param_0];
+; CHECK-NEXT: setp.gt.s32 %p1, %r1, %r2;
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: @%p1 bra $L__BB4_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r3, 1;
+; CHECK-NEXT: $L__BB4_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB4_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: $L__BB4_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp sgt i32 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp sle i32 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int32_sge(i32 %a, i32 %b) {
+; CHECK-LABEL: test_int32_sge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r2, [test_int32_sge_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_int32_sge_param_0];
+; CHECK-NEXT: setp.ge.s32 %p1, %r1, %r2;
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: @%p1 bra $L__BB5_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r3, 1;
+; CHECK-NEXT: $L__BB5_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB5_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: $L__BB5_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp sge i32 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp slt i32 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int32_ult(i32 %a, i32 %b) {
+; CHECK-LABEL: test_int32_ult(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r2, [test_int32_ult_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_int32_ult_param_0];
+; CHECK-NEXT: setp.lt.u32 %p1, %r1, %r2;
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: @%p1 bra $L__BB6_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r3, 1;
+; CHECK-NEXT: $L__BB6_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB6_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: $L__BB6_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp ult i32 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp uge i32 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int32_ule(i32 %a, i32 %b) {
+; CHECK-LABEL: test_int32_ule(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r2, [test_int32_ule_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_int32_ule_param_0];
+; CHECK-NEXT: setp.le.u32 %p1, %r1, %r2;
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: @%p1 bra $L__BB7_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r3, 1;
+; CHECK-NEXT: $L__BB7_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB7_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: $L__BB7_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp ule i32 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp ugt i32 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int32_ugt(i32 %a, i32 %b) {
+; CHECK-LABEL: test_int32_ugt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r2, [test_int32_ugt_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_int32_ugt_param_0];
+; CHECK-NEXT: setp.gt.u32 %p1, %r1, %r2;
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: @%p1 bra $L__BB8_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r3, 1;
+; CHECK-NEXT: $L__BB8_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB8_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: $L__BB8_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp ugt i32 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp ule i32 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int32_uge(i32 %a, i32 %b) {
+; CHECK-LABEL: test_int32_uge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r2, [test_int32_uge_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_int32_uge_param_0];
+; CHECK-NEXT: setp.ge.u32 %p1, %r1, %r2;
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: @%p1 bra $L__BB9_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r3, 1;
+; CHECK-NEXT: $L__BB9_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB9_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: $L__BB9_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp uge i32 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp ult i32 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-int64.ll b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-int64.ll
new file mode 100644
index 0000000000000..bc90ea4335d2e
--- /dev/null
+++ b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-int64.ll
@@ -0,0 +1,437 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -march=nvptx64 -mcpu=sm_100 -O2 < %s | FileCheck %s
+; RUN: %if ptxas-sm_100 %{ llc < %s -march=nvptx64 -mcpu=sm_100 -O2 | %ptxas-verify -arch=sm_100 %}
+
+target triple = "nvptx64-nvidia-cuda"
+
+; Test int64 integer comparison inversions
+
+define i32 @test_int64_eq(i64 %a, i64 %b) {
+; CHECK-LABEL: test_int64_eq(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_eq_param_1];
+; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_eq_param_0];
+; CHECK-NEXT: setp.eq.b64 %p1, %rd1, %rd2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB0_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB0_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB0_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB0_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp eq i64 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp ne i64 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int64_ne(i64 %a, i64 %b) {
+; CHECK-LABEL: test_int64_ne(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_ne_param_1];
+; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_ne_param_0];
+; CHECK-NEXT: setp.ne.b64 %p1, %rd1, %rd2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB1_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB1_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB1_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB1_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp ne i64 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp eq i64 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int64_slt(i64 %a, i64 %b) {
+; CHECK-LABEL: test_int64_slt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_slt_param_1];
+; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_slt_param_0];
+; CHECK-NEXT: setp.lt.s64 %p1, %rd1, %rd2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB2_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB2_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB2_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB2_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp slt i64 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp sge i64 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int64_sle(i64 %a, i64 %b) {
+; CHECK-LABEL: test_int64_sle(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_sle_param_1];
+; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_sle_param_0];
+; CHECK-NEXT: setp.le.s64 %p1, %rd1, %rd2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB3_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB3_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB3_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB3_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp sle i64 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp sgt i64 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int64_sgt(i64 %a, i64 %b) {
+; CHECK-LABEL: test_int64_sgt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_sgt_param_1];
+; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_sgt_param_0];
+; CHECK-NEXT: setp.gt.s64 %p1, %rd1, %rd2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB4_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB4_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB4_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB4_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp sgt i64 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp sle i64 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int64_sge(i64 %a, i64 %b) {
+; CHECK-LABEL: test_int64_sge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_sge_param_1];
+; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_sge_param_0];
+; CHECK-NEXT: setp.ge.s64 %p1, %rd1, %rd2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB5_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB5_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB5_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB5_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp sge i64 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp slt i64 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int64_ult(i64 %a, i64 %b) {
+; CHECK-LABEL: test_int64_ult(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_ult_param_1];
+; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_ult_param_0];
+; CHECK-NEXT: setp.lt.u64 %p1, %rd1, %rd2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB6_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB6_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB6_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB6_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp ult i64 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp uge i64 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int64_ule(i64 %a, i64 %b) {
+; CHECK-LABEL: test_int64_ule(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_ule_param_1];
+; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_ule_param_0];
+; CHECK-NEXT: setp.le.u64 %p1, %rd1, %rd2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB7_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB7_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB7_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB7_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp ule i64 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp ugt i64 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int64_ugt(i64 %a, i64 %b) {
+; CHECK-LABEL: test_int64_ugt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_ugt_param_1];
+; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_ugt_param_0];
+; CHECK-NEXT: setp.gt.u64 %p1, %rd1, %rd2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB8_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB8_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB8_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB8_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp ugt i64 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp ule i64 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int64_uge(i64 %a, i64 %b) {
+; CHECK-LABEL: test_int64_uge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_uge_param_1];
+; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_uge_param_0];
+; CHECK-NEXT: setp.ge.u64 %p1, %rd1, %rd2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB9_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB9_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB9_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB9_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp uge i64 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp ult i64 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-multiple-users.ll b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-multiple-users.ll
new file mode 100644
index 0000000000000..bf4a77f599061
--- /dev/null
+++ b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-multiple-users.ll
@@ -0,0 +1,50 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -march=nvptx64 -mcpu=sm_100 -O2 < %s | FileCheck %s
+; RUN: %if ptxas-sm_100 %{ llc < %s -march=nvptx64 -mcpu=sm_100 -O2 | %ptxas-verify -arch=sm_100 %}
+
+target triple = "nvptx64-nvidia-cuda"
+
+define i32 @test_multiple_users(i32 %a, i32 %b) {
+; CHECK-LABEL: test_multiple_users(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<6>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r3, [test_multiple_users_param_1];
+; CHECK-NEXT: ld.param.b32 %r2, [test_multiple_users_param_0];
+; CHECK-NEXT: setp.eq.b32 %p1, %r2, %r3;
+; CHECK-NEXT: mov.b32 %r5, 0;
+; CHECK-NEXT: @%p1 bra $L__BB0_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r5, 1;
+; CHECK-NEXT: $L__BB0_2: // %merge1
+; CHECK-NEXT: selp.b32 %r1, 1, 0, %p1;
+; CHECK-NEXT: @!%p1 bra $L__BB0_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r5, 0;
+; CHECK-NEXT: $L__BB0_4: // %merge2
+; CHECK-NEXT: add.s32 %r4, %r5, %r1;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp eq i32 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %val = select i1 %cmp, i32 1, i32 0
+ br i1 %cmp, label %else, label %merge2
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ %ret = add i32 %phi2, %val
+ ret i32 %ret
+}
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-vector-float.ll b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-vector-float.ll
new file mode 100644
index 0000000000000..85df5da09a0e7
--- /dev/null
+++ b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-vector-float.ll
@@ -0,0 +1,100 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -march=nvptx64 -mcpu=sm_100 -O2 < %s | FileCheck %s
+; RUN: %if ptxas-sm_100 %{ llc < %s -march=nvptx64 -mcpu=sm_100 -O2 | %ptxas-verify -arch=sm_100 %}
+
+; NOTE: Currently only scalar SETP predicate inversions are optimized by MachineCSE.
+target triple = "nvptx64-nvidia-cuda"
+
+define i32 @test_float_f16x2_eq(i32 %arg) {
+; CHECK-LABEL: test_float_f16x2_eq(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<5>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float_f16x2_eq_param_0];
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: setp.eq.f16x2 %p2|%p3, %r1, %r2;
+; CHECK-NEXT: and.pred %p1, %p2, %p3;
+; CHECK-NEXT: @%p1 bra $L__BB0_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB0_2: // %merge1
+; CHECK-NEXT: not.pred %p4, %p1;
+; CHECK-NEXT: @%p4 bra $L__BB0_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB0_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %a = bitcast i32 %arg to <2 x half>
+ %zero = bitcast i32 0 to <2 x half>
+ %cmp = fcmp oeq <2 x half> %a, %zero
+ %e0 = extractelement <2 x i1> %cmp, i32 0
+ %e1 = extractelement <2 x i1> %cmp, i32 1
+ %and = and i1 %e0, %e1
+ br i1 %and, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ br i1 %and, label %else, label %merge2
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float_bf16x2_eq(i32 %arg) {
+; CHECK-LABEL: test_float_bf16x2_eq(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<5>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float_bf16x2_eq_param_0];
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: setp.eq.bf16x2 %p2|%p3, %r1, %r2;
+; CHECK-NEXT: and.pred %p1, %p2, %p3;
+; CHECK-NEXT: @%p1 bra $L__BB1_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB1_2: // %merge1
+; CHECK-NEXT: not.pred %p4, %p1;
+; CHECK-NEXT: @%p4 bra $L__BB1_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB1_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %a = bitcast i32 %arg to <2 x bfloat>
+ %zero = bitcast i32 0 to <2 x bfloat>
+ %cmp = fcmp oeq <2 x bfloat> %a, %zero
+ %e0 = extractelement <2 x i1> %cmp, i32 0
+ %e1 = extractelement <2 x i1> %cmp, i32 1
+ %and = and i1 %e0, %e1
+ br i1 %and, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ br i1 %and, label %else, label %merge2
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-bfloat16.ll b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-bfloat16.ll
new file mode 100644
index 0000000000000..9e966e1843811
--- /dev/null
+++ b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-bfloat16.ll
@@ -0,0 +1,224 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -march=nvptx64 -mcpu=sm_100 -O2 < %s | FileCheck %s
+
+target triple = "nvptx64-nvidia-cuda"
+
+define i32 @test_bfloat16_ueq_vs_une(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_ueq_vs_une(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ueq_vs_une_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ueq_vs_une_param_0];
+; CHECK-NEXT: setp.equ.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB0_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB0_2: // %merge1
+; CHECK-NEXT: setp.neu.bf16 %p2, %rs1, %rs2;
+; CHECK-NEXT: @%p2 bra $L__BB0_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB0_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ueq bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp une bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_oeq_vs_one(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_oeq_vs_one(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_oeq_vs_one_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_oeq_vs_one_param_0];
+; CHECK-NEXT: setp.eq.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB1_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB1_2: // %merge1
+; CHECK-NEXT: setp.ne.bf16 %p2, %rs1, %rs2;
+; CHECK-NEXT: @%p2 bra $L__BB1_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB1_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oeq bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp one bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_olt_vs_ogt(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_olt_vs_ogt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_olt_vs_ogt_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_olt_vs_ogt_param_0];
+; CHECK-NEXT: setp.lt.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB2_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB2_2: // %merge1
+; CHECK-NEXT: setp.gt.bf16 %p2, %rs1, %rs2;
+; CHECK-NEXT: @%p2 bra $L__BB2_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB2_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp olt bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ogt bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_ult_vs_ugt(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_ult_vs_ugt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ult_vs_ugt_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ult_vs_ugt_param_0];
+; CHECK-NEXT: setp.ltu.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB3_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB3_2: // %merge1
+; CHECK-NEXT: setp.gtu.bf16 %p2, %rs1, %rs2;
+; CHECK-NEXT: @%p2 bra $L__BB3_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB3_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ult bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ugt bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_oeq_vs_olt(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_oeq_vs_olt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_oeq_vs_olt_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_oeq_vs_olt_param_0];
+; CHECK-NEXT: setp.eq.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB4_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB4_2: // %merge1
+; CHECK-NEXT: setp.lt.bf16 %p2, %rs1, %rs2;
+; CHECK-NEXT: @%p2 bra $L__BB4_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB4_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oeq bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp olt bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-float16.ll b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-float16.ll
new file mode 100644
index 0000000000000..6ea217ab97b53
--- /dev/null
+++ b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-float16.ll
@@ -0,0 +1,224 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -march=nvptx64 -mcpu=sm_100 -O2 < %s | FileCheck %s
+
+target triple = "nvptx64-nvidia-cuda"
+
+define i32 @test_float16_ueq_vs_une(half %a, half %b) {
+; CHECK-LABEL: test_float16_ueq_vs_une(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ueq_vs_une_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ueq_vs_une_param_0];
+; CHECK-NEXT: setp.equ.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB0_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB0_2: // %merge1
+; CHECK-NEXT: setp.neu.f16 %p2, %rs1, %rs2;
+; CHECK-NEXT: @%p2 bra $L__BB0_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB0_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ueq half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp une half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_oeq_vs_one(half %a, half %b) {
+; CHECK-LABEL: test_float16_oeq_vs_one(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_oeq_vs_one_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_oeq_vs_one_param_0];
+; CHECK-NEXT: setp.eq.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB1_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB1_2: // %merge1
+; CHECK-NEXT: setp.ne.f16 %p2, %rs1, %rs2;
+; CHECK-NEXT: @%p2 bra $L__BB1_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB1_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oeq half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp one half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_olt_vs_ogt(half %a, half %b) {
+; CHECK-LABEL: test_float16_olt_vs_ogt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_olt_vs_ogt_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_olt_vs_ogt_param_0];
+; CHECK-NEXT: setp.lt.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB2_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB2_2: // %merge1
+; CHECK-NEXT: setp.gt.f16 %p2, %rs1, %rs2;
+; CHECK-NEXT: @%p2 bra $L__BB2_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB2_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp olt half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ogt half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_ult_vs_ugt(half %a, half %b) {
+; CHECK-LABEL: test_float16_ult_vs_ugt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ult_vs_ugt_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ult_vs_ugt_param_0];
+; CHECK-NEXT: setp.ltu.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB3_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB3_2: // %merge1
+; CHECK-NEXT: setp.gtu.f16 %p2, %rs1, %rs2;
+; CHECK-NEXT: @%p2 bra $L__BB3_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB3_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ult half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ugt half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_oeq_vs_olt(half %a, half %b) {
+; CHECK-LABEL: test_float16_oeq_vs_olt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_oeq_vs_olt_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_oeq_vs_olt_param_0];
+; CHECK-NEXT: setp.eq.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB4_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB4_2: // %merge1
+; CHECK-NEXT: setp.lt.f16 %p2, %rs1, %rs2;
+; CHECK-NEXT: @%p2 bra $L__BB4_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB4_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oeq half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp olt half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-float32.ll b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-float32.ll
new file mode 100644
index 0000000000000..9008782b70b25
--- /dev/null
+++ b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-float32.ll
@@ -0,0 +1,214 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -march=nvptx64 -mcpu=sm_100 -O2 < %s | FileCheck %s
+
+target triple = "nvptx64-nvidia-cuda"
+
+define i32 @test_float32_ueq_vs_une(float %arg) {
+; CHECK-LABEL: test_float32_ueq_vs_une(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ueq_vs_une_param_0];
+; CHECK-NEXT: setp.equ.f32 %p1, %r1, 0f00000000;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB0_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB0_2: // %merge1
+; CHECK-NEXT: setp.neu.f32 %p2, %r1, 0f00000000;
+; CHECK-NEXT: @%p2 bra $L__BB0_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB0_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ueq float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp une float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_oeq_vs_one(float %arg) {
+; CHECK-LABEL: test_float32_oeq_vs_one(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_oeq_vs_one_param_0];
+; CHECK-NEXT: setp.eq.f32 %p1, %r1, 0f00000000;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB1_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB1_2: // %merge1
+; CHECK-NEXT: setp.ne.f32 %p2, %r1, 0f00000000;
+; CHECK-NEXT: @%p2 bra $L__BB1_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB1_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oeq float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp one float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_olt_vs_ogt(float %arg) {
+; CHECK-LABEL: test_float32_olt_vs_ogt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_olt_vs_ogt_param_0];
+; CHECK-NEXT: setp.lt.f32 %p1, %r1, 0f00000000;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB2_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB2_2: // %merge1
+; CHECK-NEXT: setp.gt.f32 %p2, %r1, 0f00000000;
+; CHECK-NEXT: @%p2 bra $L__BB2_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB2_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp olt float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ogt float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_ult_vs_ugt(float %arg) {
+; CHECK-LABEL: test_float32_ult_vs_ugt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ult_vs_ugt_param_0];
+; CHECK-NEXT: setp.ltu.f32 %p1, %r1, 0f00000000;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB3_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB3_2: // %merge1
+; CHECK-NEXT: setp.gtu.f32 %p2, %r1, 0f00000000;
+; CHECK-NEXT: @%p2 bra $L__BB3_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB3_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ult float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ugt float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_oeq_vs_olt(float %arg) {
+; CHECK-LABEL: test_float32_oeq_vs_olt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_oeq_vs_olt_param_0];
+; CHECK-NEXT: setp.eq.f32 %p1, %r1, 0f00000000;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB4_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB4_2: // %merge1
+; CHECK-NEXT: setp.lt.f32 %p2, %r1, 0f00000000;
+; CHECK-NEXT: @%p2 bra $L__BB4_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB4_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oeq float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp olt float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-float64.ll b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-float64.ll
new file mode 100644
index 0000000000000..1c6ab1ef6f093
--- /dev/null
+++ b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-float64.ll
@@ -0,0 +1,219 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -march=nvptx64 -mcpu=sm_100 -O2 < %s | FileCheck %s
+
+target triple = "nvptx64-nvidia-cuda"
+
+define i32 @test_float64_ueq_vs_une(double %arg) {
+; CHECK-LABEL: test_float64_ueq_vs_une(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ueq_vs_une_param_0];
+; CHECK-NEXT: setp.equ.f64 %p1, %rd1, 0d0000000000000000;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB0_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB0_2: // %merge1
+; CHECK-NEXT: setp.neu.f64 %p2, %rd1, 0d0000000000000000;
+; CHECK-NEXT: @%p2 bra $L__BB0_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB0_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ueq double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp une double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_oeq_vs_one(double %arg) {
+; CHECK-LABEL: test_float64_oeq_vs_one(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_oeq_vs_one_param_0];
+; CHECK-NEXT: setp.eq.f64 %p1, %rd1, 0d0000000000000000;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB1_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB1_2: // %merge1
+; CHECK-NEXT: setp.ne.f64 %p2, %rd1, 0d0000000000000000;
+; CHECK-NEXT: @%p2 bra $L__BB1_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB1_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oeq double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp one double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_olt_vs_ogt(double %arg) {
+; CHECK-LABEL: test_float64_olt_vs_ogt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_olt_vs_ogt_param_0];
+; CHECK-NEXT: setp.lt.f64 %p1, %rd1, 0d0000000000000000;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB2_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB2_2: // %merge1
+; CHECK-NEXT: setp.gt.f64 %p2, %rd1, 0d0000000000000000;
+; CHECK-NEXT: @%p2 bra $L__BB2_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB2_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp olt double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ogt double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_ult_vs_ugt(double %arg) {
+; CHECK-LABEL: test_float64_ult_vs_ugt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ult_vs_ugt_param_0];
+; CHECK-NEXT: setp.ltu.f64 %p1, %rd1, 0d0000000000000000;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB3_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB3_2: // %merge1
+; CHECK-NEXT: setp.gtu.f64 %p2, %rd1, 0d0000000000000000;
+; CHECK-NEXT: @%p2 bra $L__BB3_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB3_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ult double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ugt double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_oeq_vs_olt(double %arg) {
+; CHECK-LABEL: test_float64_oeq_vs_olt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_oeq_vs_olt_param_0];
+; CHECK-NEXT: setp.eq.f64 %p1, %rd1, 0d0000000000000000;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB4_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB4_2: // %merge1
+; CHECK-NEXT: setp.lt.f64 %p2, %rd1, 0d0000000000000000;
+; CHECK-NEXT: @%p2 bra $L__BB4_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB4_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oeq double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp olt double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-int16.ll b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-int16.ll
new file mode 100644
index 0000000000000..e9656967225e3
--- /dev/null
+++ b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-int16.ll
@@ -0,0 +1,224 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -march=nvptx64 -mcpu=sm_100 -O2 < %s | FileCheck %s
+
+target triple = "nvptx64-nvidia-cuda"
+
+define i32 @test_int16_slt_vs_sgt(i16 %a, i16 %b) {
+; CHECK-LABEL: test_int16_slt_vs_sgt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_slt_vs_sgt_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_slt_vs_sgt_param_0];
+; CHECK-NEXT: setp.lt.s16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB0_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB0_2: // %merge1
+; CHECK-NEXT: setp.gt.s16 %p2, %rs1, %rs2;
+; CHECK-NEXT: @%p2 bra $L__BB0_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB0_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp slt i16 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp sgt i16 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int16_ult_vs_ugt(i16 %a, i16 %b) {
+; CHECK-LABEL: test_int16_ult_vs_ugt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_ult_vs_ugt_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_ult_vs_ugt_param_0];
+; CHECK-NEXT: setp.lt.u16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB1_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB1_2: // %merge1
+; CHECK-NEXT: setp.gt.u16 %p2, %rs1, %rs2;
+; CHECK-NEXT: @%p2 bra $L__BB1_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB1_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp ult i16 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp ugt i16 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int16_slt_vs_uge(i16 %a, i16 %b) {
+; CHECK-LABEL: test_int16_slt_vs_uge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_slt_vs_uge_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_slt_vs_uge_param_0];
+; CHECK-NEXT: setp.lt.s16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB2_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB2_2: // %merge1
+; CHECK-NEXT: setp.ge.u16 %p2, %rs1, %rs2;
+; CHECK-NEXT: @%p2 bra $L__BB2_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB2_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp slt i16 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp uge i16 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int16_eq_vs_slt(i16 %a, i16 %b) {
+; CHECK-LABEL: test_int16_eq_vs_slt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_eq_vs_slt_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_eq_vs_slt_param_0];
+; CHECK-NEXT: setp.eq.b16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB3_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB3_2: // %merge1
+; CHECK-NEXT: setp.lt.s16 %p2, %rs1, %rs2;
+; CHECK-NEXT: @%p2 bra $L__BB3_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB3_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp eq i16 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp slt i16 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int16_ult_vs_sge(i16 %a, i16 %b) {
+; CHECK-LABEL: test_int16_ult_vs_sge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_ult_vs_sge_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_ult_vs_sge_param_0];
+; CHECK-NEXT: setp.lt.u16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB4_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB4_2: // %merge1
+; CHECK-NEXT: setp.ge.s16 %p2, %rs1, %rs2;
+; CHECK-NEXT: @%p2 bra $L__BB4_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB4_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp ult i16 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp sge i16 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-int32.ll b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-int32.ll
new file mode 100644
index 0000000000000..3820ea527dc05
--- /dev/null
+++ b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-int32.ll
@@ -0,0 +1,219 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -march=nvptx64 -mcpu=sm_100 -O2 < %s | FileCheck %s
+
+target triple = "nvptx64-nvidia-cuda"
+
+define i32 @test_int32_slt_vs_sgt(i32 %a, i32 %b) {
+; CHECK-LABEL: test_int32_slt_vs_sgt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r2, [test_int32_slt_vs_sgt_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_int32_slt_vs_sgt_param_0];
+; CHECK-NEXT: setp.lt.s32 %p1, %r1, %r2;
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: @%p1 bra $L__BB0_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r3, 1;
+; CHECK-NEXT: $L__BB0_2: // %merge1
+; CHECK-NEXT: setp.gt.s32 %p2, %r1, %r2;
+; CHECK-NEXT: @%p2 bra $L__BB0_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: $L__BB0_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp slt i32 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp sgt i32 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int32_ult_vs_ugt(i32 %a, i32 %b) {
+; CHECK-LABEL: test_int32_ult_vs_ugt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r2, [test_int32_ult_vs_ugt_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_int32_ult_vs_ugt_param_0];
+; CHECK-NEXT: setp.lt.u32 %p1, %r1, %r2;
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: @%p1 bra $L__BB1_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r3, 1;
+; CHECK-NEXT: $L__BB1_2: // %merge1
+; CHECK-NEXT: setp.gt.u32 %p2, %r1, %r2;
+; CHECK-NEXT: @%p2 bra $L__BB1_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: $L__BB1_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp ult i32 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp ugt i32 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int32_slt_vs_uge(i32 %a, i32 %b) {
+; CHECK-LABEL: test_int32_slt_vs_uge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r2, [test_int32_slt_vs_uge_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_int32_slt_vs_uge_param_0];
+; CHECK-NEXT: setp.lt.s32 %p1, %r1, %r2;
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: @%p1 bra $L__BB2_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r3, 1;
+; CHECK-NEXT: $L__BB2_2: // %merge1
+; CHECK-NEXT: setp.ge.u32 %p2, %r1, %r2;
+; CHECK-NEXT: @%p2 bra $L__BB2_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: $L__BB2_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp slt i32 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp uge i32 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int32_eq_vs_slt(i32 %a, i32 %b) {
+; CHECK-LABEL: test_int32_eq_vs_slt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r2, [test_int32_eq_vs_slt_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_int32_eq_vs_slt_param_0];
+; CHECK-NEXT: setp.eq.b32 %p1, %r1, %r2;
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: @%p1 bra $L__BB3_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r3, 1;
+; CHECK-NEXT: $L__BB3_2: // %merge1
+; CHECK-NEXT: setp.lt.s32 %p2, %r1, %r2;
+; CHECK-NEXT: @%p2 bra $L__BB3_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: $L__BB3_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp eq i32 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp slt i32 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int32_ult_vs_sge(i32 %a, i32 %b) {
+; CHECK-LABEL: test_int32_ult_vs_sge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r2, [test_int32_ult_vs_sge_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_int32_ult_vs_sge_param_0];
+; CHECK-NEXT: setp.lt.u32 %p1, %r1, %r2;
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: @%p1 bra $L__BB4_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r3, 1;
+; CHECK-NEXT: $L__BB4_2: // %merge1
+; CHECK-NEXT: setp.ge.s32 %p2, %r1, %r2;
+; CHECK-NEXT: @%p2 bra $L__BB4_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: $L__BB4_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp ult i32 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp sge i32 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-int64.ll b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-int64.ll
new file mode 100644
index 0000000000000..9989929f8f5db
--- /dev/null
+++ b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-int64.ll
@@ -0,0 +1,224 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -march=nvptx64 -mcpu=sm_100 -O2 < %s | FileCheck %s
+
+target triple = "nvptx64-nvidia-cuda"
+
+define i32 @test_int64_slt_vs_sgt(i64 %a, i64 %b) {
+; CHECK-LABEL: test_int64_slt_vs_sgt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_slt_vs_sgt_param_1];
+; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_slt_vs_sgt_param_0];
+; CHECK-NEXT: setp.lt.s64 %p1, %rd1, %rd2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB0_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB0_2: // %merge1
+; CHECK-NEXT: setp.gt.s64 %p2, %rd1, %rd2;
+; CHECK-NEXT: @%p2 bra $L__BB0_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB0_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp slt i64 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp sgt i64 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int64_ult_vs_ugt(i64 %a, i64 %b) {
+; CHECK-LABEL: test_int64_ult_vs_ugt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_ult_vs_ugt_param_1];
+; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_ult_vs_ugt_param_0];
+; CHECK-NEXT: setp.lt.u64 %p1, %rd1, %rd2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB1_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB1_2: // %merge1
+; CHECK-NEXT: setp.gt.u64 %p2, %rd1, %rd2;
+; CHECK-NEXT: @%p2 bra $L__BB1_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB1_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp ult i64 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp ugt i64 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int64_slt_vs_uge(i64 %a, i64 %b) {
+; CHECK-LABEL: test_int64_slt_vs_uge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_slt_vs_uge_param_1];
+; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_slt_vs_uge_param_0];
+; CHECK-NEXT: setp.lt.s64 %p1, %rd1, %rd2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB2_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB2_2: // %merge1
+; CHECK-NEXT: setp.ge.u64 %p2, %rd1, %rd2;
+; CHECK-NEXT: @%p2 bra $L__BB2_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB2_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp slt i64 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp uge i64 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int64_eq_vs_slt(i64 %a, i64 %b) {
+; CHECK-LABEL: test_int64_eq_vs_slt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_eq_vs_slt_param_1];
+; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_eq_vs_slt_param_0];
+; CHECK-NEXT: setp.eq.b64 %p1, %rd1, %rd2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB3_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB3_2: // %merge1
+; CHECK-NEXT: setp.lt.s64 %p2, %rd1, %rd2;
+; CHECK-NEXT: @%p2 bra $L__BB3_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB3_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp eq i64 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp slt i64 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int64_ult_vs_sge(i64 %a, i64 %b) {
+; CHECK-LABEL: test_int64_ult_vs_sge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_ult_vs_sge_param_1];
+; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_ult_vs_sge_param_0];
+; CHECK-NEXT: setp.lt.u64 %p1, %rd1, %rd2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB4_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB4_2: // %merge1
+; CHECK-NEXT: setp.ge.s64 %p2, %rd1, %rd2;
+; CHECK-NEXT: @%p2 bra $L__BB4_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB4_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp ult i64 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp sge i64 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
>From ab563e9ba017d51f8eee95aaf2c0d74e9e9f3cdc Mon Sep 17 00:00:00 2001
From: Modi Mo <mmo at nvidia.com>
Date: Mon, 20 Apr 2026 18:43:48 -0700
Subject: [PATCH 2/6] update rollback logic and add test exercising it
---
llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp | 36 +++++-----
llvm/lib/Target/NVPTX/NVPTXInstrInfo.td | 2 +-
...-cse-predicate-inversion-multiple-users.ll | 16 +++--
...chine-cse-predicate-inversion-rollback.mir | 66 +++++++++++++++++++
4 files changed, 93 insertions(+), 27 deletions(-)
create mode 100644 llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-rollback.mir
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
index 495dd2518bf4d..d9900e98fe694 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
@@ -344,30 +344,28 @@ MachineInstr *NVPTXInstrInfo::commuteInstructionImpl(MachineInstr &MI,
if (!isIntegerSetp(MI) && !isScalarFloatSetp(MI))
return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
- invertScalarCompareInstr(MI);
-
// For now all users must be invertible conditional branches.
// TODO: Support other users such as selects.
- bool AllInverted = true;
MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
+ SmallVector<MachineBasicBlock *, 4> BranchMBBs;
for (MachineInstr &UseMI :
MRI.use_nodbg_instructions(MI.getOperand(0).getReg())) {
- if (!(UseMI.isConditionalBranch() &&
- invertPredicateBranchInstr(*UseMI.getParent()))) {
- AllInverted = false;
- break;
- }
+ if (!UseMI.isConditionalBranch())
+ return nullptr;
+ BranchMBBs.push_back(UseMI.getParent());
}
- if (!AllInverted) {
- for (MachineInstr &UseMI :
- MRI.use_nodbg_instructions(MI.getOperand(0).getReg())) {
- if (!(UseMI.isConditionalBranch() &&
- invertPredicateBranchInstr(*UseMI.getParent())))
- break;
- }
- invertScalarCompareInstr(MI);
- return nullptr;
- }
- return &MI;
+ invertScalarCompareInstr(MI);
+ auto *Failed = llvm::find_if(BranchMBBs, [this](MachineBasicBlock *MBB) {
+ return !invertPredicateBranchInstr(*MBB);
+ });
+ if (Failed == BranchMBBs.end())
+ return &MI;
+
+ // Couldn't invert one of the branches. Roll back the prefix we
+ // already inverted and the compare-mode flip.
+ for (MachineBasicBlock *MBB : make_range(BranchMBBs.begin(), Failed))
+ invertPredicateBranchInstr(*MBB);
+ invertScalarCompareInstr(MI);
+ return nullptr;
}
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
index e35a7e92cf31b..4b30611c3a128 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
@@ -77,7 +77,7 @@ def FTZFlag : OperandWithDefaultOps<i1, (ops (getFTZFlag (i1 0)))> {
let PrintMethod = "printFTZFlag";
}
-def BranchFlag : OperandWithDefaultOps<i32, (ops (i32 0))> {
+def BranchFlag : OperandWithDefaultOps<i32, (ops (i1 0))> {
let PrintMethod = "printNegatedPredicate";
}
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-multiple-users.ll b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-multiple-users.ll
index bf4a77f599061..7b71053758147 100644
--- a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-multiple-users.ll
+++ b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-multiple-users.ll
@@ -7,7 +7,7 @@ target triple = "nvptx64-nvidia-cuda"
define i32 @test_multiple_users(i32 %a, i32 %b) {
; CHECK-LABEL: test_multiple_users(
; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .pred %p<3>;
; CHECK-NEXT: .reg .b32 %r<6>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0: // %entry
@@ -19,8 +19,9 @@ define i32 @test_multiple_users(i32 %a, i32 %b) {
; CHECK-NEXT: // %bb.1: // %then
; CHECK-NEXT: mov.b32 %r5, 1;
; CHECK-NEXT: $L__BB0_2: // %merge1
-; CHECK-NEXT: selp.b32 %r1, 1, 0, %p1;
-; CHECK-NEXT: @!%p1 bra $L__BB0_4;
+; CHECK-NEXT: setp.ne.b32 %p2, %r2, %r3;
+; CHECK-NEXT: selp.b32 %r1, 1, 0, %p2;
+; CHECK-NEXT: @%p1 bra $L__BB0_4;
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r5, 0;
; CHECK-NEXT: $L__BB0_4: // %merge2
@@ -28,8 +29,8 @@ define i32 @test_multiple_users(i32 %a, i32 %b) {
; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
; CHECK-NEXT: ret;
entry:
- %cmp = icmp eq i32 %a, %b
- br i1 %cmp, label %merge1, label %then
+ %cmp1 = icmp eq i32 %a, %b
+ br i1 %cmp1, label %merge1, label %then
then:
%tmp = load i32, ptr addrspace(1) null, align 4
@@ -37,8 +38,9 @@ then:
merge1:
%phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %val = select i1 %cmp, i32 1, i32 0
- br i1 %cmp, label %else, label %merge2
+ %cmp2 = icmp ne i32 %a, %b
+ %val = select i1 %cmp2, i32 1, i32 0
+ br i1 %cmp2, label %else, label %merge2
else:
br label %merge2
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-rollback.mir b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-rollback.mir
new file mode 100644
index 0000000000000..0a4e99da61939
--- /dev/null
+++ b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-rollback.mir
@@ -0,0 +1,66 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=nvptx64 -mcpu=sm_100 -run-pass=machine-cse -o - %s | FileCheck %s
+
+---
+name: rollback
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: rollback
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.4(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:b32 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:b32 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[SETP_i32rr:%[0-9]+]]:b1 = SETP_i32rr [[DEF]], [[DEF1]], 0
+ ; CHECK-NEXT: CBranch [[SETP_i32rr]], %bb.4, 0
+ ; CHECK-NEXT: GOTO %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[SETP_i32rr1:%[0-9]+]]:b1 = SETP_i32rr [[DEF]], [[DEF1]], 1
+ ; CHECK-NEXT: CBranch [[SETP_i32rr1]], %bb.4, 0
+ ; CHECK-NEXT: GOTO %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.4(0x40000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: CBranch [[SETP_i32rr1]], %bb.4, 0
+ ; CHECK-NEXT: CBranch [[SETP_i32rr1]], %bb.4, 0
+ ; CHECK-NEXT: GOTO %bb.3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3:
+ ; CHECK-NEXT: Return
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4:
+ ; CHECK-NEXT: Return
+ bb.0:
+ successors: %bb.1, %bb.4
+
+ %0:b32 = IMPLICIT_DEF
+ %1:b32 = IMPLICIT_DEF
+ %2:b1 = SETP_i32rr %0, %1, 0
+ CBranch %2, %bb.4, 0
+ GOTO %bb.1
+
+ bb.1:
+ successors: %bb.2, %bb.4
+
+ %3:b1 = SETP_i32rr %0, %1, 1
+ CBranch %3, %bb.4, 0
+ GOTO %bb.2
+
+ bb.2:
+ successors: %bb.3, %bb.4
+
+ CBranch %3, %bb.4, 0
+ CBranch %3, %bb.4, 0
+ GOTO %bb.3
+
+ bb.3:
+ Return
+
+ bb.4:
+ Return
+
+...
>From de26666a99e7083816b391d94266b714d2abab1e Mon Sep 17 00:00:00 2001
From: Modi Mo <mmo at nvidia.com>
Date: Tue, 21 Apr 2026 14:41:39 -0700
Subject: [PATCH 3/6] Move inversion/no inversion tests to one file. Fixup
issue in machine-cse-predicate-inversion-multiple-users.ll
---
...achine-cse-predicate-inversion-bfloat16.ll | 695 ---
...machine-cse-predicate-inversion-float16.ll | 695 ---
...machine-cse-predicate-inversion-float32.ll | 663 ---
...machine-cse-predicate-inversion-float64.ll | 679 ---
.../machine-cse-predicate-inversion-int16.ll | 437 --
.../machine-cse-predicate-inversion-int32.ll | 427 --
.../machine-cse-predicate-inversion-int64.ll | 437 --
...-cse-predicate-inversion-multiple-users.ll | 6 +-
.../NVPTX/machine-cse-predicate-inversion.ll | 3997 +++++++++++++++++
...ine-cse-predicate-no-inversion-bfloat16.ll | 224 -
...hine-cse-predicate-no-inversion-float16.ll | 224 -
...hine-cse-predicate-no-inversion-float32.ll | 214 -
...hine-cse-predicate-no-inversion-float64.ll | 219 -
...achine-cse-predicate-no-inversion-int16.ll | 224 -
...achine-cse-predicate-no-inversion-int32.ll | 219 -
...achine-cse-predicate-no-inversion-int64.ll | 224 -
.../machine-cse-predicate-no-inversion.ll | 1525 +++++++
17 files changed, 5526 insertions(+), 5583 deletions(-)
delete mode 100644 llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-bfloat16.ll
delete mode 100644 llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-float16.ll
delete mode 100644 llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-float32.ll
delete mode 100644 llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-float64.ll
delete mode 100644 llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-int16.ll
delete mode 100644 llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-int32.ll
delete mode 100644 llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-int64.ll
create mode 100644 llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion.ll
delete mode 100644 llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-bfloat16.ll
delete mode 100644 llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-float16.ll
delete mode 100644 llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-float32.ll
delete mode 100644 llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-float64.ll
delete mode 100644 llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-int16.ll
delete mode 100644 llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-int32.ll
delete mode 100644 llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-int64.ll
create mode 100644 llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion.ll
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-bfloat16.ll b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-bfloat16.ll
deleted file mode 100644
index b6b77e9c09108..0000000000000
--- a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-bfloat16.ll
+++ /dev/null
@@ -1,695 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -march=nvptx64 -mcpu=sm_100 -O2 < %s | FileCheck %s
-; RUN: %if ptxas-sm_100 %{ llc < %s -march=nvptx64 -mcpu=sm_100 -O2 | %ptxas-verify -arch=sm_100 %}
-
-target triple = "nvptx64-nvidia-cuda"
-
-define i32 @test_bfloat16_eq(bfloat %a, bfloat %b) {
-; CHECK-LABEL: test_bfloat16_eq(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_eq_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_eq_param_0];
-; CHECK-NEXT: setp.eq.bf16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB0_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB0_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB0_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB0_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp oeq bfloat %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp une bfloat %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_bfloat16_ne(bfloat %a, bfloat %b) {
-; CHECK-LABEL: test_bfloat16_ne(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ne_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ne_param_0];
-; CHECK-NEXT: setp.ne.bf16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB1_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB1_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB1_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB1_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp one bfloat %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ueq bfloat %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_bfloat16_oeq(bfloat %a, bfloat %b) {
-; CHECK-LABEL: test_bfloat16_oeq(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_oeq_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_oeq_param_0];
-; CHECK-NEXT: setp.eq.bf16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB2_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB2_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB2_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB2_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp oeq bfloat %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp une bfloat %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_bfloat16_one(bfloat %a, bfloat %b) {
-; CHECK-LABEL: test_bfloat16_one(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_one_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_one_param_0];
-; CHECK-NEXT: setp.ne.bf16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB3_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB3_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB3_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB3_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp one bfloat %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ueq bfloat %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_bfloat16_ueq(bfloat %a, bfloat %b) {
-; CHECK-LABEL: test_bfloat16_ueq(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ueq_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ueq_param_0];
-; CHECK-NEXT: setp.equ.bf16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB4_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB4_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB4_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB4_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp ueq bfloat %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp one bfloat %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_bfloat16_une(bfloat %a, bfloat %b) {
-; CHECK-LABEL: test_bfloat16_une(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_une_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_une_param_0];
-; CHECK-NEXT: setp.neu.bf16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB5_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB5_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB5_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB5_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp une bfloat %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp oeq bfloat %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_bfloat16_olt(bfloat %a, bfloat %b) {
-; CHECK-LABEL: test_bfloat16_olt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_olt_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_olt_param_0];
-; CHECK-NEXT: setp.lt.bf16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB6_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB6_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB6_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB6_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp olt bfloat %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp uge bfloat %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_bfloat16_ole(bfloat %a, bfloat %b) {
-; CHECK-LABEL: test_bfloat16_ole(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ole_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ole_param_0];
-; CHECK-NEXT: setp.le.bf16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB7_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB7_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB7_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB7_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp ole bfloat %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ugt bfloat %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_bfloat16_ogt(bfloat %a, bfloat %b) {
-; CHECK-LABEL: test_bfloat16_ogt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ogt_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ogt_param_0];
-; CHECK-NEXT: setp.gt.bf16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB8_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB8_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB8_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB8_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp ogt bfloat %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ule bfloat %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_bfloat16_oge(bfloat %a, bfloat %b) {
-; CHECK-LABEL: test_bfloat16_oge(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_oge_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_oge_param_0];
-; CHECK-NEXT: setp.ge.bf16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB9_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB9_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB9_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB9_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp oge bfloat %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ult bfloat %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_bfloat16_ult(bfloat %a, bfloat %b) {
-; CHECK-LABEL: test_bfloat16_ult(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ult_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ult_param_0];
-; CHECK-NEXT: setp.ltu.bf16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB10_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB10_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB10_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB10_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp ult bfloat %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp oge bfloat %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_bfloat16_ule(bfloat %a, bfloat %b) {
-; CHECK-LABEL: test_bfloat16_ule(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ule_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ule_param_0];
-; CHECK-NEXT: setp.leu.bf16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB11_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB11_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB11_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB11_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp ule bfloat %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ogt bfloat %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_bfloat16_ugt(bfloat %a, bfloat %b) {
-; CHECK-LABEL: test_bfloat16_ugt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ugt_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ugt_param_0];
-; CHECK-NEXT: setp.gtu.bf16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB12_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB12_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB12_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB12_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp ugt bfloat %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ole bfloat %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_bfloat16_uge(bfloat %a, bfloat %b) {
-; CHECK-LABEL: test_bfloat16_uge(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_uge_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_uge_param_0];
-; CHECK-NEXT: setp.geu.bf16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB13_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB13_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB13_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB13_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp uge bfloat %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp olt bfloat %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_bfloat16_ord(bfloat %a, bfloat %b) {
-; CHECK-LABEL: test_bfloat16_ord(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ord_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ord_param_0];
-; CHECK-NEXT: setp.num.bf16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @!%p1 bra $L__BB14_1;
-; CHECK-NEXT: $L__BB14_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB14_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB14_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-; CHECK-NEXT: $L__BB14_1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: bra.uni $L__BB14_2;
-entry:
- %cmp = fcmp ord bfloat %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp uno bfloat %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_bfloat16_uno(bfloat %a, bfloat %b) {
-; CHECK-LABEL: test_bfloat16_uno(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_uno_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_uno_param_0];
-; CHECK-NEXT: setp.nan.bf16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB15_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB15_2: // %merge1
-; CHECK-NEXT: @%p1 bra $L__BB15_3;
-; CHECK-NEXT: $L__BB15_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-; CHECK-NEXT: $L__BB15_3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: bra.uni $L__BB15_4;
-entry:
- %cmp = fcmp uno bfloat %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ord bfloat %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-float16.ll b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-float16.ll
deleted file mode 100644
index 42aa05da4c76a..0000000000000
--- a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-float16.ll
+++ /dev/null
@@ -1,695 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -march=nvptx64 -mcpu=sm_100 -O2 < %s | FileCheck %s
-; RUN: %if ptxas-sm_100 %{ llc < %s -march=nvptx64 -mcpu=sm_100 -O2 | %ptxas-verify -arch=sm_100 %}
-
-target triple = "nvptx64-nvidia-cuda"
-
-define i32 @test_float16_eq(half %a, half %b) {
-; CHECK-LABEL: test_float16_eq(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_eq_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_eq_param_0];
-; CHECK-NEXT: setp.eq.f16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB0_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB0_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB0_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB0_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp oeq half %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp une half %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float16_ne(half %a, half %b) {
-; CHECK-LABEL: test_float16_ne(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ne_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ne_param_0];
-; CHECK-NEXT: setp.ne.f16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB1_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB1_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB1_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB1_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp one half %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ueq half %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float16_oeq(half %a, half %b) {
-; CHECK-LABEL: test_float16_oeq(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_oeq_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_oeq_param_0];
-; CHECK-NEXT: setp.eq.f16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB2_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB2_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB2_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB2_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp oeq half %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp une half %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float16_one(half %a, half %b) {
-; CHECK-LABEL: test_float16_one(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_one_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_one_param_0];
-; CHECK-NEXT: setp.ne.f16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB3_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB3_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB3_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB3_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp one half %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ueq half %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float16_ueq(half %a, half %b) {
-; CHECK-LABEL: test_float16_ueq(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ueq_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ueq_param_0];
-; CHECK-NEXT: setp.equ.f16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB4_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB4_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB4_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB4_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp ueq half %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp one half %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float16_une(half %a, half %b) {
-; CHECK-LABEL: test_float16_une(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_une_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_une_param_0];
-; CHECK-NEXT: setp.neu.f16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB5_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB5_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB5_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB5_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp une half %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp oeq half %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float16_olt(half %a, half %b) {
-; CHECK-LABEL: test_float16_olt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_olt_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_olt_param_0];
-; CHECK-NEXT: setp.lt.f16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB6_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB6_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB6_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB6_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp olt half %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp uge half %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float16_ole(half %a, half %b) {
-; CHECK-LABEL: test_float16_ole(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ole_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ole_param_0];
-; CHECK-NEXT: setp.le.f16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB7_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB7_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB7_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB7_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp ole half %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ugt half %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float16_ogt(half %a, half %b) {
-; CHECK-LABEL: test_float16_ogt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ogt_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ogt_param_0];
-; CHECK-NEXT: setp.gt.f16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB8_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB8_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB8_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB8_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp ogt half %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ule half %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float16_oge(half %a, half %b) {
-; CHECK-LABEL: test_float16_oge(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_oge_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_oge_param_0];
-; CHECK-NEXT: setp.ge.f16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB9_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB9_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB9_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB9_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp oge half %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ult half %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float16_ult(half %a, half %b) {
-; CHECK-LABEL: test_float16_ult(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ult_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ult_param_0];
-; CHECK-NEXT: setp.ltu.f16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB10_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB10_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB10_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB10_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp ult half %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp oge half %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float16_ule(half %a, half %b) {
-; CHECK-LABEL: test_float16_ule(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ule_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ule_param_0];
-; CHECK-NEXT: setp.leu.f16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB11_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB11_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB11_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB11_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp ule half %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ogt half %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float16_ugt(half %a, half %b) {
-; CHECK-LABEL: test_float16_ugt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ugt_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ugt_param_0];
-; CHECK-NEXT: setp.gtu.f16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB12_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB12_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB12_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB12_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp ugt half %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ole half %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float16_uge(half %a, half %b) {
-; CHECK-LABEL: test_float16_uge(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_uge_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_uge_param_0];
-; CHECK-NEXT: setp.geu.f16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB13_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB13_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB13_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB13_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp uge half %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp olt half %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float16_ord(half %a, half %b) {
-; CHECK-LABEL: test_float16_ord(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ord_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ord_param_0];
-; CHECK-NEXT: setp.num.f16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @!%p1 bra $L__BB14_1;
-; CHECK-NEXT: $L__BB14_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB14_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB14_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-; CHECK-NEXT: $L__BB14_1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: bra.uni $L__BB14_2;
-entry:
- %cmp = fcmp ord half %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp uno half %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float16_uno(half %a, half %b) {
-; CHECK-LABEL: test_float16_uno(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_uno_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_uno_param_0];
-; CHECK-NEXT: setp.nan.f16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB15_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB15_2: // %merge1
-; CHECK-NEXT: @%p1 bra $L__BB15_3;
-; CHECK-NEXT: $L__BB15_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-; CHECK-NEXT: $L__BB15_3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: bra.uni $L__BB15_4;
-entry:
- %cmp = fcmp uno half %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ord half %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-float32.ll b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-float32.ll
deleted file mode 100644
index a034ef25aea11..0000000000000
--- a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-float32.ll
+++ /dev/null
@@ -1,663 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -march=nvptx64 -mcpu=sm_100 -O2 < %s | FileCheck %s
-; RUN: %if ptxas-sm_100 %{ llc < %s -march=nvptx64 -mcpu=sm_100 -O2 | %ptxas-verify -arch=sm_100 %}
-
-target triple = "nvptx64-nvidia-cuda"
-
-define i32 @test_float32_eq(float %arg) {
-; CHECK-LABEL: test_float32_eq(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_eq_param_0];
-; CHECK-NEXT: setp.eq.f32 %p1, %r1, 0f00000000;
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: @%p1 bra $L__BB0_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r2, 1;
-; CHECK-NEXT: $L__BB0_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB0_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: $L__BB0_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp oeq float %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp une float %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float32_ne(float %arg) {
-; CHECK-LABEL: test_float32_ne(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ne_param_0];
-; CHECK-NEXT: setp.ne.f32 %p1, %r1, 0f00000000;
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: @%p1 bra $L__BB1_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r2, 1;
-; CHECK-NEXT: $L__BB1_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB1_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: $L__BB1_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp one float %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ueq float %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float32_oeq(float %arg) {
-; CHECK-LABEL: test_float32_oeq(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_oeq_param_0];
-; CHECK-NEXT: setp.eq.f32 %p1, %r1, 0f00000000;
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: @%p1 bra $L__BB2_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r2, 1;
-; CHECK-NEXT: $L__BB2_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB2_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: $L__BB2_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp oeq float %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp une float %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float32_one(float %arg) {
-; CHECK-LABEL: test_float32_one(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_one_param_0];
-; CHECK-NEXT: setp.ne.f32 %p1, %r1, 0f00000000;
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: @%p1 bra $L__BB3_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r2, 1;
-; CHECK-NEXT: $L__BB3_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB3_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: $L__BB3_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp one float %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ueq float %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float32_ueq(float %arg) {
-; CHECK-LABEL: test_float32_ueq(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ueq_param_0];
-; CHECK-NEXT: setp.equ.f32 %p1, %r1, 0f00000000;
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: @%p1 bra $L__BB4_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r2, 1;
-; CHECK-NEXT: $L__BB4_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB4_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: $L__BB4_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp ueq float %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp one float %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float32_une(float %arg) {
-; CHECK-LABEL: test_float32_une(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_une_param_0];
-; CHECK-NEXT: setp.neu.f32 %p1, %r1, 0f00000000;
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: @%p1 bra $L__BB5_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r2, 1;
-; CHECK-NEXT: $L__BB5_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB5_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: $L__BB5_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp une float %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp oeq float %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float32_olt(float %arg) {
-; CHECK-LABEL: test_float32_olt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_olt_param_0];
-; CHECK-NEXT: setp.lt.f32 %p1, %r1, 0f00000000;
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: @%p1 bra $L__BB6_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r2, 1;
-; CHECK-NEXT: $L__BB6_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB6_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: $L__BB6_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp olt float %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp uge float %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float32_ole(float %arg) {
-; CHECK-LABEL: test_float32_ole(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ole_param_0];
-; CHECK-NEXT: setp.le.f32 %p1, %r1, 0f00000000;
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: @%p1 bra $L__BB7_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r2, 1;
-; CHECK-NEXT: $L__BB7_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB7_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: $L__BB7_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp ole float %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ugt float %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float32_ogt(float %arg) {
-; CHECK-LABEL: test_float32_ogt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ogt_param_0];
-; CHECK-NEXT: setp.gt.f32 %p1, %r1, 0f00000000;
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: @%p1 bra $L__BB8_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r2, 1;
-; CHECK-NEXT: $L__BB8_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB8_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: $L__BB8_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp ogt float %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ule float %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float32_oge(float %arg) {
-; CHECK-LABEL: test_float32_oge(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_oge_param_0];
-; CHECK-NEXT: setp.ge.f32 %p1, %r1, 0f00000000;
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: @%p1 bra $L__BB9_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r2, 1;
-; CHECK-NEXT: $L__BB9_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB9_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: $L__BB9_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp oge float %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ult float %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float32_ult(float %arg) {
-; CHECK-LABEL: test_float32_ult(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ult_param_0];
-; CHECK-NEXT: setp.ltu.f32 %p1, %r1, 0f00000000;
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: @%p1 bra $L__BB10_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r2, 1;
-; CHECK-NEXT: $L__BB10_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB10_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: $L__BB10_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp ult float %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp oge float %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float32_ule(float %arg) {
-; CHECK-LABEL: test_float32_ule(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ule_param_0];
-; CHECK-NEXT: setp.leu.f32 %p1, %r1, 0f00000000;
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: @%p1 bra $L__BB11_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r2, 1;
-; CHECK-NEXT: $L__BB11_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB11_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: $L__BB11_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp ule float %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ogt float %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float32_ugt(float %arg) {
-; CHECK-LABEL: test_float32_ugt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ugt_param_0];
-; CHECK-NEXT: setp.gtu.f32 %p1, %r1, 0f00000000;
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: @%p1 bra $L__BB12_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r2, 1;
-; CHECK-NEXT: $L__BB12_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB12_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: $L__BB12_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp ugt float %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ole float %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float32_uge(float %arg) {
-; CHECK-LABEL: test_float32_uge(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_uge_param_0];
-; CHECK-NEXT: setp.geu.f32 %p1, %r1, 0f00000000;
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: @%p1 bra $L__BB13_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r2, 1;
-; CHECK-NEXT: $L__BB13_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB13_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: $L__BB13_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp uge float %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp olt float %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float32_ord(float %arg) {
-; CHECK-LABEL: test_float32_ord(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ord_param_0];
-; CHECK-NEXT: setp.num.f32 %p1, %r1, %r1;
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: @!%p1 bra $L__BB14_1;
-; CHECK-NEXT: $L__BB14_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB14_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: $L__BB14_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
-; CHECK-NEXT: ret;
-; CHECK-NEXT: $L__BB14_1: // %then
-; CHECK-NEXT: mov.b32 %r2, 1;
-; CHECK-NEXT: bra.uni $L__BB14_2;
-entry:
- %cmp = fcmp ord float %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp uno float %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float32_uno(float %arg) {
-; CHECK-LABEL: test_float32_uno(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_uno_param_0];
-; CHECK-NEXT: setp.nan.f32 %p1, %r1, %r1;
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: @%p1 bra $L__BB15_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r2, 1;
-; CHECK-NEXT: $L__BB15_2: // %merge1
-; CHECK-NEXT: @%p1 bra $L__BB15_3;
-; CHECK-NEXT: $L__BB15_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
-; CHECK-NEXT: ret;
-; CHECK-NEXT: $L__BB15_3: // %else
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: bra.uni $L__BB15_4;
-entry:
- %cmp = fcmp uno float %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ord float %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-float64.ll b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-float64.ll
deleted file mode 100644
index 4106d7b9a9184..0000000000000
--- a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-float64.ll
+++ /dev/null
@@ -1,679 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -march=nvptx64 -mcpu=sm_100 -O2 < %s | FileCheck %s
-; RUN: %if ptxas-sm_100 %{ llc < %s -march=nvptx64 -mcpu=sm_100 -O2 | %ptxas-verify -arch=sm_100 %}
-
-target triple = "nvptx64-nvidia-cuda"
-
-define i32 @test_float64_eq(double %arg) {
-; CHECK-LABEL: test_float64_eq(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_eq_param_0];
-; CHECK-NEXT: setp.eq.f64 %p1, %rd1, 0d0000000000000000;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB0_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB0_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB0_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB0_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp oeq double %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp une double %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float64_ne(double %arg) {
-; CHECK-LABEL: test_float64_ne(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ne_param_0];
-; CHECK-NEXT: setp.ne.f64 %p1, %rd1, 0d0000000000000000;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB1_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB1_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB1_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB1_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp one double %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ueq double %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float64_oeq(double %arg) {
-; CHECK-LABEL: test_float64_oeq(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_oeq_param_0];
-; CHECK-NEXT: setp.eq.f64 %p1, %rd1, 0d0000000000000000;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB2_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB2_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB2_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB2_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp oeq double %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp une double %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float64_one(double %arg) {
-; CHECK-LABEL: test_float64_one(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_one_param_0];
-; CHECK-NEXT: setp.ne.f64 %p1, %rd1, 0d0000000000000000;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB3_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB3_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB3_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB3_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp one double %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ueq double %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float64_ueq(double %arg) {
-; CHECK-LABEL: test_float64_ueq(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ueq_param_0];
-; CHECK-NEXT: setp.equ.f64 %p1, %rd1, 0d0000000000000000;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB4_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB4_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB4_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB4_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp ueq double %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp one double %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float64_une(double %arg) {
-; CHECK-LABEL: test_float64_une(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_une_param_0];
-; CHECK-NEXT: setp.neu.f64 %p1, %rd1, 0d0000000000000000;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB5_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB5_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB5_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB5_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp une double %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp oeq double %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float64_olt(double %arg) {
-; CHECK-LABEL: test_float64_olt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_olt_param_0];
-; CHECK-NEXT: setp.lt.f64 %p1, %rd1, 0d0000000000000000;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB6_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB6_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB6_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB6_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp olt double %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp uge double %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float64_ole(double %arg) {
-; CHECK-LABEL: test_float64_ole(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ole_param_0];
-; CHECK-NEXT: setp.le.f64 %p1, %rd1, 0d0000000000000000;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB7_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB7_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB7_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB7_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp ole double %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ugt double %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float64_ogt(double %arg) {
-; CHECK-LABEL: test_float64_ogt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ogt_param_0];
-; CHECK-NEXT: setp.gt.f64 %p1, %rd1, 0d0000000000000000;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB8_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB8_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB8_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB8_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp ogt double %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ule double %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float64_oge(double %arg) {
-; CHECK-LABEL: test_float64_oge(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_oge_param_0];
-; CHECK-NEXT: setp.ge.f64 %p1, %rd1, 0d0000000000000000;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB9_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB9_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB9_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB9_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp oge double %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ult double %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float64_ult(double %arg) {
-; CHECK-LABEL: test_float64_ult(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ult_param_0];
-; CHECK-NEXT: setp.ltu.f64 %p1, %rd1, 0d0000000000000000;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB10_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB10_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB10_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB10_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp ult double %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp oge double %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float64_ule(double %arg) {
-; CHECK-LABEL: test_float64_ule(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ule_param_0];
-; CHECK-NEXT: setp.leu.f64 %p1, %rd1, 0d0000000000000000;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB11_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB11_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB11_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB11_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp ule double %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ogt double %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float64_ugt(double %arg) {
-; CHECK-LABEL: test_float64_ugt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ugt_param_0];
-; CHECK-NEXT: setp.gtu.f64 %p1, %rd1, 0d0000000000000000;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB12_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB12_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB12_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB12_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp ugt double %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ole double %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float64_uge(double %arg) {
-; CHECK-LABEL: test_float64_uge(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_uge_param_0];
-; CHECK-NEXT: setp.geu.f64 %p1, %rd1, 0d0000000000000000;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB13_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB13_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB13_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB13_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp uge double %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp olt double %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float64_ord(double %arg) {
-; CHECK-LABEL: test_float64_ord(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ord_param_0];
-; CHECK-NEXT: setp.num.f64 %p1, %rd1, %rd1;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @!%p1 bra $L__BB14_1;
-; CHECK-NEXT: $L__BB14_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB14_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB14_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-; CHECK-NEXT: $L__BB14_1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: bra.uni $L__BB14_2;
-entry:
- %cmp = fcmp ord double %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp uno double %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float64_uno(double %arg) {
-; CHECK-LABEL: test_float64_uno(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_uno_param_0];
-; CHECK-NEXT: setp.nan.f64 %p1, %rd1, %rd1;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB15_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB15_2: // %merge1
-; CHECK-NEXT: @%p1 bra $L__BB15_3;
-; CHECK-NEXT: $L__BB15_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-; CHECK-NEXT: $L__BB15_3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: bra.uni $L__BB15_4;
-entry:
- %cmp = fcmp uno double %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ord double %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-int16.ll b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-int16.ll
deleted file mode 100644
index 2cb3fa6110c18..0000000000000
--- a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-int16.ll
+++ /dev/null
@@ -1,437 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -march=nvptx64 -mcpu=sm_100 -O2 < %s | FileCheck %s
-; RUN: %if ptxas-sm_100 %{ llc < %s -march=nvptx64 -mcpu=sm_100 -O2 | %ptxas-verify -arch=sm_100 %}
-
-target triple = "nvptx64-nvidia-cuda"
-
-; Test int16 integer comparison inversions
-
-define i32 @test_int16_eq(i16 %a, i16 %b) {
-; CHECK-LABEL: test_int16_eq(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_eq_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_eq_param_0];
-; CHECK-NEXT: setp.eq.b16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB0_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB0_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB0_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB0_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp eq i16 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp ne i16 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int16_ne(i16 %a, i16 %b) {
-; CHECK-LABEL: test_int16_ne(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_ne_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_ne_param_0];
-; CHECK-NEXT: setp.ne.b16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB1_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB1_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB1_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB1_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp ne i16 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp eq i16 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int16_slt(i16 %a, i16 %b) {
-; CHECK-LABEL: test_int16_slt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_slt_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_slt_param_0];
-; CHECK-NEXT: setp.lt.s16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB2_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB2_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB2_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB2_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp slt i16 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp sge i16 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int16_sle(i16 %a, i16 %b) {
-; CHECK-LABEL: test_int16_sle(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_sle_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_sle_param_0];
-; CHECK-NEXT: setp.le.s16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB3_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB3_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB3_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB3_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp sle i16 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp sgt i16 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int16_sgt(i16 %a, i16 %b) {
-; CHECK-LABEL: test_int16_sgt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_sgt_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_sgt_param_0];
-; CHECK-NEXT: setp.gt.s16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB4_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB4_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB4_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB4_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp sgt i16 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp sle i16 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int16_sge(i16 %a, i16 %b) {
-; CHECK-LABEL: test_int16_sge(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_sge_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_sge_param_0];
-; CHECK-NEXT: setp.ge.s16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB5_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB5_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB5_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB5_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp sge i16 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp slt i16 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int16_ult(i16 %a, i16 %b) {
-; CHECK-LABEL: test_int16_ult(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_ult_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_ult_param_0];
-; CHECK-NEXT: setp.lt.u16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB6_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB6_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB6_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB6_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp ult i16 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp uge i16 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int16_ule(i16 %a, i16 %b) {
-; CHECK-LABEL: test_int16_ule(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_ule_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_ule_param_0];
-; CHECK-NEXT: setp.le.u16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB7_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB7_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB7_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB7_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp ule i16 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp ugt i16 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int16_ugt(i16 %a, i16 %b) {
-; CHECK-LABEL: test_int16_ugt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_ugt_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_ugt_param_0];
-; CHECK-NEXT: setp.gt.u16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB8_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB8_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB8_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB8_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp ugt i16 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp ule i16 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int16_uge(i16 %a, i16 %b) {
-; CHECK-LABEL: test_int16_uge(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_uge_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_uge_param_0];
-; CHECK-NEXT: setp.ge.u16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB9_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB9_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB9_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB9_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp uge i16 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp ult i16 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-int32.ll b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-int32.ll
deleted file mode 100644
index 4d1f7c97fe594..0000000000000
--- a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-int32.ll
+++ /dev/null
@@ -1,427 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -march=nvptx64 -mcpu=sm_100 -O2 < %s | FileCheck %s
-; RUN: %if ptxas-sm_100 %{ llc < %s -march=nvptx64 -mcpu=sm_100 -O2 | %ptxas-verify -arch=sm_100 %}
-
-target triple = "nvptx64-nvidia-cuda"
-
-; Test int32 integer comparison inversions
-
-define i32 @test_int32_eq(i32 %a, i32 %b) {
-; CHECK-LABEL: test_int32_eq(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<4>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r2, [test_int32_eq_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_int32_eq_param_0];
-; CHECK-NEXT: setp.eq.b32 %p1, %r1, %r2;
-; CHECK-NEXT: mov.b32 %r3, 0;
-; CHECK-NEXT: @%p1 bra $L__BB0_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r3, 1;
-; CHECK-NEXT: $L__BB0_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB0_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r3, 0;
-; CHECK-NEXT: $L__BB0_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp eq i32 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp ne i32 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int32_ne(i32 %a, i32 %b) {
-; CHECK-LABEL: test_int32_ne(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<4>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r2, [test_int32_ne_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_int32_ne_param_0];
-; CHECK-NEXT: setp.ne.b32 %p1, %r1, %r2;
-; CHECK-NEXT: mov.b32 %r3, 0;
-; CHECK-NEXT: @%p1 bra $L__BB1_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r3, 1;
-; CHECK-NEXT: $L__BB1_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB1_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r3, 0;
-; CHECK-NEXT: $L__BB1_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp ne i32 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp eq i32 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int32_slt(i32 %a, i32 %b) {
-; CHECK-LABEL: test_int32_slt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<4>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r2, [test_int32_slt_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_int32_slt_param_0];
-; CHECK-NEXT: setp.lt.s32 %p1, %r1, %r2;
-; CHECK-NEXT: mov.b32 %r3, 0;
-; CHECK-NEXT: @%p1 bra $L__BB2_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r3, 1;
-; CHECK-NEXT: $L__BB2_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB2_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r3, 0;
-; CHECK-NEXT: $L__BB2_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp slt i32 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp sge i32 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int32_sle(i32 %a, i32 %b) {
-; CHECK-LABEL: test_int32_sle(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<4>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r2, [test_int32_sle_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_int32_sle_param_0];
-; CHECK-NEXT: setp.le.s32 %p1, %r1, %r2;
-; CHECK-NEXT: mov.b32 %r3, 0;
-; CHECK-NEXT: @%p1 bra $L__BB3_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r3, 1;
-; CHECK-NEXT: $L__BB3_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB3_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r3, 0;
-; CHECK-NEXT: $L__BB3_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp sle i32 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp sgt i32 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int32_sgt(i32 %a, i32 %b) {
-; CHECK-LABEL: test_int32_sgt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<4>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r2, [test_int32_sgt_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_int32_sgt_param_0];
-; CHECK-NEXT: setp.gt.s32 %p1, %r1, %r2;
-; CHECK-NEXT: mov.b32 %r3, 0;
-; CHECK-NEXT: @%p1 bra $L__BB4_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r3, 1;
-; CHECK-NEXT: $L__BB4_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB4_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r3, 0;
-; CHECK-NEXT: $L__BB4_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp sgt i32 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp sle i32 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int32_sge(i32 %a, i32 %b) {
-; CHECK-LABEL: test_int32_sge(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<4>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r2, [test_int32_sge_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_int32_sge_param_0];
-; CHECK-NEXT: setp.ge.s32 %p1, %r1, %r2;
-; CHECK-NEXT: mov.b32 %r3, 0;
-; CHECK-NEXT: @%p1 bra $L__BB5_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r3, 1;
-; CHECK-NEXT: $L__BB5_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB5_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r3, 0;
-; CHECK-NEXT: $L__BB5_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp sge i32 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp slt i32 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int32_ult(i32 %a, i32 %b) {
-; CHECK-LABEL: test_int32_ult(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<4>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r2, [test_int32_ult_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_int32_ult_param_0];
-; CHECK-NEXT: setp.lt.u32 %p1, %r1, %r2;
-; CHECK-NEXT: mov.b32 %r3, 0;
-; CHECK-NEXT: @%p1 bra $L__BB6_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r3, 1;
-; CHECK-NEXT: $L__BB6_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB6_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r3, 0;
-; CHECK-NEXT: $L__BB6_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp ult i32 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp uge i32 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int32_ule(i32 %a, i32 %b) {
-; CHECK-LABEL: test_int32_ule(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<4>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r2, [test_int32_ule_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_int32_ule_param_0];
-; CHECK-NEXT: setp.le.u32 %p1, %r1, %r2;
-; CHECK-NEXT: mov.b32 %r3, 0;
-; CHECK-NEXT: @%p1 bra $L__BB7_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r3, 1;
-; CHECK-NEXT: $L__BB7_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB7_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r3, 0;
-; CHECK-NEXT: $L__BB7_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp ule i32 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp ugt i32 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int32_ugt(i32 %a, i32 %b) {
-; CHECK-LABEL: test_int32_ugt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<4>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r2, [test_int32_ugt_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_int32_ugt_param_0];
-; CHECK-NEXT: setp.gt.u32 %p1, %r1, %r2;
-; CHECK-NEXT: mov.b32 %r3, 0;
-; CHECK-NEXT: @%p1 bra $L__BB8_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r3, 1;
-; CHECK-NEXT: $L__BB8_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB8_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r3, 0;
-; CHECK-NEXT: $L__BB8_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp ugt i32 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp ule i32 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int32_uge(i32 %a, i32 %b) {
-; CHECK-LABEL: test_int32_uge(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<4>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r2, [test_int32_uge_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_int32_uge_param_0];
-; CHECK-NEXT: setp.ge.u32 %p1, %r1, %r2;
-; CHECK-NEXT: mov.b32 %r3, 0;
-; CHECK-NEXT: @%p1 bra $L__BB9_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r3, 1;
-; CHECK-NEXT: $L__BB9_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB9_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r3, 0;
-; CHECK-NEXT: $L__BB9_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp uge i32 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp ult i32 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-int64.ll b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-int64.ll
deleted file mode 100644
index bc90ea4335d2e..0000000000000
--- a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-int64.ll
+++ /dev/null
@@ -1,437 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -march=nvptx64 -mcpu=sm_100 -O2 < %s | FileCheck %s
-; RUN: %if ptxas-sm_100 %{ llc < %s -march=nvptx64 -mcpu=sm_100 -O2 | %ptxas-verify -arch=sm_100 %}
-
-target triple = "nvptx64-nvidia-cuda"
-
-; Test int64 integer comparison inversions
-
-define i32 @test_int64_eq(i64 %a, i64 %b) {
-; CHECK-LABEL: test_int64_eq(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_eq_param_1];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_eq_param_0];
-; CHECK-NEXT: setp.eq.b64 %p1, %rd1, %rd2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB0_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB0_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB0_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB0_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp eq i64 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp ne i64 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int64_ne(i64 %a, i64 %b) {
-; CHECK-LABEL: test_int64_ne(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_ne_param_1];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_ne_param_0];
-; CHECK-NEXT: setp.ne.b64 %p1, %rd1, %rd2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB1_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB1_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB1_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB1_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp ne i64 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp eq i64 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int64_slt(i64 %a, i64 %b) {
-; CHECK-LABEL: test_int64_slt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_slt_param_1];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_slt_param_0];
-; CHECK-NEXT: setp.lt.s64 %p1, %rd1, %rd2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB2_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB2_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB2_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB2_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp slt i64 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp sge i64 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int64_sle(i64 %a, i64 %b) {
-; CHECK-LABEL: test_int64_sle(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_sle_param_1];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_sle_param_0];
-; CHECK-NEXT: setp.le.s64 %p1, %rd1, %rd2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB3_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB3_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB3_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB3_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp sle i64 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp sgt i64 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int64_sgt(i64 %a, i64 %b) {
-; CHECK-LABEL: test_int64_sgt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_sgt_param_1];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_sgt_param_0];
-; CHECK-NEXT: setp.gt.s64 %p1, %rd1, %rd2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB4_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB4_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB4_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB4_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp sgt i64 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp sle i64 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int64_sge(i64 %a, i64 %b) {
-; CHECK-LABEL: test_int64_sge(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_sge_param_1];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_sge_param_0];
-; CHECK-NEXT: setp.ge.s64 %p1, %rd1, %rd2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB5_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB5_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB5_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB5_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp sge i64 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp slt i64 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int64_ult(i64 %a, i64 %b) {
-; CHECK-LABEL: test_int64_ult(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_ult_param_1];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_ult_param_0];
-; CHECK-NEXT: setp.lt.u64 %p1, %rd1, %rd2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB6_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB6_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB6_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB6_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp ult i64 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp uge i64 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int64_ule(i64 %a, i64 %b) {
-; CHECK-LABEL: test_int64_ule(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_ule_param_1];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_ule_param_0];
-; CHECK-NEXT: setp.le.u64 %p1, %rd1, %rd2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB7_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB7_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB7_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB7_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp ule i64 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp ugt i64 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int64_ugt(i64 %a, i64 %b) {
-; CHECK-LABEL: test_int64_ugt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_ugt_param_1];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_ugt_param_0];
-; CHECK-NEXT: setp.gt.u64 %p1, %rd1, %rd2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB8_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB8_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB8_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB8_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp ugt i64 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp ule i64 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int64_uge(i64 %a, i64 %b) {
-; CHECK-LABEL: test_int64_uge(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_uge_param_1];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_uge_param_0];
-; CHECK-NEXT: setp.ge.u64 %p1, %rd1, %rd2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB9_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB9_2: // %merge1
-; CHECK-NEXT: @!%p1 bra $L__BB9_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB9_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp uge i64 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp ult i64 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-multiple-users.ll b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-multiple-users.ll
index 7b71053758147..675285a068d47 100644
--- a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-multiple-users.ll
+++ b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion-multiple-users.ll
@@ -2,6 +2,8 @@
; RUN: llc -march=nvptx64 -mcpu=sm_100 -O2 < %s | FileCheck %s
; RUN: %if ptxas-sm_100 %{ llc < %s -march=nvptx64 -mcpu=sm_100 -O2 | %ptxas-verify -arch=sm_100 %}
+; NOTE: Currently SETP inversions require all users to be CBranch. However other users like selects
+; can also be processed.
target triple = "nvptx64-nvidia-cuda"
define i32 @test_multiple_users(i32 %a, i32 %b) {
@@ -21,7 +23,7 @@ define i32 @test_multiple_users(i32 %a, i32 %b) {
; CHECK-NEXT: $L__BB0_2: // %merge1
; CHECK-NEXT: setp.ne.b32 %p2, %r2, %r3;
; CHECK-NEXT: selp.b32 %r1, 1, 0, %p2;
-; CHECK-NEXT: @%p1 bra $L__BB0_4;
+; CHECK-NEXT: @%p2 bra $L__BB0_4;
; CHECK-NEXT: // %bb.3: // %else
; CHECK-NEXT: mov.b32 %r5, 0;
; CHECK-NEXT: $L__BB0_4: // %merge2
@@ -40,7 +42,7 @@ merge1:
%phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
%cmp2 = icmp ne i32 %a, %b
%val = select i1 %cmp2, i32 1, i32 0
- br i1 %cmp2, label %else, label %merge2
+ br i1 %cmp2, label %merge2, label %else
else:
br label %merge2
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion.ll b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion.ll
new file mode 100644
index 0000000000000..08bc3a8d64ea4
--- /dev/null
+++ b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-inversion.ll
@@ -0,0 +1,3997 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -march=nvptx64 -mcpu=sm_100 -O2 < %s | FileCheck %s
+; RUN: %if ptxas-sm_100 %{ llc < %s -march=nvptx64 -mcpu=sm_100 -O2 | %ptxas-verify -arch=sm_100 %}
+
+target triple = "nvptx64-nvidia-cuda"
+
+define i32 @test_int16_eq(i16 %a, i16 %b) {
+; CHECK-LABEL: test_int16_eq(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_eq_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_eq_param_0];
+; CHECK-NEXT: setp.eq.b16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB0_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB0_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB0_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB0_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp eq i16 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp ne i16 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int16_ne(i16 %a, i16 %b) {
+; CHECK-LABEL: test_int16_ne(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_ne_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_ne_param_0];
+; CHECK-NEXT: setp.ne.b16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB1_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB1_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB1_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB1_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp ne i16 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp eq i16 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int16_slt(i16 %a, i16 %b) {
+; CHECK-LABEL: test_int16_slt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_slt_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_slt_param_0];
+; CHECK-NEXT: setp.lt.s16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB2_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB2_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB2_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB2_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp slt i16 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp sge i16 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int16_sle(i16 %a, i16 %b) {
+; CHECK-LABEL: test_int16_sle(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_sle_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_sle_param_0];
+; CHECK-NEXT: setp.le.s16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB3_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB3_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB3_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB3_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp sle i16 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp sgt i16 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int16_sgt(i16 %a, i16 %b) {
+; CHECK-LABEL: test_int16_sgt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_sgt_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_sgt_param_0];
+; CHECK-NEXT: setp.gt.s16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB4_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB4_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB4_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB4_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp sgt i16 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp sle i16 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int16_sge(i16 %a, i16 %b) {
+; CHECK-LABEL: test_int16_sge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_sge_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_sge_param_0];
+; CHECK-NEXT: setp.ge.s16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB5_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB5_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB5_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB5_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp sge i16 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp slt i16 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int16_ult(i16 %a, i16 %b) {
+; CHECK-LABEL: test_int16_ult(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_ult_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_ult_param_0];
+; CHECK-NEXT: setp.lt.u16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB6_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB6_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB6_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB6_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp ult i16 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp uge i16 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int16_ule(i16 %a, i16 %b) {
+; CHECK-LABEL: test_int16_ule(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_ule_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_ule_param_0];
+; CHECK-NEXT: setp.le.u16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB7_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB7_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB7_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB7_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp ule i16 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp ugt i16 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int16_ugt(i16 %a, i16 %b) {
+; CHECK-LABEL: test_int16_ugt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_ugt_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_ugt_param_0];
+; CHECK-NEXT: setp.gt.u16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB8_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB8_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB8_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB8_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp ugt i16 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp ule i16 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int16_uge(i16 %a, i16 %b) {
+; CHECK-LABEL: test_int16_uge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_uge_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_uge_param_0];
+; CHECK-NEXT: setp.ge.u16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB9_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB9_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB9_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB9_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp uge i16 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp ult i16 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int32_eq(i32 %a, i32 %b) {
+; CHECK-LABEL: test_int32_eq(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r2, [test_int32_eq_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_int32_eq_param_0];
+; CHECK-NEXT: setp.eq.b32 %p1, %r1, %r2;
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: @%p1 bra $L__BB10_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r3, 1;
+; CHECK-NEXT: $L__BB10_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB10_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: $L__BB10_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp eq i32 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp ne i32 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int32_ne(i32 %a, i32 %b) {
+; CHECK-LABEL: test_int32_ne(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r2, [test_int32_ne_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_int32_ne_param_0];
+; CHECK-NEXT: setp.ne.b32 %p1, %r1, %r2;
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: @%p1 bra $L__BB11_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r3, 1;
+; CHECK-NEXT: $L__BB11_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB11_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: $L__BB11_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp ne i32 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp eq i32 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int32_slt(i32 %a, i32 %b) {
+; CHECK-LABEL: test_int32_slt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r2, [test_int32_slt_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_int32_slt_param_0];
+; CHECK-NEXT: setp.lt.s32 %p1, %r1, %r2;
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: @%p1 bra $L__BB12_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r3, 1;
+; CHECK-NEXT: $L__BB12_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB12_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: $L__BB12_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp slt i32 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp sge i32 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int32_sle(i32 %a, i32 %b) {
+; CHECK-LABEL: test_int32_sle(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r2, [test_int32_sle_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_int32_sle_param_0];
+; CHECK-NEXT: setp.le.s32 %p1, %r1, %r2;
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: @%p1 bra $L__BB13_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r3, 1;
+; CHECK-NEXT: $L__BB13_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB13_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: $L__BB13_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp sle i32 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp sgt i32 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int32_sgt(i32 %a, i32 %b) {
+; CHECK-LABEL: test_int32_sgt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r2, [test_int32_sgt_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_int32_sgt_param_0];
+; CHECK-NEXT: setp.gt.s32 %p1, %r1, %r2;
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: @%p1 bra $L__BB14_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r3, 1;
+; CHECK-NEXT: $L__BB14_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB14_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: $L__BB14_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp sgt i32 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp sle i32 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int32_sge(i32 %a, i32 %b) {
+; CHECK-LABEL: test_int32_sge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r2, [test_int32_sge_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_int32_sge_param_0];
+; CHECK-NEXT: setp.ge.s32 %p1, %r1, %r2;
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: @%p1 bra $L__BB15_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r3, 1;
+; CHECK-NEXT: $L__BB15_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB15_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: $L__BB15_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp sge i32 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp slt i32 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int32_ult(i32 %a, i32 %b) {
+; CHECK-LABEL: test_int32_ult(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r2, [test_int32_ult_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_int32_ult_param_0];
+; CHECK-NEXT: setp.lt.u32 %p1, %r1, %r2;
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: @%p1 bra $L__BB16_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r3, 1;
+; CHECK-NEXT: $L__BB16_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB16_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: $L__BB16_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp ult i32 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp uge i32 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int32_ule(i32 %a, i32 %b) {
+; CHECK-LABEL: test_int32_ule(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r2, [test_int32_ule_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_int32_ule_param_0];
+; CHECK-NEXT: setp.le.u32 %p1, %r1, %r2;
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: @%p1 bra $L__BB17_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r3, 1;
+; CHECK-NEXT: $L__BB17_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB17_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: $L__BB17_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp ule i32 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp ugt i32 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int32_ugt(i32 %a, i32 %b) {
+; CHECK-LABEL: test_int32_ugt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r2, [test_int32_ugt_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_int32_ugt_param_0];
+; CHECK-NEXT: setp.gt.u32 %p1, %r1, %r2;
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: @%p1 bra $L__BB18_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r3, 1;
+; CHECK-NEXT: $L__BB18_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB18_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: $L__BB18_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp ugt i32 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp ule i32 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int32_uge(i32 %a, i32 %b) {
+; CHECK-LABEL: test_int32_uge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r2, [test_int32_uge_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_int32_uge_param_0];
+; CHECK-NEXT: setp.ge.u32 %p1, %r1, %r2;
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: @%p1 bra $L__BB19_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r3, 1;
+; CHECK-NEXT: $L__BB19_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB19_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: $L__BB19_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp uge i32 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp ult i32 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int64_eq(i64 %a, i64 %b) {
+; CHECK-LABEL: test_int64_eq(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_eq_param_1];
+; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_eq_param_0];
+; CHECK-NEXT: setp.eq.b64 %p1, %rd1, %rd2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB20_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB20_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB20_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB20_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp eq i64 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp ne i64 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int64_ne(i64 %a, i64 %b) {
+; CHECK-LABEL: test_int64_ne(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_ne_param_1];
+; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_ne_param_0];
+; CHECK-NEXT: setp.ne.b64 %p1, %rd1, %rd2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB21_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB21_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB21_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB21_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp ne i64 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp eq i64 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int64_slt(i64 %a, i64 %b) {
+; CHECK-LABEL: test_int64_slt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_slt_param_1];
+; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_slt_param_0];
+; CHECK-NEXT: setp.lt.s64 %p1, %rd1, %rd2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB22_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB22_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB22_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB22_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp slt i64 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp sge i64 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int64_sle(i64 %a, i64 %b) {
+; CHECK-LABEL: test_int64_sle(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_sle_param_1];
+; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_sle_param_0];
+; CHECK-NEXT: setp.le.s64 %p1, %rd1, %rd2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB23_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB23_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB23_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB23_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp sle i64 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp sgt i64 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int64_sgt(i64 %a, i64 %b) {
+; CHECK-LABEL: test_int64_sgt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_sgt_param_1];
+; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_sgt_param_0];
+; CHECK-NEXT: setp.gt.s64 %p1, %rd1, %rd2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB24_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB24_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB24_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB24_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp sgt i64 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp sle i64 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int64_sge(i64 %a, i64 %b) {
+; CHECK-LABEL: test_int64_sge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_sge_param_1];
+; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_sge_param_0];
+; CHECK-NEXT: setp.ge.s64 %p1, %rd1, %rd2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB25_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB25_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB25_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB25_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp sge i64 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp slt i64 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int64_ult(i64 %a, i64 %b) {
+; CHECK-LABEL: test_int64_ult(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_ult_param_1];
+; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_ult_param_0];
+; CHECK-NEXT: setp.lt.u64 %p1, %rd1, %rd2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB26_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB26_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB26_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB26_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp ult i64 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp uge i64 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int64_ule(i64 %a, i64 %b) {
+; CHECK-LABEL: test_int64_ule(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_ule_param_1];
+; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_ule_param_0];
+; CHECK-NEXT: setp.le.u64 %p1, %rd1, %rd2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB27_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB27_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB27_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB27_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp ule i64 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp ugt i64 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int64_ugt(i64 %a, i64 %b) {
+; CHECK-LABEL: test_int64_ugt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_ugt_param_1];
+; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_ugt_param_0];
+; CHECK-NEXT: setp.gt.u64 %p1, %rd1, %rd2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB28_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB28_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB28_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB28_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp ugt i64 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp ule i64 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int64_uge(i64 %a, i64 %b) {
+; CHECK-LABEL: test_int64_uge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_uge_param_1];
+; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_uge_param_0];
+; CHECK-NEXT: setp.ge.u64 %p1, %rd1, %rd2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB29_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB29_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB29_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB29_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp uge i64 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp ult i64 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_eq(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_eq(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_eq_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_eq_param_0];
+; CHECK-NEXT: setp.eq.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB30_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB30_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB30_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB30_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oeq bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp une bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_ne(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_ne(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ne_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ne_param_0];
+; CHECK-NEXT: setp.ne.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB31_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB31_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB31_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB31_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp one bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ueq bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_oeq(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_oeq(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_oeq_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_oeq_param_0];
+; CHECK-NEXT: setp.eq.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB32_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB32_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB32_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB32_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oeq bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp une bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_one(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_one(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_one_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_one_param_0];
+; CHECK-NEXT: setp.ne.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB33_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB33_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB33_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB33_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp one bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ueq bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_ueq(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_ueq(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ueq_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ueq_param_0];
+; CHECK-NEXT: setp.equ.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB34_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB34_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB34_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB34_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ueq bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp one bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_une(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_une(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_une_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_une_param_0];
+; CHECK-NEXT: setp.neu.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB35_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB35_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB35_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB35_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp une bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp oeq bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_olt(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_olt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_olt_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_olt_param_0];
+; CHECK-NEXT: setp.lt.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB36_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB36_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB36_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB36_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp olt bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp uge bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_ole(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_ole(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ole_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ole_param_0];
+; CHECK-NEXT: setp.le.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB37_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB37_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB37_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB37_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ole bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ugt bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_ogt(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_ogt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ogt_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ogt_param_0];
+; CHECK-NEXT: setp.gt.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB38_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB38_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB38_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB38_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ogt bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ule bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_oge(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_oge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_oge_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_oge_param_0];
+; CHECK-NEXT: setp.ge.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB39_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB39_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB39_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB39_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oge bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ult bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_ult(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_ult(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ult_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ult_param_0];
+; CHECK-NEXT: setp.ltu.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB40_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB40_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB40_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB40_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ult bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp oge bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_ule(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_ule(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ule_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ule_param_0];
+; CHECK-NEXT: setp.leu.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB41_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB41_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB41_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB41_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ule bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ogt bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_ugt(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_ugt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ugt_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ugt_param_0];
+; CHECK-NEXT: setp.gtu.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB42_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB42_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB42_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB42_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ugt bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ole bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_uge(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_uge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_uge_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_uge_param_0];
+; CHECK-NEXT: setp.geu.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB43_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB43_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB43_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB43_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp uge bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp olt bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_ord(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_ord(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ord_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ord_param_0];
+; CHECK-NEXT: setp.num.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @!%p1 bra $L__BB44_1;
+; CHECK-NEXT: $L__BB44_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB44_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB44_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+; CHECK-NEXT: $L__BB44_1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: bra.uni $L__BB44_2;
+entry:
+ %cmp = fcmp ord bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp uno bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_uno(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_uno(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_uno_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_uno_param_0];
+; CHECK-NEXT: setp.nan.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB45_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB45_2: // %merge1
+; CHECK-NEXT: @%p1 bra $L__BB45_3;
+; CHECK-NEXT: $L__BB45_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+; CHECK-NEXT: $L__BB45_3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: bra.uni $L__BB45_4;
+entry:
+ %cmp = fcmp uno bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ord bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_eq(half %a, half %b) {
+; CHECK-LABEL: test_float16_eq(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_eq_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_eq_param_0];
+; CHECK-NEXT: setp.eq.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB46_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB46_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB46_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB46_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oeq half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp une half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_ne(half %a, half %b) {
+; CHECK-LABEL: test_float16_ne(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ne_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ne_param_0];
+; CHECK-NEXT: setp.ne.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB47_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB47_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB47_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB47_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp one half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ueq half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_oeq(half %a, half %b) {
+; CHECK-LABEL: test_float16_oeq(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_oeq_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_oeq_param_0];
+; CHECK-NEXT: setp.eq.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB48_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB48_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB48_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB48_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oeq half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp une half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_one(half %a, half %b) {
+; CHECK-LABEL: test_float16_one(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_one_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_one_param_0];
+; CHECK-NEXT: setp.ne.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB49_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB49_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB49_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB49_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp one half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ueq half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_ueq(half %a, half %b) {
+; CHECK-LABEL: test_float16_ueq(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ueq_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ueq_param_0];
+; CHECK-NEXT: setp.equ.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB50_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB50_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB50_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB50_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ueq half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp one half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_une(half %a, half %b) {
+; CHECK-LABEL: test_float16_une(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_une_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_une_param_0];
+; CHECK-NEXT: setp.neu.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB51_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB51_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB51_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB51_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp une half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp oeq half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_olt(half %a, half %b) {
+; CHECK-LABEL: test_float16_olt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_olt_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_olt_param_0];
+; CHECK-NEXT: setp.lt.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB52_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB52_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB52_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB52_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp olt half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp uge half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_ole(half %a, half %b) {
+; CHECK-LABEL: test_float16_ole(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ole_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ole_param_0];
+; CHECK-NEXT: setp.le.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB53_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB53_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB53_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB53_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ole half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ugt half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_ogt(half %a, half %b) {
+; CHECK-LABEL: test_float16_ogt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ogt_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ogt_param_0];
+; CHECK-NEXT: setp.gt.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB54_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB54_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB54_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB54_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ogt half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ule half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_oge(half %a, half %b) {
+; CHECK-LABEL: test_float16_oge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_oge_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_oge_param_0];
+; CHECK-NEXT: setp.ge.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB55_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB55_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB55_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB55_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oge half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ult half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_ult(half %a, half %b) {
+; CHECK-LABEL: test_float16_ult(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ult_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ult_param_0];
+; CHECK-NEXT: setp.ltu.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB56_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB56_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB56_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB56_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ult half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp oge half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_ule(half %a, half %b) {
+; CHECK-LABEL: test_float16_ule(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ule_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ule_param_0];
+; CHECK-NEXT: setp.leu.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB57_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB57_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB57_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB57_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ule half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ogt half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_ugt(half %a, half %b) {
+; CHECK-LABEL: test_float16_ugt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ugt_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ugt_param_0];
+; CHECK-NEXT: setp.gtu.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB58_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB58_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB58_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB58_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ugt half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ole half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_uge(half %a, half %b) {
+; CHECK-LABEL: test_float16_uge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_uge_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_uge_param_0];
+; CHECK-NEXT: setp.geu.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB59_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB59_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB59_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB59_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp uge half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp olt half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_ord(half %a, half %b) {
+; CHECK-LABEL: test_float16_ord(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ord_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ord_param_0];
+; CHECK-NEXT: setp.num.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @!%p1 bra $L__BB60_1;
+; CHECK-NEXT: $L__BB60_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB60_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB60_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+; CHECK-NEXT: $L__BB60_1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: bra.uni $L__BB60_2;
+entry:
+ %cmp = fcmp ord half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp uno half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_uno(half %a, half %b) {
+; CHECK-LABEL: test_float16_uno(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_uno_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_uno_param_0];
+; CHECK-NEXT: setp.nan.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB61_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB61_2: // %merge1
+; CHECK-NEXT: @%p1 bra $L__BB61_3;
+; CHECK-NEXT: $L__BB61_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+; CHECK-NEXT: $L__BB61_3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: bra.uni $L__BB61_4;
+entry:
+ %cmp = fcmp uno half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ord half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_eq(float %arg) {
+; CHECK-LABEL: test_float32_eq(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_eq_param_0];
+; CHECK-NEXT: setp.eq.f32 %p1, %r1, 0f00000000;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB62_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB62_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB62_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB62_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oeq float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp une float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_ne(float %arg) {
+; CHECK-LABEL: test_float32_ne(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ne_param_0];
+; CHECK-NEXT: setp.ne.f32 %p1, %r1, 0f00000000;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB63_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB63_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB63_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB63_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp one float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ueq float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_oeq(float %arg) {
+; CHECK-LABEL: test_float32_oeq(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_oeq_param_0];
+; CHECK-NEXT: setp.eq.f32 %p1, %r1, 0f00000000;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB64_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB64_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB64_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB64_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oeq float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp une float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_one(float %arg) {
+; CHECK-LABEL: test_float32_one(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_one_param_0];
+; CHECK-NEXT: setp.ne.f32 %p1, %r1, 0f00000000;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB65_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB65_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB65_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB65_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp one float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ueq float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_ueq(float %arg) {
+; CHECK-LABEL: test_float32_ueq(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ueq_param_0];
+; CHECK-NEXT: setp.equ.f32 %p1, %r1, 0f00000000;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB66_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB66_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB66_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB66_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ueq float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp one float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_une(float %arg) {
+; CHECK-LABEL: test_float32_une(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_une_param_0];
+; CHECK-NEXT: setp.neu.f32 %p1, %r1, 0f00000000;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB67_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB67_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB67_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB67_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp une float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp oeq float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_olt(float %arg) {
+; CHECK-LABEL: test_float32_olt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_olt_param_0];
+; CHECK-NEXT: setp.lt.f32 %p1, %r1, 0f00000000;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB68_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB68_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB68_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB68_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp olt float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp uge float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_ole(float %arg) {
+; CHECK-LABEL: test_float32_ole(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ole_param_0];
+; CHECK-NEXT: setp.le.f32 %p1, %r1, 0f00000000;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB69_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB69_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB69_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB69_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ole float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ugt float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_ogt(float %arg) {
+; CHECK-LABEL: test_float32_ogt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ogt_param_0];
+; CHECK-NEXT: setp.gt.f32 %p1, %r1, 0f00000000;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB70_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB70_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB70_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB70_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ogt float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ule float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_oge(float %arg) {
+; CHECK-LABEL: test_float32_oge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_oge_param_0];
+; CHECK-NEXT: setp.ge.f32 %p1, %r1, 0f00000000;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB71_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB71_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB71_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB71_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oge float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ult float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_ult(float %arg) {
+; CHECK-LABEL: test_float32_ult(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ult_param_0];
+; CHECK-NEXT: setp.ltu.f32 %p1, %r1, 0f00000000;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB72_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB72_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB72_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB72_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ult float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp oge float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_ule(float %arg) {
+; CHECK-LABEL: test_float32_ule(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ule_param_0];
+; CHECK-NEXT: setp.leu.f32 %p1, %r1, 0f00000000;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB73_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB73_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB73_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB73_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ule float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ogt float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_ugt(float %arg) {
+; CHECK-LABEL: test_float32_ugt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ugt_param_0];
+; CHECK-NEXT: setp.gtu.f32 %p1, %r1, 0f00000000;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB74_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB74_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB74_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB74_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ugt float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ole float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_uge(float %arg) {
+; CHECK-LABEL: test_float32_uge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_uge_param_0];
+; CHECK-NEXT: setp.geu.f32 %p1, %r1, 0f00000000;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB75_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB75_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB75_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB75_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp uge float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp olt float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_ord(float %arg) {
+; CHECK-LABEL: test_float32_ord(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ord_param_0];
+; CHECK-NEXT: setp.num.f32 %p1, %r1, %r1;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @!%p1 bra $L__BB76_1;
+; CHECK-NEXT: $L__BB76_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB76_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB76_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+; CHECK-NEXT: $L__BB76_1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: bra.uni $L__BB76_2;
+entry:
+ %cmp = fcmp ord float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp uno float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_uno(float %arg) {
+; CHECK-LABEL: test_float32_uno(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_uno_param_0];
+; CHECK-NEXT: setp.nan.f32 %p1, %r1, %r1;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB77_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB77_2: // %merge1
+; CHECK-NEXT: @%p1 bra $L__BB77_3;
+; CHECK-NEXT: $L__BB77_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+; CHECK-NEXT: $L__BB77_3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: bra.uni $L__BB77_4;
+entry:
+ %cmp = fcmp uno float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ord float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_eq(double %arg) {
+; CHECK-LABEL: test_float64_eq(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_eq_param_0];
+; CHECK-NEXT: setp.eq.f64 %p1, %rd1, 0d0000000000000000;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB78_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB78_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB78_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB78_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oeq double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp une double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_ne(double %arg) {
+; CHECK-LABEL: test_float64_ne(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ne_param_0];
+; CHECK-NEXT: setp.ne.f64 %p1, %rd1, 0d0000000000000000;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB79_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB79_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB79_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB79_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp one double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ueq double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_oeq(double %arg) {
+; CHECK-LABEL: test_float64_oeq(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_oeq_param_0];
+; CHECK-NEXT: setp.eq.f64 %p1, %rd1, 0d0000000000000000;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB80_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB80_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB80_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB80_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oeq double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp une double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_one(double %arg) {
+; CHECK-LABEL: test_float64_one(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_one_param_0];
+; CHECK-NEXT: setp.ne.f64 %p1, %rd1, 0d0000000000000000;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB81_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB81_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB81_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB81_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp one double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ueq double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_ueq(double %arg) {
+; CHECK-LABEL: test_float64_ueq(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ueq_param_0];
+; CHECK-NEXT: setp.equ.f64 %p1, %rd1, 0d0000000000000000;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB82_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB82_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB82_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB82_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ueq double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp one double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_une(double %arg) {
+; CHECK-LABEL: test_float64_une(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_une_param_0];
+; CHECK-NEXT: setp.neu.f64 %p1, %rd1, 0d0000000000000000;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB83_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB83_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB83_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB83_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp une double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp oeq double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_olt(double %arg) {
+; CHECK-LABEL: test_float64_olt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_olt_param_0];
+; CHECK-NEXT: setp.lt.f64 %p1, %rd1, 0d0000000000000000;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB84_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB84_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB84_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB84_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp olt double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp uge double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_ole(double %arg) {
+; CHECK-LABEL: test_float64_ole(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ole_param_0];
+; CHECK-NEXT: setp.le.f64 %p1, %rd1, 0d0000000000000000;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB85_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB85_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB85_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB85_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ole double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ugt double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_ogt(double %arg) {
+; CHECK-LABEL: test_float64_ogt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ogt_param_0];
+; CHECK-NEXT: setp.gt.f64 %p1, %rd1, 0d0000000000000000;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB86_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB86_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB86_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB86_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ogt double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ule double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_oge(double %arg) {
+; CHECK-LABEL: test_float64_oge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_oge_param_0];
+; CHECK-NEXT: setp.ge.f64 %p1, %rd1, 0d0000000000000000;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB87_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB87_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB87_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB87_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oge double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ult double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_ult(double %arg) {
+; CHECK-LABEL: test_float64_ult(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ult_param_0];
+; CHECK-NEXT: setp.ltu.f64 %p1, %rd1, 0d0000000000000000;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB88_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB88_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB88_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB88_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ult double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp oge double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_ule(double %arg) {
+; CHECK-LABEL: test_float64_ule(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ule_param_0];
+; CHECK-NEXT: setp.leu.f64 %p1, %rd1, 0d0000000000000000;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB89_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB89_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB89_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB89_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ule double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ogt double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_ugt(double %arg) {
+; CHECK-LABEL: test_float64_ugt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ugt_param_0];
+; CHECK-NEXT: setp.gtu.f64 %p1, %rd1, 0d0000000000000000;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB90_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB90_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB90_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB90_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ugt double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ole double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_uge(double %arg) {
+; CHECK-LABEL: test_float64_uge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_uge_param_0];
+; CHECK-NEXT: setp.geu.f64 %p1, %rd1, 0d0000000000000000;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB91_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB91_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB91_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB91_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp uge double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp olt double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_ord(double %arg) {
+; CHECK-LABEL: test_float64_ord(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ord_param_0];
+; CHECK-NEXT: setp.num.f64 %p1, %rd1, %rd1;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @!%p1 bra $L__BB92_1;
+; CHECK-NEXT: $L__BB92_2: // %merge1
+; CHECK-NEXT: @!%p1 bra $L__BB92_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB92_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+; CHECK-NEXT: $L__BB92_1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: bra.uni $L__BB92_2;
+entry:
+ %cmp = fcmp ord double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp uno double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_uno(double %arg) {
+; CHECK-LABEL: test_float64_uno(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_uno_param_0];
+; CHECK-NEXT: setp.nan.f64 %p1, %rd1, %rd1;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB93_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB93_2: // %merge1
+; CHECK-NEXT: @%p1 bra $L__BB93_3;
+; CHECK-NEXT: $L__BB93_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+; CHECK-NEXT: $L__BB93_3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: bra.uni $L__BB93_4;
+entry:
+ %cmp = fcmp uno double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ord double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-bfloat16.ll b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-bfloat16.ll
deleted file mode 100644
index 9e966e1843811..0000000000000
--- a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-bfloat16.ll
+++ /dev/null
@@ -1,224 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -march=nvptx64 -mcpu=sm_100 -O2 < %s | FileCheck %s
-
-target triple = "nvptx64-nvidia-cuda"
-
-define i32 @test_bfloat16_ueq_vs_une(bfloat %a, bfloat %b) {
-; CHECK-LABEL: test_bfloat16_ueq_vs_une(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<3>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ueq_vs_une_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ueq_vs_une_param_0];
-; CHECK-NEXT: setp.equ.bf16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB0_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB0_2: // %merge1
-; CHECK-NEXT: setp.neu.bf16 %p2, %rs1, %rs2;
-; CHECK-NEXT: @%p2 bra $L__BB0_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB0_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp ueq bfloat %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp une bfloat %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_bfloat16_oeq_vs_one(bfloat %a, bfloat %b) {
-; CHECK-LABEL: test_bfloat16_oeq_vs_one(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<3>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_oeq_vs_one_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_oeq_vs_one_param_0];
-; CHECK-NEXT: setp.eq.bf16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB1_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB1_2: // %merge1
-; CHECK-NEXT: setp.ne.bf16 %p2, %rs1, %rs2;
-; CHECK-NEXT: @%p2 bra $L__BB1_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB1_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp oeq bfloat %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp one bfloat %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_bfloat16_olt_vs_ogt(bfloat %a, bfloat %b) {
-; CHECK-LABEL: test_bfloat16_olt_vs_ogt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<3>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_olt_vs_ogt_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_olt_vs_ogt_param_0];
-; CHECK-NEXT: setp.lt.bf16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB2_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB2_2: // %merge1
-; CHECK-NEXT: setp.gt.bf16 %p2, %rs1, %rs2;
-; CHECK-NEXT: @%p2 bra $L__BB2_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB2_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp olt bfloat %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ogt bfloat %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_bfloat16_ult_vs_ugt(bfloat %a, bfloat %b) {
-; CHECK-LABEL: test_bfloat16_ult_vs_ugt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<3>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ult_vs_ugt_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ult_vs_ugt_param_0];
-; CHECK-NEXT: setp.ltu.bf16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB3_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB3_2: // %merge1
-; CHECK-NEXT: setp.gtu.bf16 %p2, %rs1, %rs2;
-; CHECK-NEXT: @%p2 bra $L__BB3_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB3_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp ult bfloat %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ugt bfloat %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_bfloat16_oeq_vs_olt(bfloat %a, bfloat %b) {
-; CHECK-LABEL: test_bfloat16_oeq_vs_olt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<3>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_oeq_vs_olt_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_oeq_vs_olt_param_0];
-; CHECK-NEXT: setp.eq.bf16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB4_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB4_2: // %merge1
-; CHECK-NEXT: setp.lt.bf16 %p2, %rs1, %rs2;
-; CHECK-NEXT: @%p2 bra $L__BB4_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB4_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp oeq bfloat %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp olt bfloat %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-float16.ll b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-float16.ll
deleted file mode 100644
index 6ea217ab97b53..0000000000000
--- a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-float16.ll
+++ /dev/null
@@ -1,224 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -march=nvptx64 -mcpu=sm_100 -O2 < %s | FileCheck %s
-
-target triple = "nvptx64-nvidia-cuda"
-
-define i32 @test_float16_ueq_vs_une(half %a, half %b) {
-; CHECK-LABEL: test_float16_ueq_vs_une(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<3>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ueq_vs_une_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ueq_vs_une_param_0];
-; CHECK-NEXT: setp.equ.f16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB0_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB0_2: // %merge1
-; CHECK-NEXT: setp.neu.f16 %p2, %rs1, %rs2;
-; CHECK-NEXT: @%p2 bra $L__BB0_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB0_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp ueq half %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp une half %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float16_oeq_vs_one(half %a, half %b) {
-; CHECK-LABEL: test_float16_oeq_vs_one(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<3>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_oeq_vs_one_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_oeq_vs_one_param_0];
-; CHECK-NEXT: setp.eq.f16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB1_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB1_2: // %merge1
-; CHECK-NEXT: setp.ne.f16 %p2, %rs1, %rs2;
-; CHECK-NEXT: @%p2 bra $L__BB1_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB1_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp oeq half %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp one half %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float16_olt_vs_ogt(half %a, half %b) {
-; CHECK-LABEL: test_float16_olt_vs_ogt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<3>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_olt_vs_ogt_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_olt_vs_ogt_param_0];
-; CHECK-NEXT: setp.lt.f16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB2_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB2_2: // %merge1
-; CHECK-NEXT: setp.gt.f16 %p2, %rs1, %rs2;
-; CHECK-NEXT: @%p2 bra $L__BB2_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB2_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp olt half %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ogt half %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float16_ult_vs_ugt(half %a, half %b) {
-; CHECK-LABEL: test_float16_ult_vs_ugt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<3>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ult_vs_ugt_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ult_vs_ugt_param_0];
-; CHECK-NEXT: setp.ltu.f16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB3_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB3_2: // %merge1
-; CHECK-NEXT: setp.gtu.f16 %p2, %rs1, %rs2;
-; CHECK-NEXT: @%p2 bra $L__BB3_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB3_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp ult half %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ugt half %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float16_oeq_vs_olt(half %a, half %b) {
-; CHECK-LABEL: test_float16_oeq_vs_olt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<3>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_oeq_vs_olt_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_oeq_vs_olt_param_0];
-; CHECK-NEXT: setp.eq.f16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB4_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB4_2: // %merge1
-; CHECK-NEXT: setp.lt.f16 %p2, %rs1, %rs2;
-; CHECK-NEXT: @%p2 bra $L__BB4_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB4_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp oeq half %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp olt half %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-float32.ll b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-float32.ll
deleted file mode 100644
index 9008782b70b25..0000000000000
--- a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-float32.ll
+++ /dev/null
@@ -1,214 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -march=nvptx64 -mcpu=sm_100 -O2 < %s | FileCheck %s
-
-target triple = "nvptx64-nvidia-cuda"
-
-define i32 @test_float32_ueq_vs_une(float %arg) {
-; CHECK-LABEL: test_float32_ueq_vs_une(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<3>;
-; CHECK-NEXT: .reg .b32 %r<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ueq_vs_une_param_0];
-; CHECK-NEXT: setp.equ.f32 %p1, %r1, 0f00000000;
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: @%p1 bra $L__BB0_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r2, 1;
-; CHECK-NEXT: $L__BB0_2: // %merge1
-; CHECK-NEXT: setp.neu.f32 %p2, %r1, 0f00000000;
-; CHECK-NEXT: @%p2 bra $L__BB0_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: $L__BB0_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp ueq float %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp une float %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float32_oeq_vs_one(float %arg) {
-; CHECK-LABEL: test_float32_oeq_vs_one(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<3>;
-; CHECK-NEXT: .reg .b32 %r<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_oeq_vs_one_param_0];
-; CHECK-NEXT: setp.eq.f32 %p1, %r1, 0f00000000;
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: @%p1 bra $L__BB1_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r2, 1;
-; CHECK-NEXT: $L__BB1_2: // %merge1
-; CHECK-NEXT: setp.ne.f32 %p2, %r1, 0f00000000;
-; CHECK-NEXT: @%p2 bra $L__BB1_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: $L__BB1_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp oeq float %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp one float %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float32_olt_vs_ogt(float %arg) {
-; CHECK-LABEL: test_float32_olt_vs_ogt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<3>;
-; CHECK-NEXT: .reg .b32 %r<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_olt_vs_ogt_param_0];
-; CHECK-NEXT: setp.lt.f32 %p1, %r1, 0f00000000;
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: @%p1 bra $L__BB2_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r2, 1;
-; CHECK-NEXT: $L__BB2_2: // %merge1
-; CHECK-NEXT: setp.gt.f32 %p2, %r1, 0f00000000;
-; CHECK-NEXT: @%p2 bra $L__BB2_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: $L__BB2_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp olt float %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ogt float %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float32_ult_vs_ugt(float %arg) {
-; CHECK-LABEL: test_float32_ult_vs_ugt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<3>;
-; CHECK-NEXT: .reg .b32 %r<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ult_vs_ugt_param_0];
-; CHECK-NEXT: setp.ltu.f32 %p1, %r1, 0f00000000;
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: @%p1 bra $L__BB3_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r2, 1;
-; CHECK-NEXT: $L__BB3_2: // %merge1
-; CHECK-NEXT: setp.gtu.f32 %p2, %r1, 0f00000000;
-; CHECK-NEXT: @%p2 bra $L__BB3_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: $L__BB3_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp ult float %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ugt float %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float32_oeq_vs_olt(float %arg) {
-; CHECK-LABEL: test_float32_oeq_vs_olt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<3>;
-; CHECK-NEXT: .reg .b32 %r<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r1, [test_float32_oeq_vs_olt_param_0];
-; CHECK-NEXT: setp.eq.f32 %p1, %r1, 0f00000000;
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: @%p1 bra $L__BB4_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r2, 1;
-; CHECK-NEXT: $L__BB4_2: // %merge1
-; CHECK-NEXT: setp.lt.f32 %p2, %r1, 0f00000000;
-; CHECK-NEXT: @%p2 bra $L__BB4_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r2, 0;
-; CHECK-NEXT: $L__BB4_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp oeq float %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp olt float %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-float64.ll b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-float64.ll
deleted file mode 100644
index 1c6ab1ef6f093..0000000000000
--- a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-float64.ll
+++ /dev/null
@@ -1,219 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -march=nvptx64 -mcpu=sm_100 -O2 < %s | FileCheck %s
-
-target triple = "nvptx64-nvidia-cuda"
-
-define i32 @test_float64_ueq_vs_une(double %arg) {
-; CHECK-LABEL: test_float64_ueq_vs_une(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ueq_vs_une_param_0];
-; CHECK-NEXT: setp.equ.f64 %p1, %rd1, 0d0000000000000000;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB0_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB0_2: // %merge1
-; CHECK-NEXT: setp.neu.f64 %p2, %rd1, 0d0000000000000000;
-; CHECK-NEXT: @%p2 bra $L__BB0_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB0_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp ueq double %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp une double %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float64_oeq_vs_one(double %arg) {
-; CHECK-LABEL: test_float64_oeq_vs_one(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_oeq_vs_one_param_0];
-; CHECK-NEXT: setp.eq.f64 %p1, %rd1, 0d0000000000000000;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB1_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB1_2: // %merge1
-; CHECK-NEXT: setp.ne.f64 %p2, %rd1, 0d0000000000000000;
-; CHECK-NEXT: @%p2 bra $L__BB1_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB1_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp oeq double %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp one double %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float64_olt_vs_ogt(double %arg) {
-; CHECK-LABEL: test_float64_olt_vs_ogt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_olt_vs_ogt_param_0];
-; CHECK-NEXT: setp.lt.f64 %p1, %rd1, 0d0000000000000000;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB2_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB2_2: // %merge1
-; CHECK-NEXT: setp.gt.f64 %p2, %rd1, 0d0000000000000000;
-; CHECK-NEXT: @%p2 bra $L__BB2_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB2_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp olt double %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ogt double %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float64_ult_vs_ugt(double %arg) {
-; CHECK-LABEL: test_float64_ult_vs_ugt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ult_vs_ugt_param_0];
-; CHECK-NEXT: setp.ltu.f64 %p1, %rd1, 0d0000000000000000;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB3_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB3_2: // %merge1
-; CHECK-NEXT: setp.gtu.f64 %p2, %rd1, 0d0000000000000000;
-; CHECK-NEXT: @%p2 bra $L__BB3_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB3_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp ult double %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp ugt double %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_float64_oeq_vs_olt(double %arg) {
-; CHECK-LABEL: test_float64_oeq_vs_olt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_oeq_vs_olt_param_0];
-; CHECK-NEXT: setp.eq.f64 %p1, %rd1, 0d0000000000000000;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB4_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB4_2: // %merge1
-; CHECK-NEXT: setp.lt.f64 %p2, %rd1, 0d0000000000000000;
-; CHECK-NEXT: @%p2 bra $L__BB4_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB4_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = fcmp oeq double %arg, 0.000000e+00
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = fcmp olt double %arg, 0.000000e+00
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-int16.ll b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-int16.ll
deleted file mode 100644
index e9656967225e3..0000000000000
--- a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-int16.ll
+++ /dev/null
@@ -1,224 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -march=nvptx64 -mcpu=sm_100 -O2 < %s | FileCheck %s
-
-target triple = "nvptx64-nvidia-cuda"
-
-define i32 @test_int16_slt_vs_sgt(i16 %a, i16 %b) {
-; CHECK-LABEL: test_int16_slt_vs_sgt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<3>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_slt_vs_sgt_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_slt_vs_sgt_param_0];
-; CHECK-NEXT: setp.lt.s16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB0_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB0_2: // %merge1
-; CHECK-NEXT: setp.gt.s16 %p2, %rs1, %rs2;
-; CHECK-NEXT: @%p2 bra $L__BB0_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB0_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp slt i16 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp sgt i16 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int16_ult_vs_ugt(i16 %a, i16 %b) {
-; CHECK-LABEL: test_int16_ult_vs_ugt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<3>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_ult_vs_ugt_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_ult_vs_ugt_param_0];
-; CHECK-NEXT: setp.lt.u16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB1_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB1_2: // %merge1
-; CHECK-NEXT: setp.gt.u16 %p2, %rs1, %rs2;
-; CHECK-NEXT: @%p2 bra $L__BB1_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB1_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp ult i16 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp ugt i16 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int16_slt_vs_uge(i16 %a, i16 %b) {
-; CHECK-LABEL: test_int16_slt_vs_uge(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<3>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_slt_vs_uge_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_slt_vs_uge_param_0];
-; CHECK-NEXT: setp.lt.s16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB2_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB2_2: // %merge1
-; CHECK-NEXT: setp.ge.u16 %p2, %rs1, %rs2;
-; CHECK-NEXT: @%p2 bra $L__BB2_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB2_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp slt i16 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp uge i16 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int16_eq_vs_slt(i16 %a, i16 %b) {
-; CHECK-LABEL: test_int16_eq_vs_slt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<3>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_eq_vs_slt_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_eq_vs_slt_param_0];
-; CHECK-NEXT: setp.eq.b16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB3_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB3_2: // %merge1
-; CHECK-NEXT: setp.lt.s16 %p2, %rs1, %rs2;
-; CHECK-NEXT: @%p2 bra $L__BB3_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB3_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp eq i16 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp slt i16 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int16_ult_vs_sge(i16 %a, i16 %b) {
-; CHECK-LABEL: test_int16_ult_vs_sge(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<3>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_ult_vs_sge_param_1];
-; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_ult_vs_sge_param_0];
-; CHECK-NEXT: setp.lt.u16 %p1, %rs1, %rs2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB4_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB4_2: // %merge1
-; CHECK-NEXT: setp.ge.s16 %p2, %rs1, %rs2;
-; CHECK-NEXT: @%p2 bra $L__BB4_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB4_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp ult i16 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp sge i16 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-int32.ll b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-int32.ll
deleted file mode 100644
index 3820ea527dc05..0000000000000
--- a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-int32.ll
+++ /dev/null
@@ -1,219 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -march=nvptx64 -mcpu=sm_100 -O2 < %s | FileCheck %s
-
-target triple = "nvptx64-nvidia-cuda"
-
-define i32 @test_int32_slt_vs_sgt(i32 %a, i32 %b) {
-; CHECK-LABEL: test_int32_slt_vs_sgt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<3>;
-; CHECK-NEXT: .reg .b32 %r<4>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r2, [test_int32_slt_vs_sgt_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_int32_slt_vs_sgt_param_0];
-; CHECK-NEXT: setp.lt.s32 %p1, %r1, %r2;
-; CHECK-NEXT: mov.b32 %r3, 0;
-; CHECK-NEXT: @%p1 bra $L__BB0_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r3, 1;
-; CHECK-NEXT: $L__BB0_2: // %merge1
-; CHECK-NEXT: setp.gt.s32 %p2, %r1, %r2;
-; CHECK-NEXT: @%p2 bra $L__BB0_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r3, 0;
-; CHECK-NEXT: $L__BB0_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp slt i32 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp sgt i32 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int32_ult_vs_ugt(i32 %a, i32 %b) {
-; CHECK-LABEL: test_int32_ult_vs_ugt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<3>;
-; CHECK-NEXT: .reg .b32 %r<4>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r2, [test_int32_ult_vs_ugt_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_int32_ult_vs_ugt_param_0];
-; CHECK-NEXT: setp.lt.u32 %p1, %r1, %r2;
-; CHECK-NEXT: mov.b32 %r3, 0;
-; CHECK-NEXT: @%p1 bra $L__BB1_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r3, 1;
-; CHECK-NEXT: $L__BB1_2: // %merge1
-; CHECK-NEXT: setp.gt.u32 %p2, %r1, %r2;
-; CHECK-NEXT: @%p2 bra $L__BB1_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r3, 0;
-; CHECK-NEXT: $L__BB1_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp ult i32 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp ugt i32 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int32_slt_vs_uge(i32 %a, i32 %b) {
-; CHECK-LABEL: test_int32_slt_vs_uge(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<3>;
-; CHECK-NEXT: .reg .b32 %r<4>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r2, [test_int32_slt_vs_uge_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_int32_slt_vs_uge_param_0];
-; CHECK-NEXT: setp.lt.s32 %p1, %r1, %r2;
-; CHECK-NEXT: mov.b32 %r3, 0;
-; CHECK-NEXT: @%p1 bra $L__BB2_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r3, 1;
-; CHECK-NEXT: $L__BB2_2: // %merge1
-; CHECK-NEXT: setp.ge.u32 %p2, %r1, %r2;
-; CHECK-NEXT: @%p2 bra $L__BB2_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r3, 0;
-; CHECK-NEXT: $L__BB2_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp slt i32 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp uge i32 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int32_eq_vs_slt(i32 %a, i32 %b) {
-; CHECK-LABEL: test_int32_eq_vs_slt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<3>;
-; CHECK-NEXT: .reg .b32 %r<4>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r2, [test_int32_eq_vs_slt_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_int32_eq_vs_slt_param_0];
-; CHECK-NEXT: setp.eq.b32 %p1, %r1, %r2;
-; CHECK-NEXT: mov.b32 %r3, 0;
-; CHECK-NEXT: @%p1 bra $L__BB3_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r3, 1;
-; CHECK-NEXT: $L__BB3_2: // %merge1
-; CHECK-NEXT: setp.lt.s32 %p2, %r1, %r2;
-; CHECK-NEXT: @%p2 bra $L__BB3_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r3, 0;
-; CHECK-NEXT: $L__BB3_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp eq i32 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp slt i32 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int32_ult_vs_sge(i32 %a, i32 %b) {
-; CHECK-LABEL: test_int32_ult_vs_sge(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<3>;
-; CHECK-NEXT: .reg .b32 %r<4>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b32 %r2, [test_int32_ult_vs_sge_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_int32_ult_vs_sge_param_0];
-; CHECK-NEXT: setp.lt.u32 %p1, %r1, %r2;
-; CHECK-NEXT: mov.b32 %r3, 0;
-; CHECK-NEXT: @%p1 bra $L__BB4_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r3, 1;
-; CHECK-NEXT: $L__BB4_2: // %merge1
-; CHECK-NEXT: setp.ge.s32 %p2, %r1, %r2;
-; CHECK-NEXT: @%p2 bra $L__BB4_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r3, 0;
-; CHECK-NEXT: $L__BB4_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp ult i32 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp sge i32 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-int64.ll b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-int64.ll
deleted file mode 100644
index 9989929f8f5db..0000000000000
--- a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion-int64.ll
+++ /dev/null
@@ -1,224 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -march=nvptx64 -mcpu=sm_100 -O2 < %s | FileCheck %s
-
-target triple = "nvptx64-nvidia-cuda"
-
-define i32 @test_int64_slt_vs_sgt(i64 %a, i64 %b) {
-; CHECK-LABEL: test_int64_slt_vs_sgt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_slt_vs_sgt_param_1];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_slt_vs_sgt_param_0];
-; CHECK-NEXT: setp.lt.s64 %p1, %rd1, %rd2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB0_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB0_2: // %merge1
-; CHECK-NEXT: setp.gt.s64 %p2, %rd1, %rd2;
-; CHECK-NEXT: @%p2 bra $L__BB0_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB0_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp slt i64 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp sgt i64 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int64_ult_vs_ugt(i64 %a, i64 %b) {
-; CHECK-LABEL: test_int64_ult_vs_ugt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_ult_vs_ugt_param_1];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_ult_vs_ugt_param_0];
-; CHECK-NEXT: setp.lt.u64 %p1, %rd1, %rd2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB1_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB1_2: // %merge1
-; CHECK-NEXT: setp.gt.u64 %p2, %rd1, %rd2;
-; CHECK-NEXT: @%p2 bra $L__BB1_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB1_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp ult i64 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp ugt i64 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int64_slt_vs_uge(i64 %a, i64 %b) {
-; CHECK-LABEL: test_int64_slt_vs_uge(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_slt_vs_uge_param_1];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_slt_vs_uge_param_0];
-; CHECK-NEXT: setp.lt.s64 %p1, %rd1, %rd2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB2_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB2_2: // %merge1
-; CHECK-NEXT: setp.ge.u64 %p2, %rd1, %rd2;
-; CHECK-NEXT: @%p2 bra $L__BB2_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB2_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp slt i64 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp uge i64 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int64_eq_vs_slt(i64 %a, i64 %b) {
-; CHECK-LABEL: test_int64_eq_vs_slt(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_eq_vs_slt_param_1];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_eq_vs_slt_param_0];
-; CHECK-NEXT: setp.eq.b64 %p1, %rd1, %rd2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB3_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB3_2: // %merge1
-; CHECK-NEXT: setp.lt.s64 %p2, %rd1, %rd2;
-; CHECK-NEXT: @%p2 bra $L__BB3_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB3_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp eq i64 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp slt i64 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
-
-define i32 @test_int64_ult_vs_sge(i64 %a, i64 %b) {
-; CHECK-LABEL: test_int64_ult_vs_sge(
-; CHECK: {
-; CHECK-NEXT: .reg .pred %p<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<3>;
-; CHECK-EMPTY:
-; CHECK-NEXT: // %bb.0: // %entry
-; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_ult_vs_sge_param_1];
-; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_ult_vs_sge_param_0];
-; CHECK-NEXT: setp.lt.u64 %p1, %rd1, %rd2;
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: @%p1 bra $L__BB4_2;
-; CHECK-NEXT: // %bb.1: // %then
-; CHECK-NEXT: mov.b32 %r1, 1;
-; CHECK-NEXT: $L__BB4_2: // %merge1
-; CHECK-NEXT: setp.ge.s64 %p2, %rd1, %rd2;
-; CHECK-NEXT: @%p2 bra $L__BB4_4;
-; CHECK-NEXT: // %bb.3: // %else
-; CHECK-NEXT: mov.b32 %r1, 0;
-; CHECK-NEXT: $L__BB4_4: // %merge2
-; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
-; CHECK-NEXT: ret;
-entry:
- %cmp = icmp ult i64 %a, %b
- br i1 %cmp, label %merge1, label %then
-
-then:
- %tmp = load i32, ptr addrspace(1) null, align 4
- br label %merge1
-
-merge1:
- %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
- %cmp2 = icmp sge i64 %a, %b
- br i1 %cmp2, label %merge2, label %else
-
-else:
- br label %merge2
-
-merge2:
- %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
- ret i32 %phi2
-}
diff --git a/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion.ll b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion.ll
new file mode 100644
index 0000000000000..2a6780fb296bd
--- /dev/null
+++ b/llvm/test/CodeGen/NVPTX/machine-cse-predicate-no-inversion.ll
@@ -0,0 +1,1525 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -march=nvptx64 -mcpu=sm_100 -O2 < %s | FileCheck %s
+; RUN: %if ptxas-sm_100 %{ llc < %s -march=nvptx64 -mcpu=sm_100 -O2 | %ptxas-verify -arch=sm_100 %}
+
+target triple = "nvptx64-nvidia-cuda"
+
+define i32 @test_int16_slt_vs_sgt(i16 %a, i16 %b) {
+; CHECK-LABEL: test_int16_slt_vs_sgt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_slt_vs_sgt_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_slt_vs_sgt_param_0];
+; CHECK-NEXT: setp.lt.s16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB0_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB0_2: // %merge1
+; CHECK-NEXT: setp.gt.s16 %p2, %rs1, %rs2;
+; CHECK-NEXT: @%p2 bra $L__BB0_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB0_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp slt i16 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp sgt i16 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int16_ult_vs_ugt(i16 %a, i16 %b) {
+; CHECK-LABEL: test_int16_ult_vs_ugt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_ult_vs_ugt_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_ult_vs_ugt_param_0];
+; CHECK-NEXT: setp.lt.u16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB1_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB1_2: // %merge1
+; CHECK-NEXT: setp.gt.u16 %p2, %rs1, %rs2;
+; CHECK-NEXT: @%p2 bra $L__BB1_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB1_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp ult i16 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp ugt i16 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int16_slt_vs_uge(i16 %a, i16 %b) {
+; CHECK-LABEL: test_int16_slt_vs_uge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_slt_vs_uge_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_slt_vs_uge_param_0];
+; CHECK-NEXT: setp.lt.s16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB2_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB2_2: // %merge1
+; CHECK-NEXT: setp.ge.u16 %p2, %rs1, %rs2;
+; CHECK-NEXT: @%p2 bra $L__BB2_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB2_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp slt i16 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp uge i16 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int16_eq_vs_slt(i16 %a, i16 %b) {
+; CHECK-LABEL: test_int16_eq_vs_slt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_eq_vs_slt_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_eq_vs_slt_param_0];
+; CHECK-NEXT: setp.eq.b16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB3_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB3_2: // %merge1
+; CHECK-NEXT: setp.lt.s16 %p2, %rs1, %rs2;
+; CHECK-NEXT: @%p2 bra $L__BB3_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB3_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp eq i16 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp slt i16 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int16_ult_vs_sge(i16 %a, i16 %b) {
+; CHECK-LABEL: test_int16_ult_vs_sge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_int16_ult_vs_sge_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_int16_ult_vs_sge_param_0];
+; CHECK-NEXT: setp.lt.u16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB4_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB4_2: // %merge1
+; CHECK-NEXT: setp.ge.s16 %p2, %rs1, %rs2;
+; CHECK-NEXT: @%p2 bra $L__BB4_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB4_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp ult i16 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp sge i16 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int32_slt_vs_sgt(i32 %a, i32 %b) {
+; CHECK-LABEL: test_int32_slt_vs_sgt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r2, [test_int32_slt_vs_sgt_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_int32_slt_vs_sgt_param_0];
+; CHECK-NEXT: setp.lt.s32 %p1, %r1, %r2;
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: @%p1 bra $L__BB5_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r3, 1;
+; CHECK-NEXT: $L__BB5_2: // %merge1
+; CHECK-NEXT: setp.gt.s32 %p2, %r1, %r2;
+; CHECK-NEXT: @%p2 bra $L__BB5_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: $L__BB5_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp slt i32 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp sgt i32 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int32_ult_vs_ugt(i32 %a, i32 %b) {
+; CHECK-LABEL: test_int32_ult_vs_ugt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r2, [test_int32_ult_vs_ugt_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_int32_ult_vs_ugt_param_0];
+; CHECK-NEXT: setp.lt.u32 %p1, %r1, %r2;
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: @%p1 bra $L__BB6_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r3, 1;
+; CHECK-NEXT: $L__BB6_2: // %merge1
+; CHECK-NEXT: setp.gt.u32 %p2, %r1, %r2;
+; CHECK-NEXT: @%p2 bra $L__BB6_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: $L__BB6_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp ult i32 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp ugt i32 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int32_slt_vs_uge(i32 %a, i32 %b) {
+; CHECK-LABEL: test_int32_slt_vs_uge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r2, [test_int32_slt_vs_uge_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_int32_slt_vs_uge_param_0];
+; CHECK-NEXT: setp.lt.s32 %p1, %r1, %r2;
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: @%p1 bra $L__BB7_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r3, 1;
+; CHECK-NEXT: $L__BB7_2: // %merge1
+; CHECK-NEXT: setp.ge.u32 %p2, %r1, %r2;
+; CHECK-NEXT: @%p2 bra $L__BB7_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: $L__BB7_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp slt i32 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp uge i32 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int32_eq_vs_slt(i32 %a, i32 %b) {
+; CHECK-LABEL: test_int32_eq_vs_slt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r2, [test_int32_eq_vs_slt_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_int32_eq_vs_slt_param_0];
+; CHECK-NEXT: setp.eq.b32 %p1, %r1, %r2;
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: @%p1 bra $L__BB8_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r3, 1;
+; CHECK-NEXT: $L__BB8_2: // %merge1
+; CHECK-NEXT: setp.lt.s32 %p2, %r1, %r2;
+; CHECK-NEXT: @%p2 bra $L__BB8_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: $L__BB8_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp eq i32 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp slt i32 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int32_ult_vs_sge(i32 %a, i32 %b) {
+; CHECK-LABEL: test_int32_ult_vs_sge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r2, [test_int32_ult_vs_sge_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_int32_ult_vs_sge_param_0];
+; CHECK-NEXT: setp.lt.u32 %p1, %r1, %r2;
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: @%p1 bra $L__BB9_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r3, 1;
+; CHECK-NEXT: $L__BB9_2: // %merge1
+; CHECK-NEXT: setp.ge.s32 %p2, %r1, %r2;
+; CHECK-NEXT: @%p2 bra $L__BB9_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r3, 0;
+; CHECK-NEXT: $L__BB9_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp ult i32 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp sge i32 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int64_slt_vs_sgt(i64 %a, i64 %b) {
+; CHECK-LABEL: test_int64_slt_vs_sgt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_slt_vs_sgt_param_1];
+; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_slt_vs_sgt_param_0];
+; CHECK-NEXT: setp.lt.s64 %p1, %rd1, %rd2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB10_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB10_2: // %merge1
+; CHECK-NEXT: setp.gt.s64 %p2, %rd1, %rd2;
+; CHECK-NEXT: @%p2 bra $L__BB10_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB10_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp slt i64 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp sgt i64 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int64_ult_vs_ugt(i64 %a, i64 %b) {
+; CHECK-LABEL: test_int64_ult_vs_ugt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_ult_vs_ugt_param_1];
+; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_ult_vs_ugt_param_0];
+; CHECK-NEXT: setp.lt.u64 %p1, %rd1, %rd2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB11_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB11_2: // %merge1
+; CHECK-NEXT: setp.gt.u64 %p2, %rd1, %rd2;
+; CHECK-NEXT: @%p2 bra $L__BB11_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB11_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp ult i64 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp ugt i64 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int64_slt_vs_uge(i64 %a, i64 %b) {
+; CHECK-LABEL: test_int64_slt_vs_uge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_slt_vs_uge_param_1];
+; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_slt_vs_uge_param_0];
+; CHECK-NEXT: setp.lt.s64 %p1, %rd1, %rd2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB12_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB12_2: // %merge1
+; CHECK-NEXT: setp.ge.u64 %p2, %rd1, %rd2;
+; CHECK-NEXT: @%p2 bra $L__BB12_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB12_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp slt i64 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp uge i64 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int64_eq_vs_slt(i64 %a, i64 %b) {
+; CHECK-LABEL: test_int64_eq_vs_slt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_eq_vs_slt_param_1];
+; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_eq_vs_slt_param_0];
+; CHECK-NEXT: setp.eq.b64 %p1, %rd1, %rd2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB13_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB13_2: // %merge1
+; CHECK-NEXT: setp.lt.s64 %p2, %rd1, %rd2;
+; CHECK-NEXT: @%p2 bra $L__BB13_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB13_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp eq i64 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp slt i64 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_int64_ult_vs_sge(i64 %a, i64 %b) {
+; CHECK-LABEL: test_int64_ult_vs_sge(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd2, [test_int64_ult_vs_sge_param_1];
+; CHECK-NEXT: ld.param.b64 %rd1, [test_int64_ult_vs_sge_param_0];
+; CHECK-NEXT: setp.lt.u64 %p1, %rd1, %rd2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB14_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB14_2: // %merge1
+; CHECK-NEXT: setp.ge.s64 %p2, %rd1, %rd2;
+; CHECK-NEXT: @%p2 bra $L__BB14_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB14_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = icmp ult i64 %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = icmp sge i64 %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_ueq_vs_une(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_ueq_vs_une(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ueq_vs_une_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ueq_vs_une_param_0];
+; CHECK-NEXT: setp.equ.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB15_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB15_2: // %merge1
+; CHECK-NEXT: setp.neu.bf16 %p2, %rs1, %rs2;
+; CHECK-NEXT: @%p2 bra $L__BB15_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB15_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ueq bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp une bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_oeq_vs_one(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_oeq_vs_one(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_oeq_vs_one_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_oeq_vs_one_param_0];
+; CHECK-NEXT: setp.eq.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB16_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB16_2: // %merge1
+; CHECK-NEXT: setp.ne.bf16 %p2, %rs1, %rs2;
+; CHECK-NEXT: @%p2 bra $L__BB16_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB16_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oeq bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp one bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_olt_vs_ogt(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_olt_vs_ogt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_olt_vs_ogt_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_olt_vs_ogt_param_0];
+; CHECK-NEXT: setp.lt.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB17_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB17_2: // %merge1
+; CHECK-NEXT: setp.gt.bf16 %p2, %rs1, %rs2;
+; CHECK-NEXT: @%p2 bra $L__BB17_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB17_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp olt bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ogt bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_ult_vs_ugt(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_ult_vs_ugt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_ult_vs_ugt_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_ult_vs_ugt_param_0];
+; CHECK-NEXT: setp.ltu.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB18_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB18_2: // %merge1
+; CHECK-NEXT: setp.gtu.bf16 %p2, %rs1, %rs2;
+; CHECK-NEXT: @%p2 bra $L__BB18_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB18_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ult bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ugt bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_bfloat16_oeq_vs_olt(bfloat %a, bfloat %b) {
+; CHECK-LABEL: test_bfloat16_oeq_vs_olt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_bfloat16_oeq_vs_olt_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_bfloat16_oeq_vs_olt_param_0];
+; CHECK-NEXT: setp.eq.bf16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB19_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB19_2: // %merge1
+; CHECK-NEXT: setp.lt.bf16 %p2, %rs1, %rs2;
+; CHECK-NEXT: @%p2 bra $L__BB19_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB19_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oeq bfloat %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp olt bfloat %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_ueq_vs_une(half %a, half %b) {
+; CHECK-LABEL: test_float16_ueq_vs_une(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ueq_vs_une_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ueq_vs_une_param_0];
+; CHECK-NEXT: setp.equ.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB20_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB20_2: // %merge1
+; CHECK-NEXT: setp.neu.f16 %p2, %rs1, %rs2;
+; CHECK-NEXT: @%p2 bra $L__BB20_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB20_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ueq half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp une half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_oeq_vs_one(half %a, half %b) {
+; CHECK-LABEL: test_float16_oeq_vs_one(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_oeq_vs_one_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_oeq_vs_one_param_0];
+; CHECK-NEXT: setp.eq.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB21_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB21_2: // %merge1
+; CHECK-NEXT: setp.ne.f16 %p2, %rs1, %rs2;
+; CHECK-NEXT: @%p2 bra $L__BB21_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB21_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oeq half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp one half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_olt_vs_ogt(half %a, half %b) {
+; CHECK-LABEL: test_float16_olt_vs_ogt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_olt_vs_ogt_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_olt_vs_ogt_param_0];
+; CHECK-NEXT: setp.lt.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB22_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB22_2: // %merge1
+; CHECK-NEXT: setp.gt.f16 %p2, %rs1, %rs2;
+; CHECK-NEXT: @%p2 bra $L__BB22_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB22_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp olt half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ogt half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_ult_vs_ugt(half %a, half %b) {
+; CHECK-LABEL: test_float16_ult_vs_ugt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_ult_vs_ugt_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_ult_vs_ugt_param_0];
+; CHECK-NEXT: setp.ltu.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB23_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB23_2: // %merge1
+; CHECK-NEXT: setp.gtu.f16 %p2, %rs1, %rs2;
+; CHECK-NEXT: @%p2 bra $L__BB23_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB23_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ult half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ugt half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float16_oeq_vs_olt(half %a, half %b) {
+; CHECK-LABEL: test_float16_oeq_vs_olt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b16 %rs2, [test_float16_oeq_vs_olt_param_1];
+; CHECK-NEXT: ld.param.b16 %rs1, [test_float16_oeq_vs_olt_param_0];
+; CHECK-NEXT: setp.eq.f16 %p1, %rs1, %rs2;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB24_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB24_2: // %merge1
+; CHECK-NEXT: setp.lt.f16 %p2, %rs1, %rs2;
+; CHECK-NEXT: @%p2 bra $L__BB24_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB24_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oeq half %a, %b
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp olt half %a, %b
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_ueq_vs_une(float %arg) {
+; CHECK-LABEL: test_float32_ueq_vs_une(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ueq_vs_une_param_0];
+; CHECK-NEXT: setp.equ.f32 %p1, %r1, 0f00000000;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB25_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB25_2: // %merge1
+; CHECK-NEXT: setp.neu.f32 %p2, %r1, 0f00000000;
+; CHECK-NEXT: @%p2 bra $L__BB25_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB25_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ueq float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp une float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_oeq_vs_one(float %arg) {
+; CHECK-LABEL: test_float32_oeq_vs_one(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_oeq_vs_one_param_0];
+; CHECK-NEXT: setp.eq.f32 %p1, %r1, 0f00000000;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB26_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB26_2: // %merge1
+; CHECK-NEXT: setp.ne.f32 %p2, %r1, 0f00000000;
+; CHECK-NEXT: @%p2 bra $L__BB26_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB26_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oeq float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp one float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_olt_vs_ogt(float %arg) {
+; CHECK-LABEL: test_float32_olt_vs_ogt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_olt_vs_ogt_param_0];
+; CHECK-NEXT: setp.lt.f32 %p1, %r1, 0f00000000;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB27_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB27_2: // %merge1
+; CHECK-NEXT: setp.gt.f32 %p2, %r1, 0f00000000;
+; CHECK-NEXT: @%p2 bra $L__BB27_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB27_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp olt float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ogt float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_ult_vs_ugt(float %arg) {
+; CHECK-LABEL: test_float32_ult_vs_ugt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_ult_vs_ugt_param_0];
+; CHECK-NEXT: setp.ltu.f32 %p1, %r1, 0f00000000;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB28_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB28_2: // %merge1
+; CHECK-NEXT: setp.gtu.f32 %p2, %r1, 0f00000000;
+; CHECK-NEXT: @%p2 bra $L__BB28_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB28_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ult float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ugt float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float32_oeq_vs_olt(float %arg) {
+; CHECK-LABEL: test_float32_oeq_vs_olt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b32 %r1, [test_float32_oeq_vs_olt_param_0];
+; CHECK-NEXT: setp.eq.f32 %p1, %r1, 0f00000000;
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: @%p1 bra $L__BB29_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r2, 1;
+; CHECK-NEXT: $L__BB29_2: // %merge1
+; CHECK-NEXT: setp.lt.f32 %p2, %r1, 0f00000000;
+; CHECK-NEXT: @%p2 bra $L__BB29_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r2, 0;
+; CHECK-NEXT: $L__BB29_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oeq float %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp olt float %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_ueq_vs_une(double %arg) {
+; CHECK-LABEL: test_float64_ueq_vs_une(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ueq_vs_une_param_0];
+; CHECK-NEXT: setp.equ.f64 %p1, %rd1, 0d0000000000000000;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB30_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB30_2: // %merge1
+; CHECK-NEXT: setp.neu.f64 %p2, %rd1, 0d0000000000000000;
+; CHECK-NEXT: @%p2 bra $L__BB30_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB30_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ueq double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp une double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_oeq_vs_one(double %arg) {
+; CHECK-LABEL: test_float64_oeq_vs_one(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_oeq_vs_one_param_0];
+; CHECK-NEXT: setp.eq.f64 %p1, %rd1, 0d0000000000000000;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB31_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB31_2: // %merge1
+; CHECK-NEXT: setp.ne.f64 %p2, %rd1, 0d0000000000000000;
+; CHECK-NEXT: @%p2 bra $L__BB31_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB31_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oeq double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp one double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_olt_vs_ogt(double %arg) {
+; CHECK-LABEL: test_float64_olt_vs_ogt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_olt_vs_ogt_param_0];
+; CHECK-NEXT: setp.lt.f64 %p1, %rd1, 0d0000000000000000;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB32_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB32_2: // %merge1
+; CHECK-NEXT: setp.gt.f64 %p2, %rd1, 0d0000000000000000;
+; CHECK-NEXT: @%p2 bra $L__BB32_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB32_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp olt double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ogt double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_ult_vs_ugt(double %arg) {
+; CHECK-LABEL: test_float64_ult_vs_ugt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_ult_vs_ugt_param_0];
+; CHECK-NEXT: setp.ltu.f64 %p1, %rd1, 0d0000000000000000;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB33_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB33_2: // %merge1
+; CHECK-NEXT: setp.gtu.f64 %p2, %rd1, 0d0000000000000000;
+; CHECK-NEXT: @%p2 bra $L__BB33_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB33_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp ult double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp ugt double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
+
+define i32 @test_float64_oeq_vs_olt(double %arg) {
+; CHECK-LABEL: test_float64_oeq_vs_olt(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_float64_oeq_vs_olt_param_0];
+; CHECK-NEXT: setp.eq.f64 %p1, %rd1, 0d0000000000000000;
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: @%p1 bra $L__BB34_2;
+; CHECK-NEXT: // %bb.1: // %then
+; CHECK-NEXT: mov.b32 %r1, 1;
+; CHECK-NEXT: $L__BB34_2: // %merge1
+; CHECK-NEXT: setp.lt.f64 %p2, %rd1, 0d0000000000000000;
+; CHECK-NEXT: @%p2 bra $L__BB34_4;
+; CHECK-NEXT: // %bb.3: // %else
+; CHECK-NEXT: mov.b32 %r1, 0;
+; CHECK-NEXT: $L__BB34_4: // %merge2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
+entry:
+ %cmp = fcmp oeq double %arg, 0.000000e+00
+ br i1 %cmp, label %merge1, label %then
+
+then:
+ %tmp = load i32, ptr addrspace(1) null, align 4
+ br label %merge1
+
+merge1:
+ %phi1 = phi i32 [ 1, %then ], [ 0, %entry ]
+ %cmp2 = fcmp olt double %arg, 0.000000e+00
+ br i1 %cmp2, label %merge2, label %else
+
+else:
+ br label %merge2
+
+merge2:
+ %phi2 = phi i32 [ %phi1, %merge1 ], [ 0, %else ]
+ ret i32 %phi2
+}
>From 896c96ae73c104d89f1a1d28f553808463faefae Mon Sep 17 00:00:00 2001
From: Modi Mo <mmo at nvidia.com>
Date: Wed, 22 Apr 2026 21:20:32 -0700
Subject: [PATCH 4/6] move cmp modes into td and update users
---
llvm/lib/Target/NVPTX/CMakeLists.txt | 1 +
.../NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp | 120 +++---------------
llvm/lib/Target/NVPTX/NVPTX.h | 34 +++--
llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp | 34 ++---
llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp | 58 +--------
llvm/lib/Target/NVPTX/NVPTXInstrInfo.td | 64 +++++++++-
6 files changed, 113 insertions(+), 198 deletions(-)
diff --git a/llvm/lib/Target/NVPTX/CMakeLists.txt b/llvm/lib/Target/NVPTX/CMakeLists.txt
index e0e2b1a40bffc..6fd07fe2210ff 100644
--- a/llvm/lib/Target/NVPTX/CMakeLists.txt
+++ b/llvm/lib/Target/NVPTX/CMakeLists.txt
@@ -8,6 +8,7 @@ tablegen(LLVM NVPTXGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM NVPTXGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM NVPTXGenSDNodeInfo.inc -gen-sd-node-info)
tablegen(LLVM NVPTXGenSubtargetInfo.inc -gen-subtarget)
+tablegen(LLVM NVPTXGenCmpModes.inc -gen-searchable-tables)
add_public_tablegen_target(NVPTXCommonTableGen)
diff --git a/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp b/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
index 5af9e75bca399..5be1fa0332210 100644
--- a/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
+++ b/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
@@ -33,6 +33,11 @@ using namespace llvm;
#include "NVPTXGenAsmWriter.inc"
+namespace llvm::NVPTX::PTXCmpMode {
+#define GET_PTXCmpModeTable_IMPL
+#include "NVPTXGenCmpModes.inc"
+} // namespace llvm::NVPTX::PTXCmpMode
+
static bool hasParamSubqualifiers(const MCSubtargetInfo &STI) {
return STI.hasFeature(NVPTX::PTX83);
}
@@ -188,108 +193,19 @@ void NVPTXInstPrinter::printNegatedPredicate(const MCInst *MI, int OpNum,
void NVPTXInstPrinter::printCmpMode(const MCInst *MI, int OpNum,
const MCSubtargetInfo &, raw_ostream &O,
StringRef Modifier) {
- const MCOperand &MO = MI->getOperand(OpNum);
- int64_t Imm = MO.getImm();
-
- if (Modifier == "FCmp") {
- switch (Imm) {
- default:
- return;
- case NVPTX::PTXCmpMode::EQ:
- O << "eq";
- return;
- case NVPTX::PTXCmpMode::NE:
- O << "ne";
- return;
- case NVPTX::PTXCmpMode::LT:
- O << "lt";
- return;
- case NVPTX::PTXCmpMode::LE:
- O << "le";
- return;
- case NVPTX::PTXCmpMode::GT:
- O << "gt";
- return;
- case NVPTX::PTXCmpMode::GE:
- O << "ge";
- return;
- case NVPTX::PTXCmpMode::EQU:
- O << "equ";
- return;
- case NVPTX::PTXCmpMode::NEU:
- O << "neu";
- return;
- case NVPTX::PTXCmpMode::LTU:
- O << "ltu";
- return;
- case NVPTX::PTXCmpMode::LEU:
- O << "leu";
- return;
- case NVPTX::PTXCmpMode::GTU:
- O << "gtu";
- return;
- case NVPTX::PTXCmpMode::GEU:
- O << "geu";
- return;
- case NVPTX::PTXCmpMode::NUM:
- O << "num";
- return;
- case NVPTX::PTXCmpMode::NotANumber:
- O << "nan";
- return;
- }
- }
- if (Modifier == "ICmp") {
- switch (Imm) {
- default:
- llvm_unreachable("Invalid ICmp mode");
- case NVPTX::PTXCmpMode::EQ:
- O << "eq";
- return;
- case NVPTX::PTXCmpMode::NE:
- O << "ne";
- return;
- case NVPTX::PTXCmpMode::LT:
- case NVPTX::PTXCmpMode::LTU:
- O << "lt";
- return;
- case NVPTX::PTXCmpMode::LE:
- case NVPTX::PTXCmpMode::LEU:
- O << "le";
- return;
- case NVPTX::PTXCmpMode::GT:
- case NVPTX::PTXCmpMode::GTU:
- O << "gt";
- return;
- case NVPTX::PTXCmpMode::GE:
- case NVPTX::PTXCmpMode::GEU:
- O << "ge";
- return;
- }
- }
- if (Modifier == "IType") {
- switch (Imm) {
- default:
- llvm_unreachable("Invalid IType");
- case NVPTX::PTXCmpMode::EQ:
- case NVPTX::PTXCmpMode::NE:
- O << "b";
- return;
- case NVPTX::PTXCmpMode::LT:
- case NVPTX::PTXCmpMode::LE:
- case NVPTX::PTXCmpMode::GT:
- case NVPTX::PTXCmpMode::GE:
- O << "s";
- return;
- case NVPTX::PTXCmpMode::LTU:
- case NVPTX::PTXCmpMode::LEU:
- case NVPTX::PTXCmpMode::GTU:
- case NVPTX::PTXCmpMode::GEU:
- O << "u";
- return;
- }
- }
- llvm_unreachable("Empty Modifier");
+ const NVPTX::CmpModeInfo *Info =
+ NVPTX::PTXCmpMode::lookupCmpModeByValue(MI->getOperand(OpNum).getImm());
+ StringRef Str;
+ if (Modifier == "FCmp")
+ Str = Info->FCmpPrintStr;
+ else if (Modifier == "ICmp")
+ Str = Info->ICmpPrintStr;
+ else if (Modifier == "IType")
+ Str = Info->ITypePrintStr;
+ else
+ llvm_unreachable("Empty Modifier");
+ assert(!Str.empty() && "Invalid comparison mode for this modifier");
+ O << Str;
}
void NVPTXInstPrinter::printAtomicCode(const MCInst *MI, int OpNum,
diff --git a/llvm/lib/Target/NVPTX/NVPTX.h b/llvm/lib/Target/NVPTX/NVPTX.h
index d751f95fe3db0..628df0d427a43 100644
--- a/llvm/lib/Target/NVPTX/NVPTX.h
+++ b/llvm/lib/Target/NVPTX/NVPTX.h
@@ -241,26 +241,22 @@ enum CvtMode {
};
}
-/// PTXCmpMode - Comparison mode enumeration
-namespace PTXCmpMode {
-enum CmpMode {
- EQ = 0,
- NE,
- LT,
- LE,
- GT,
- GE,
- EQU,
- NEU,
- LTU,
- LEU,
- GTU,
- GEU,
- NUM,
- // NAN is a MACRO
- NotANumber,
+// Field order must match NVPTXInstrInfo.td
+struct CmpModeInfo {
+ uint8_t Value;
+ StringRef Name;
+ uint8_t IntInverseValue;
+ uint8_t FPInverseValue;
+ StringRef FCmpPrintStr;
+ StringRef ICmpPrintStr;
+ StringRef ITypePrintStr;
};
-}
+
+namespace PTXCmpMode {
+#define GET_PTXCmpMode_DECL
+#define GET_PTXCmpModeTable_DECL
+#include "NVPTXGenCmpModes.inc"
+} // namespace PTXCmpMode
namespace PTXPrmtMode {
enum PrmtMode {
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
index ede1deb5400b0..3904c74c080e0 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
@@ -366,48 +366,48 @@ bool NVPTXDAGToDAGISel::tryIntrinsicChain(SDNode *N) {
// Map ISD:CONDCODE value to appropriate CmpMode expected by
// NVPTXInstPrinter::printCmpMode()
SDValue NVPTXDAGToDAGISel::getPTXCmpMode(const CondCodeSDNode &CondCode) {
- using NVPTX::PTXCmpMode::CmpMode;
- const unsigned PTXCmpMode = [](ISD::CondCode CC) {
+ using namespace NVPTX::PTXCmpMode;
+ const unsigned Mode = [](ISD::CondCode CC) {
switch (CC) {
default:
llvm_unreachable("Unexpected condition code.");
case ISD::SETOEQ:
case ISD::SETEQ:
- return CmpMode::EQ;
+ return EQ;
case ISD::SETOGT:
case ISD::SETGT:
- return CmpMode::GT;
+ return GT;
case ISD::SETOGE:
case ISD::SETGE:
- return CmpMode::GE;
+ return GE;
case ISD::SETOLT:
case ISD::SETLT:
- return CmpMode::LT;
+ return LT;
case ISD::SETOLE:
case ISD::SETLE:
- return CmpMode::LE;
+ return LE;
case ISD::SETONE:
case ISD::SETNE:
- return CmpMode::NE;
+ return NE;
case ISD::SETO:
- return CmpMode::NUM;
+ return NUM;
case ISD::SETUO:
- return CmpMode::NotANumber;
+ return NotANumber;
case ISD::SETUEQ:
- return CmpMode::EQU;
+ return EQU;
case ISD::SETUGT:
- return CmpMode::GTU;
+ return GTU;
case ISD::SETUGE:
- return CmpMode::GEU;
+ return GEU;
case ISD::SETULT:
- return CmpMode::LTU;
+ return LTU;
case ISD::SETULE:
- return CmpMode::LEU;
+ return LEU;
case ISD::SETUNE:
- return CmpMode::NEU;
+ return NEU;
}
}(CondCode.get());
- return CurDAG->getTargetConstant(PTXCmpMode, SDLoc(), MVT::i32);
+ return CurDAG->getTargetConstant(Mode, SDLoc(), MVT::i32);
}
bool NVPTXDAGToDAGISel::SelectSETP_F16X2(SDNode *N) {
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
index d9900e98fe694..981cef95e1dad 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
@@ -255,65 +255,11 @@ static bool isScalarFloatSetp(const MachineInstr &MI) {
}
static int64_t invertIntegerCmpMode(int64_t Mode) {
- switch (Mode) {
- case NVPTX::PTXCmpMode::EQ:
- return NVPTX::PTXCmpMode::NE;
- case NVPTX::PTXCmpMode::NE:
- return NVPTX::PTXCmpMode::EQ;
- case NVPTX::PTXCmpMode::LT:
- return NVPTX::PTXCmpMode::GE;
- case NVPTX::PTXCmpMode::LE:
- return NVPTX::PTXCmpMode::GT;
- case NVPTX::PTXCmpMode::GT:
- return NVPTX::PTXCmpMode::LE;
- case NVPTX::PTXCmpMode::GE:
- return NVPTX::PTXCmpMode::LT;
- case NVPTX::PTXCmpMode::LTU:
- return NVPTX::PTXCmpMode::GEU;
- case NVPTX::PTXCmpMode::LEU:
- return NVPTX::PTXCmpMode::GTU;
- case NVPTX::PTXCmpMode::GTU:
- return NVPTX::PTXCmpMode::LEU;
- case NVPTX::PTXCmpMode::GEU:
- return NVPTX::PTXCmpMode::LTU;
- default:
- llvm_unreachable("Invalid integer comparison mode");
- }
+ return NVPTX::PTXCmpMode::lookupCmpModeByValue(Mode)->IntInverseValue;
}
static int64_t invertScalarFloatCmpMode(int64_t Mode) {
- switch (Mode) {
- case NVPTX::PTXCmpMode::EQ:
- return NVPTX::PTXCmpMode::NEU;
- case NVPTX::PTXCmpMode::NE:
- return NVPTX::PTXCmpMode::EQU;
- case NVPTX::PTXCmpMode::EQU:
- return NVPTX::PTXCmpMode::NE;
- case NVPTX::PTXCmpMode::NEU:
- return NVPTX::PTXCmpMode::EQ;
- case NVPTX::PTXCmpMode::LT:
- return NVPTX::PTXCmpMode::GEU;
- case NVPTX::PTXCmpMode::LE:
- return NVPTX::PTXCmpMode::GTU;
- case NVPTX::PTXCmpMode::GT:
- return NVPTX::PTXCmpMode::LEU;
- case NVPTX::PTXCmpMode::GE:
- return NVPTX::PTXCmpMode::LTU;
- case NVPTX::PTXCmpMode::LTU:
- return NVPTX::PTXCmpMode::GE;
- case NVPTX::PTXCmpMode::LEU:
- return NVPTX::PTXCmpMode::GT;
- case NVPTX::PTXCmpMode::GTU:
- return NVPTX::PTXCmpMode::LE;
- case NVPTX::PTXCmpMode::GEU:
- return NVPTX::PTXCmpMode::LT;
- case NVPTX::PTXCmpMode::NUM:
- return NVPTX::PTXCmpMode::NotANumber;
- case NVPTX::PTXCmpMode::NotANumber:
- return NVPTX::PTXCmpMode::NUM;
- default:
- llvm_unreachable("Invalid scalar float comparison mode");
- }
+ return NVPTX::PTXCmpMode::lookupCmpModeByValue(Mode)->FPInverseValue;
}
static void invertScalarCompareInstr(MachineInstr &MI) {
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
index 4b30611c3a128..609028b90f220 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
@@ -11,6 +11,7 @@
//===----------------------------------------------------------------------===//
include "NVPTXInstrFormats.td"
+include "llvm/TableGen/SearchableTable.td"
let OperandType = "OPERAND_IMMEDIATE" in {
def f16imm : Operand<f16>;
@@ -81,10 +82,65 @@ def BranchFlag : OperandWithDefaultOps<i32, (ops (i1 0))> {
let PrintMethod = "printNegatedPredicate";
}
-// Compare modes
-// These must match the enum in NVPTX.h
-def CmpEQ : PatLeaf<(i32 0)>;
-def CmpNE : PatLeaf<(i32 1)>;
+// SETP compare modes
+
+// Sentinel meaning "no valid inverse for this mode".
+defvar CmpModeInvalidInt = 0xFF;
+
+class CmpModeRec<int val, string name,
+ int intInv, int fpInv,
+ string fcmp, string icmp, string ityp> {
+ // Numeric encoding carried by the setp machine operand.
+ bits<8> Value = val;
+ // Enumerator spelling in NVPTX::PTXCmpMode.
+ string Name = name;
+ // Inverse predicate under integer-setp semantics
+ bits<8> IntInverseValue = intInv;
+ // Inverse predicate under scalar-float-setp semantics
+ bits<8> FPInverseValue = fpInv;
+ // Print mnemonic for float compares.
+ string FCmpPrintStr = fcmp;
+ // Print mnemonic for int compares.
+ string ICmpPrintStr = icmp;
+ // Signedness suffix for the integer setp instruction name (b/s/u);
+ string ITypePrintStr = ityp;
+}
+
+// val name intInv fpInv fcmp icmp ityp
+def CmpModeEQ_Rec : CmpModeRec<0, "EQ", 1, 7, "eq", "eq", "b">;
+def CmpModeNE_Rec : CmpModeRec<1, "NE", 0, 6, "ne", "ne", "b">;
+def CmpModeLT_Rec : CmpModeRec<2, "LT", 5, 11, "lt", "lt", "s">;
+def CmpModeLE_Rec : CmpModeRec<3, "LE", 4, 10, "le", "le", "s">;
+def CmpModeGT_Rec : CmpModeRec<4, "GT", 3, 9, "gt", "gt", "s">;
+def CmpModeGE_Rec : CmpModeRec<5, "GE", 2, 8, "ge", "ge", "s">;
+def CmpModeEQU_Rec : CmpModeRec<6, "EQU", CmpModeInvalidInt, 1, "equ", "", "">;
+def CmpModeNEU_Rec : CmpModeRec<7, "NEU", CmpModeInvalidInt, 0, "neu", "", "">;
+def CmpModeLTU_Rec : CmpModeRec<8, "LTU", 11, 5, "ltu", "lt", "u">;
+def CmpModeLEU_Rec : CmpModeRec<9, "LEU", 10, 4, "leu", "le", "u">;
+def CmpModeGTU_Rec : CmpModeRec<10, "GTU", 9, 3, "gtu", "gt", "u">;
+def CmpModeGEU_Rec : CmpModeRec<11, "GEU", 8, 2, "geu", "ge", "u">;
+def CmpModeNUM_Rec : CmpModeRec<12, "NUM", CmpModeInvalidInt, 13, "num", "", "">;
+def CmpModeNotANumber_Rec : CmpModeRec<13, "NotANumber", CmpModeInvalidInt, 12, "nan", "", "">;
+
+def PTXCmpMode : GenericEnum {
+ let FilterClass = "CmpModeRec";
+ let NameField = "Name";
+ let ValueField = "Value";
+ let UnderlyingType = "unsigned";
+}
+
+def PTXCmpModeTable : GenericTable {
+ let FilterClass = "CmpModeRec";
+ let CppTypeName = "CmpModeInfo";
+ let Fields = ["Value", "Name",
+ "IntInverseValue", "FPInverseValue",
+ "FCmpPrintStr", "ICmpPrintStr", "ITypePrintStr"];
+ let PrimaryKey = ["Value"];
+ let PrimaryKeyName = "lookupCmpModeByValue";
+}
+
+def CmpEQ : PatLeaf<(i32 !cast<int>(CmpModeEQ_Rec.Value))>;
+def CmpNE : PatLeaf<(i32 !cast<int>(CmpModeNE_Rec.Value))>;
def CmpMode : Operand<i32> {
let PrintMethod = "printCmpMode";
>From 08d120207dba845029f8c95a8a732203860071c9 Mon Sep 17 00:00:00 2001
From: modiking <mmo at nvidia.com>
Date: Thu, 30 Apr 2026 13:53:30 -0700
Subject: [PATCH 5/6] Update NVPTXInstrInfo.td
---
llvm/lib/Target/NVPTX/NVPTXInstrInfo.td | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
index 609028b90f220..454dfde39e536 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
@@ -78,7 +78,8 @@ def FTZFlag : OperandWithDefaultOps<i1, (ops (getFTZFlag (i1 0)))> {
let PrintMethod = "printFTZFlag";
}
-def BranchFlag : OperandWithDefaultOps<i32, (ops (i1 0))> {
+// Flag to indicate predicate negation (@!p) for conditional branches.
+def BranchFlag : OperandWithDefaultOps<i1, (ops (i1 0))> {
let PrintMethod = "printNegatedPredicate";
}
>From 4c1d0ee3ecea2fe7abaf294d897796f6e8129dbe Mon Sep 17 00:00:00 2001
From: root <mmo at nvidia.com>
Date: Tue, 5 May 2026 15:52:10 -0700
Subject: [PATCH 6/6] Revert "move cmp modes into td and update users"
This reverts commit 5950d9fcd6b2053e71929972b89cc983ce2cccaa, restoring
the hand-written PTXCmpMode enum in NVPTX.h and the switch-based
implementations of invertIntegerCmpMode, invertScalarFloatCmpMode,
NVPTXInstPrinter::printCmpMode and NVPTXDAGToDAGISel::getPTXCmpMode.
The TableGen GenericTable migration consolidated the comparison-mode
data but at the cost of an extra .inc file, an ODR-driven split between
NVPTXCodeGen and NVPTXDesc, and indirection through a generated lookup
where the local switches were already self-contained. Reverting until a
broader cleanup of NVPTX::PTXCmpMode is taken on as part of a larger
refactor.
Co-authored-by: Cursor <cursoragent at cursor.com>
---
llvm/lib/Target/NVPTX/CMakeLists.txt | 1 -
.../NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp | 120 +++++++++++++++---
llvm/lib/Target/NVPTX/NVPTX.h | 34 ++---
llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp | 34 ++---
llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp | 58 ++++++++-
llvm/lib/Target/NVPTX/NVPTXInstrInfo.td | 64 +---------
6 files changed, 198 insertions(+), 113 deletions(-)
diff --git a/llvm/lib/Target/NVPTX/CMakeLists.txt b/llvm/lib/Target/NVPTX/CMakeLists.txt
index 6fd07fe2210ff..e0e2b1a40bffc 100644
--- a/llvm/lib/Target/NVPTX/CMakeLists.txt
+++ b/llvm/lib/Target/NVPTX/CMakeLists.txt
@@ -8,7 +8,6 @@ tablegen(LLVM NVPTXGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM NVPTXGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM NVPTXGenSDNodeInfo.inc -gen-sd-node-info)
tablegen(LLVM NVPTXGenSubtargetInfo.inc -gen-subtarget)
-tablegen(LLVM NVPTXGenCmpModes.inc -gen-searchable-tables)
add_public_tablegen_target(NVPTXCommonTableGen)
diff --git a/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp b/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
index 5be1fa0332210..5af9e75bca399 100644
--- a/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
+++ b/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
@@ -33,11 +33,6 @@ using namespace llvm;
#include "NVPTXGenAsmWriter.inc"
-namespace llvm::NVPTX::PTXCmpMode {
-#define GET_PTXCmpModeTable_IMPL
-#include "NVPTXGenCmpModes.inc"
-} // namespace llvm::NVPTX::PTXCmpMode
-
static bool hasParamSubqualifiers(const MCSubtargetInfo &STI) {
return STI.hasFeature(NVPTX::PTX83);
}
@@ -193,19 +188,108 @@ void NVPTXInstPrinter::printNegatedPredicate(const MCInst *MI, int OpNum,
void NVPTXInstPrinter::printCmpMode(const MCInst *MI, int OpNum,
const MCSubtargetInfo &, raw_ostream &O,
StringRef Modifier) {
- const NVPTX::CmpModeInfo *Info =
- NVPTX::PTXCmpMode::lookupCmpModeByValue(MI->getOperand(OpNum).getImm());
- StringRef Str;
- if (Modifier == "FCmp")
- Str = Info->FCmpPrintStr;
- else if (Modifier == "ICmp")
- Str = Info->ICmpPrintStr;
- else if (Modifier == "IType")
- Str = Info->ITypePrintStr;
- else
- llvm_unreachable("Empty Modifier");
- assert(!Str.empty() && "Invalid comparison mode for this modifier");
- O << Str;
+ const MCOperand &MO = MI->getOperand(OpNum);
+ int64_t Imm = MO.getImm();
+
+ if (Modifier == "FCmp") {
+ switch (Imm) {
+ default:
+ return;
+ case NVPTX::PTXCmpMode::EQ:
+ O << "eq";
+ return;
+ case NVPTX::PTXCmpMode::NE:
+ O << "ne";
+ return;
+ case NVPTX::PTXCmpMode::LT:
+ O << "lt";
+ return;
+ case NVPTX::PTXCmpMode::LE:
+ O << "le";
+ return;
+ case NVPTX::PTXCmpMode::GT:
+ O << "gt";
+ return;
+ case NVPTX::PTXCmpMode::GE:
+ O << "ge";
+ return;
+ case NVPTX::PTXCmpMode::EQU:
+ O << "equ";
+ return;
+ case NVPTX::PTXCmpMode::NEU:
+ O << "neu";
+ return;
+ case NVPTX::PTXCmpMode::LTU:
+ O << "ltu";
+ return;
+ case NVPTX::PTXCmpMode::LEU:
+ O << "leu";
+ return;
+ case NVPTX::PTXCmpMode::GTU:
+ O << "gtu";
+ return;
+ case NVPTX::PTXCmpMode::GEU:
+ O << "geu";
+ return;
+ case NVPTX::PTXCmpMode::NUM:
+ O << "num";
+ return;
+ case NVPTX::PTXCmpMode::NotANumber:
+ O << "nan";
+ return;
+ }
+ }
+ if (Modifier == "ICmp") {
+ switch (Imm) {
+ default:
+ llvm_unreachable("Invalid ICmp mode");
+ case NVPTX::PTXCmpMode::EQ:
+ O << "eq";
+ return;
+ case NVPTX::PTXCmpMode::NE:
+ O << "ne";
+ return;
+ case NVPTX::PTXCmpMode::LT:
+ case NVPTX::PTXCmpMode::LTU:
+ O << "lt";
+ return;
+ case NVPTX::PTXCmpMode::LE:
+ case NVPTX::PTXCmpMode::LEU:
+ O << "le";
+ return;
+ case NVPTX::PTXCmpMode::GT:
+ case NVPTX::PTXCmpMode::GTU:
+ O << "gt";
+ return;
+ case NVPTX::PTXCmpMode::GE:
+ case NVPTX::PTXCmpMode::GEU:
+ O << "ge";
+ return;
+ }
+ }
+ if (Modifier == "IType") {
+ switch (Imm) {
+ default:
+ llvm_unreachable("Invalid IType");
+ case NVPTX::PTXCmpMode::EQ:
+ case NVPTX::PTXCmpMode::NE:
+ O << "b";
+ return;
+ case NVPTX::PTXCmpMode::LT:
+ case NVPTX::PTXCmpMode::LE:
+ case NVPTX::PTXCmpMode::GT:
+ case NVPTX::PTXCmpMode::GE:
+ O << "s";
+ return;
+ case NVPTX::PTXCmpMode::LTU:
+ case NVPTX::PTXCmpMode::LEU:
+ case NVPTX::PTXCmpMode::GTU:
+ case NVPTX::PTXCmpMode::GEU:
+ O << "u";
+ return;
+ }
+ }
+ llvm_unreachable("Empty Modifier");
}
void NVPTXInstPrinter::printAtomicCode(const MCInst *MI, int OpNum,
diff --git a/llvm/lib/Target/NVPTX/NVPTX.h b/llvm/lib/Target/NVPTX/NVPTX.h
index 628df0d427a43..d751f95fe3db0 100644
--- a/llvm/lib/Target/NVPTX/NVPTX.h
+++ b/llvm/lib/Target/NVPTX/NVPTX.h
@@ -241,22 +241,26 @@ enum CvtMode {
};
}
-// Field order must match NVPTXInstrInfo.td
-struct CmpModeInfo {
- uint8_t Value;
- StringRef Name;
- uint8_t IntInverseValue;
- uint8_t FPInverseValue;
- StringRef FCmpPrintStr;
- StringRef ICmpPrintStr;
- StringRef ITypePrintStr;
-};
-
+/// PTXCmpMode - Comparison mode enumeration
namespace PTXCmpMode {
-#define GET_PTXCmpMode_DECL
-#define GET_PTXCmpModeTable_DECL
-#include "NVPTXGenCmpModes.inc"
-} // namespace PTXCmpMode
+enum CmpMode {
+ EQ = 0,
+ NE,
+ LT,
+ LE,
+ GT,
+ GE,
+ EQU,
+ NEU,
+ LTU,
+ LEU,
+ GTU,
+ GEU,
+ NUM,
+ // NAN is a MACRO
+ NotANumber,
+};
+}
namespace PTXPrmtMode {
enum PrmtMode {
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
index 3904c74c080e0..ede1deb5400b0 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
@@ -366,48 +366,48 @@ bool NVPTXDAGToDAGISel::tryIntrinsicChain(SDNode *N) {
// Map ISD:CONDCODE value to appropriate CmpMode expected by
// NVPTXInstPrinter::printCmpMode()
SDValue NVPTXDAGToDAGISel::getPTXCmpMode(const CondCodeSDNode &CondCode) {
- using namespace NVPTX::PTXCmpMode;
- const unsigned Mode = [](ISD::CondCode CC) {
+ using NVPTX::PTXCmpMode::CmpMode;
+ const unsigned PTXCmpMode = [](ISD::CondCode CC) {
switch (CC) {
default:
llvm_unreachable("Unexpected condition code.");
case ISD::SETOEQ:
case ISD::SETEQ:
- return EQ;
+ return CmpMode::EQ;
case ISD::SETOGT:
case ISD::SETGT:
- return GT;
+ return CmpMode::GT;
case ISD::SETOGE:
case ISD::SETGE:
- return GE;
+ return CmpMode::GE;
case ISD::SETOLT:
case ISD::SETLT:
- return LT;
+ return CmpMode::LT;
case ISD::SETOLE:
case ISD::SETLE:
- return LE;
+ return CmpMode::LE;
case ISD::SETONE:
case ISD::SETNE:
- return NE;
+ return CmpMode::NE;
case ISD::SETO:
- return NUM;
+ return CmpMode::NUM;
case ISD::SETUO:
- return NotANumber;
+ return CmpMode::NotANumber;
case ISD::SETUEQ:
- return EQU;
+ return CmpMode::EQU;
case ISD::SETUGT:
- return GTU;
+ return CmpMode::GTU;
case ISD::SETUGE:
- return GEU;
+ return CmpMode::GEU;
case ISD::SETULT:
- return LTU;
+ return CmpMode::LTU;
case ISD::SETULE:
- return LEU;
+ return CmpMode::LEU;
case ISD::SETUNE:
- return NEU;
+ return CmpMode::NEU;
}
}(CondCode.get());
- return CurDAG->getTargetConstant(Mode, SDLoc(), MVT::i32);
+ return CurDAG->getTargetConstant(PTXCmpMode, SDLoc(), MVT::i32);
}
bool NVPTXDAGToDAGISel::SelectSETP_F16X2(SDNode *N) {
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
index 981cef95e1dad..d9900e98fe694 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
@@ -255,11 +255,65 @@ static bool isScalarFloatSetp(const MachineInstr &MI) {
}
static int64_t invertIntegerCmpMode(int64_t Mode) {
- return NVPTX::PTXCmpMode::lookupCmpModeByValue(Mode)->IntInverseValue;
+ switch (Mode) {
+ case NVPTX::PTXCmpMode::EQ:
+ return NVPTX::PTXCmpMode::NE;
+ case NVPTX::PTXCmpMode::NE:
+ return NVPTX::PTXCmpMode::EQ;
+ case NVPTX::PTXCmpMode::LT:
+ return NVPTX::PTXCmpMode::GE;
+ case NVPTX::PTXCmpMode::LE:
+ return NVPTX::PTXCmpMode::GT;
+ case NVPTX::PTXCmpMode::GT:
+ return NVPTX::PTXCmpMode::LE;
+ case NVPTX::PTXCmpMode::GE:
+ return NVPTX::PTXCmpMode::LT;
+ case NVPTX::PTXCmpMode::LTU:
+ return NVPTX::PTXCmpMode::GEU;
+ case NVPTX::PTXCmpMode::LEU:
+ return NVPTX::PTXCmpMode::GTU;
+ case NVPTX::PTXCmpMode::GTU:
+ return NVPTX::PTXCmpMode::LEU;
+ case NVPTX::PTXCmpMode::GEU:
+ return NVPTX::PTXCmpMode::LTU;
+ default:
+ llvm_unreachable("Invalid integer comparison mode");
+ }
}
static int64_t invertScalarFloatCmpMode(int64_t Mode) {
- return NVPTX::PTXCmpMode::lookupCmpModeByValue(Mode)->FPInverseValue;
+ switch (Mode) {
+ case NVPTX::PTXCmpMode::EQ:
+ return NVPTX::PTXCmpMode::NEU;
+ case NVPTX::PTXCmpMode::NE:
+ return NVPTX::PTXCmpMode::EQU;
+ case NVPTX::PTXCmpMode::EQU:
+ return NVPTX::PTXCmpMode::NE;
+ case NVPTX::PTXCmpMode::NEU:
+ return NVPTX::PTXCmpMode::EQ;
+ case NVPTX::PTXCmpMode::LT:
+ return NVPTX::PTXCmpMode::GEU;
+ case NVPTX::PTXCmpMode::LE:
+ return NVPTX::PTXCmpMode::GTU;
+ case NVPTX::PTXCmpMode::GT:
+ return NVPTX::PTXCmpMode::LEU;
+ case NVPTX::PTXCmpMode::GE:
+ return NVPTX::PTXCmpMode::LTU;
+ case NVPTX::PTXCmpMode::LTU:
+ return NVPTX::PTXCmpMode::GE;
+ case NVPTX::PTXCmpMode::LEU:
+ return NVPTX::PTXCmpMode::GT;
+ case NVPTX::PTXCmpMode::GTU:
+ return NVPTX::PTXCmpMode::LE;
+ case NVPTX::PTXCmpMode::GEU:
+ return NVPTX::PTXCmpMode::LT;
+ case NVPTX::PTXCmpMode::NUM:
+ return NVPTX::PTXCmpMode::NotANumber;
+ case NVPTX::PTXCmpMode::NotANumber:
+ return NVPTX::PTXCmpMode::NUM;
+ default:
+ llvm_unreachable("Invalid scalar float comparison mode");
+ }
}
static void invertScalarCompareInstr(MachineInstr &MI) {
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
index 454dfde39e536..8c7bf72cee147 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
@@ -11,7 +11,6 @@
//===----------------------------------------------------------------------===//
include "NVPTXInstrFormats.td"
-include "llvm/TableGen/SearchableTable.td"
let OperandType = "OPERAND_IMMEDIATE" in {
def f16imm : Operand<f16>;
@@ -83,65 +82,10 @@ def BranchFlag : OperandWithDefaultOps<i1, (ops (i1 0))> {
let PrintMethod = "printNegatedPredicate";
}
-// SETP compare modes
-
-// Sentinel meaning "no valid inverse for this mode".
-defvar CmpModeInvalidInt = 0xFF;
-
-class CmpModeRec<int val, string name,
- int intInv, int fpInv,
- string fcmp, string icmp, string ityp> {
- // Numeric encoding carried by the setp machine operand.
- bits<8> Value = val;
- // Enumerator spelling in NVPTX::PTXCmpMode.
- string Name = name;
- // Inverse predicate under integer-setp semantics
- bits<8> IntInverseValue = intInv;
- // Inverse predicate under scalar-float-setp semantics
- bits<8> FPInverseValue = fpInv;
- // Print mnemonic for float compares.
- string FCmpPrintStr = fcmp;
- // Print mnemonic for int compares.
- string ICmpPrintStr = icmp;
- // Signedness suffix for the integer setp instruction name (b/s/u);
- string ITypePrintStr = ityp;
-}
-
-// val name intInv fpInv fcmp icmp ityp
-def CmpModeEQ_Rec : CmpModeRec<0, "EQ", 1, 7, "eq", "eq", "b">;
-def CmpModeNE_Rec : CmpModeRec<1, "NE", 0, 6, "ne", "ne", "b">;
-def CmpModeLT_Rec : CmpModeRec<2, "LT", 5, 11, "lt", "lt", "s">;
-def CmpModeLE_Rec : CmpModeRec<3, "LE", 4, 10, "le", "le", "s">;
-def CmpModeGT_Rec : CmpModeRec<4, "GT", 3, 9, "gt", "gt", "s">;
-def CmpModeGE_Rec : CmpModeRec<5, "GE", 2, 8, "ge", "ge", "s">;
-def CmpModeEQU_Rec : CmpModeRec<6, "EQU", CmpModeInvalidInt, 1, "equ", "", "">;
-def CmpModeNEU_Rec : CmpModeRec<7, "NEU", CmpModeInvalidInt, 0, "neu", "", "">;
-def CmpModeLTU_Rec : CmpModeRec<8, "LTU", 11, 5, "ltu", "lt", "u">;
-def CmpModeLEU_Rec : CmpModeRec<9, "LEU", 10, 4, "leu", "le", "u">;
-def CmpModeGTU_Rec : CmpModeRec<10, "GTU", 9, 3, "gtu", "gt", "u">;
-def CmpModeGEU_Rec : CmpModeRec<11, "GEU", 8, 2, "geu", "ge", "u">;
-def CmpModeNUM_Rec : CmpModeRec<12, "NUM", CmpModeInvalidInt, 13, "num", "", "">;
-def CmpModeNotANumber_Rec : CmpModeRec<13, "NotANumber", CmpModeInvalidInt, 12, "nan", "", "">;
-
-def PTXCmpMode : GenericEnum {
- let FilterClass = "CmpModeRec";
- let NameField = "Name";
- let ValueField = "Value";
- let UnderlyingType = "unsigned";
-}
-
-def PTXCmpModeTable : GenericTable {
- let FilterClass = "CmpModeRec";
- let CppTypeName = "CmpModeInfo";
- let Fields = ["Value", "Name",
- "IntInverseValue", "FPInverseValue",
- "FCmpPrintStr", "ICmpPrintStr", "ITypePrintStr"];
- let PrimaryKey = ["Value"];
- let PrimaryKeyName = "lookupCmpModeByValue";
-}
-
-def CmpEQ : PatLeaf<(i32 !cast<int>(CmpModeEQ_Rec.Value))>;
-def CmpNE : PatLeaf<(i32 !cast<int>(CmpModeNE_Rec.Value))>;
+// Compare modes
+// These must match the enum in NVPTX.h
+def CmpEQ : PatLeaf<(i32 0)>;
+def CmpNE : PatLeaf<(i32 1)>;
def CmpMode : Operand<i32> {
let PrintMethod = "printCmpMode";
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