[llvm] a529b4c - [RISCV] Fix inconsistent usage of ValVT and LocVT in CC_RISCV_Impl. NFCI (#195368)
via llvm-commits
llvm-commits at lists.llvm.org
Tue May 5 16:46:02 PDT 2026
Author: Craig Topper
Date: 2026-05-05T16:45:57-07:00
New Revision: a529b4ccc23df4b7c66c464539c05eabcea32020
URL: https://github.com/llvm/llvm-project/commit/a529b4ccc23df4b7c66c464539c05eabcea32020
DIFF: https://github.com/llvm/llvm-project/commit/a529b4ccc23df4b7c66c464539c05eabcea32020.diff
LOG: [RISCV] Fix inconsistent usage of ValVT and LocVT in CC_RISCV_Impl. NFCI (#195368)
I think all of our checks should be against LocVT. If LocVT is different
than ValVT, that means the location has already been changed and we
should be acting on that changed type. For the most part, I don't think
that happens for RISC-V.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVCallingConv.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVCallingConv.cpp b/llvm/lib/Target/RISCV/RISCVCallingConv.cpp
index 321e986f6f8fd..c4c3475bd0515 100644
--- a/llvm/lib/Target/RISCV/RISCVCallingConv.cpp
+++ b/llvm/lib/Target/RISCV/RISCVCallingConv.cpp
@@ -318,14 +318,14 @@ static bool CC_RISCVAssign2XLen(CCState &State, CCValAssign VA1,
return false;
}
-static MCRegister allocateRVVReg(MVT ValVT, unsigned ValNo, CCState &State,
+static MCRegister allocateRVVReg(MVT LocVT, unsigned ValNo, CCState &State,
const RISCVTargetLowering &TLI) {
- const TargetRegisterClass *RC = TLI.getRegClassFor(ValVT);
+ const TargetRegisterClass *RC = TLI.getRegClassFor(LocVT);
if (RC == &RISCV::VRRegClass) {
// Assign the first mask argument to V0.
// This is an interim calling convention and it may be changed in the
// future.
- if (ValVT.getVectorElementType() == MVT::i1)
+ if (LocVT.getVectorElementType() == MVT::i1)
if (MCRegister Reg = State.AllocateReg(RISCV::V0))
return Reg;
return State.AllocateReg(ArgVRs);
@@ -368,6 +368,7 @@ static bool CC_RISCV_Impl(unsigned ValNo, MVT ValVT, MVT LocVT,
CCValAssign::LocInfo LocInfo,
ISD::ArgFlagsTy ArgFlags, Type *OrigTy,
CCState &State, bool IsRet) {
+ assert(ValVT == LocVT && "Expected ValVT and LocVT to match");
const MachineFunction &MF = State.getMachineFunction();
const DataLayout &DL = MF.getDataLayout();
const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>();
@@ -400,7 +401,7 @@ static bool CC_RISCV_Impl(unsigned ValNo, MVT ValVT, MVT LocVT,
// Any return value split in to more than two values can't be returned
// directly. Vectors are returned via the available vector registers.
- if ((!LocVT.isVector() || Subtarget.isPExtPackedType(ValVT)) && IsRet &&
+ if ((!LocVT.isVector() || Subtarget.isPExtPackedType(LocVT)) && IsRet &&
ValNo > 1)
return true;
@@ -452,14 +453,14 @@ static bool CC_RISCV_Impl(unsigned ValNo, MVT ValVT, MVT LocVT,
}
}
- if ((ValVT == MVT::f16 && Subtarget.hasStdExtZhinxmin())) {
+ if (LocVT == MVT::f16 && Subtarget.hasStdExtZhinxmin()) {
if (MCRegister Reg = State.AllocateReg(getArgGPR16s(ABI))) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false;
}
}
- if (ValVT == MVT::f32 && Subtarget.hasStdExtZfinx()) {
+ if (LocVT == MVT::f32 && Subtarget.hasStdExtZfinx()) {
if (MCRegister Reg = State.AllocateReg(getArgGPR32s(ABI))) {
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
return false;
@@ -555,7 +556,7 @@ static bool CC_RISCV_Impl(unsigned ValNo, MVT ValVT, MVT LocVT,
// If the split argument only had two elements, it should be passed directly
// in registers or on the stack.
- if ((ValVT.isScalarInteger() || Subtarget.isPExtPackedType(ValVT)) &&
+ if ((LocVT.isScalarInteger() || Subtarget.isPExtPackedType(LocVT)) &&
ArgFlags.isSplitEnd() && PendingLocs.size() <= 1) {
assert(PendingLocs.size() == 1 && "Unexpected PendingLocs.size()");
// Apply the normal calling convention rules to the first half of the
@@ -572,7 +573,7 @@ static bool CC_RISCV_Impl(unsigned ValNo, MVT ValVT, MVT LocVT,
// values. Split vectors excluding P extension packed vectors(see
// isPExtPackedType) are passed via a mix of registers and indirectly, so
// treat them as we would any other argument.
- if ((ValVT.isScalarInteger() || Subtarget.isPExtPackedType(ValVT)) &&
+ if ((LocVT.isScalarInteger() || Subtarget.isPExtPackedType(LocVT)) &&
(ArgFlags.isSplit() || !PendingLocs.empty())) {
PendingLocs.push_back(
CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo));
@@ -589,13 +590,13 @@ static bool CC_RISCV_Impl(unsigned ValNo, MVT ValVT, MVT LocVT,
// FIXME: If P extension and V extension are enabled at the same time,
// who should go first?
- if (!Subtarget.isPExtPackedType(ValVT) &&
- (ValVT.isVector() || ValVT.isRISCVVectorTuple())) {
- Reg = allocateRVVReg(ValVT, ValNo, State, TLI);
+ if (!Subtarget.isPExtPackedType(LocVT) &&
+ (LocVT.isVector() || LocVT.isRISCVVectorTuple())) {
+ Reg = allocateRVVReg(LocVT, ValNo, State, TLI);
if (Reg) {
// Fixed-length vectors are located in the corresponding scalable-vector
// container types.
- if (ValVT.isFixedLengthVector()) {
+ if (LocVT.isFixedLengthVector()) {
LocVT = TLI.getContainerForFixedLengthVector(LocVT);
State.addLoc(
CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
@@ -610,14 +611,14 @@ static bool CC_RISCV_Impl(unsigned ValNo, MVT ValVT, MVT LocVT,
if ((Reg = State.AllocateReg(ArgGPRs))) {
LocVT = XLenVT;
LocInfo = CCValAssign::Indirect;
- } else if (ValVT.isScalableVector()) {
+ } else if (LocVT.isScalableVector()) {
LocVT = XLenVT;
LocInfo = CCValAssign::Indirect;
} else {
- StoreSizeBytes = ValVT.getStoreSize();
+ StoreSizeBytes = LocVT.getStoreSize();
// Align vectors to their element sizes, being careful for vXi1
// vectors.
- StackAlign = MaybeAlign(ValVT.getScalarSizeInBits() / 8).valueOrOne();
+ StackAlign = MaybeAlign(LocVT.getScalarSizeInBits() / 8).valueOrOne();
}
}
} else {
@@ -647,10 +648,10 @@ static bool CC_RISCV_Impl(unsigned ValNo, MVT ValVT, MVT LocVT,
return false;
}
- assert(((ValVT.isFloatingPoint() && !ValVT.isVector()) || LocVT == XLenVT ||
+ assert(((LocVT.isFloatingPoint() && !LocVT.isVector()) || LocVT == XLenVT ||
Subtarget.isPExtPackedType(LocVT) ||
(TLI.getSubtarget().hasVInstructions() &&
- (ValVT.isVector() || ValVT.isRISCVVectorTuple()))) &&
+ (LocVT.isVector() || LocVT.isRISCVVectorTuple()))) &&
"Expected an XLenVT or vector types at this stage");
if (Reg) {
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