[llvm] [LFI][AArch64] Add rewrites for memory accesses (PR #195167)

[Peter Smith via llvm-commits]

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@@ -64,6 +66,97 @@ static bool isPrivilegedTPAccess(const MCInst &Inst) {
   return false;
 }
 
+// Instructions that have mayLoad/mayStore set in TableGen but don't actually
+// perform memory accesses.
+static bool isNotMemAccess(const MCInst &Inst) {
+  switch (Inst.getOpcode()) {
+  case AArch64::DMB:
+  case AArch64::DSB:
+  case AArch64::ISB:
+  case AArch64::HINT:
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smithp35 wrote:

Could be worth a comment here. The HINT can be used for any instruction that's been added in `HINT` space such as `PACIASP` and `BTI` and some additional barrier instructions. In principle a load or store could be encoded in HINT space, although I think it is unlikely.

Perhaps:
// The range of sub-architectures supported by LFI do not include any load or store instructions. 

https://github.com/llvm/llvm-project/pull/195167