[llvm] 7c30772 - [AArch64][GlobalISel] Lower unmerge to extract_subvector (#195046)
via llvm-commits
llvm-commits at lists.llvm.org
Tue May 5 09:39:12 PDT 2026
Author: David Green
Date: 2026-05-05T17:39:07+01:00
New Revision: 7c3077279f73c8bee209ff16b53742f5b8bc5a15
URL: https://github.com/llvm/llvm-project/commit/7c3077279f73c8bee209ff16b53742f5b8bc5a15
DIFF: https://github.com/llvm/llvm-project/commit/7c3077279f73c8bee209ff16b53742f5b8bc5a15.diff
LOG: [AArch64][GlobalISel] Lower unmerge to extract_subvector (#195046)
This follows and reuses the existing lowering for unmerge -> extract
vector element, extending it to also lower unmerge -> subvector extract
for half-sized vector extracts. This allows certain tablegen patterns to
match.
An extra extract_subvector(dup) combine is needed to optimize away
unnecessary instructions. The ext vs mov/dup brings us in-line with
SDAG, but we may change both to use mov/dup.
Added:
Modified:
llvm/lib/Target/AArch64/AArch64Combine.td
llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-unmergedup.mir
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-unmerge-ext.mir
llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
llvm/test/CodeGen/AArch64/aarch64-mulv.ll
llvm/test/CodeGen/AArch64/aarch64-smull.ll
llvm/test/CodeGen/AArch64/arm64-ext.ll
llvm/test/CodeGen/AArch64/arm64-extract_subvector.ll
llvm/test/CodeGen/AArch64/arm64-neon-2velem-high.ll
llvm/test/CodeGen/AArch64/arm64-neon-2velem.ll
llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll
llvm/test/CodeGen/AArch64/arm64-neon-add-pairwise.ll
llvm/test/CodeGen/AArch64/arm64-neon-mul-div.ll
llvm/test/CodeGen/AArch64/arm64-vabs.ll
llvm/test/CodeGen/AArch64/arm64-vadd.ll
llvm/test/CodeGen/AArch64/arm64-vhadd.ll
llvm/test/CodeGen/AArch64/arm64-vmul.ll
llvm/test/CodeGen/AArch64/arm64-vshift.ll
llvm/test/CodeGen/AArch64/bitreverse.ll
llvm/test/CodeGen/AArch64/bswap.ll
llvm/test/CodeGen/AArch64/concat-vector.ll
llvm/test/CodeGen/AArch64/double_reduct.ll
llvm/test/CodeGen/AArch64/dup.ll
llvm/test/CodeGen/AArch64/ext-narrow-index.ll
llvm/test/CodeGen/AArch64/fptoi.ll
llvm/test/CodeGen/AArch64/highextractbitcast.ll
llvm/test/CodeGen/AArch64/neon-extadd.ll
llvm/test/CodeGen/AArch64/neon-perm.ll
llvm/test/CodeGen/AArch64/neon-shift-left-long.ll
llvm/test/CodeGen/AArch64/phi.ll
llvm/test/CodeGen/AArch64/reduce-and.ll
llvm/test/CodeGen/AArch64/reduce-or.ll
llvm/test/CodeGen/AArch64/reduce-xor.ll
llvm/test/CodeGen/AArch64/rem-by-const.ll
llvm/test/CodeGen/AArch64/rem.ll
llvm/test/CodeGen/AArch64/shift.ll
llvm/test/CodeGen/AArch64/st1-lane.ll
llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
llvm/test/CodeGen/AArch64/vecreduce-fmul.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64Combine.td b/llvm/lib/Target/AArch64/AArch64Combine.td
index 84489ab3d107b..287d15dfc7384 100644
--- a/llvm/lib/Target/AArch64/AArch64Combine.td
+++ b/llvm/lib/Target/AArch64/AArch64Combine.td
@@ -173,7 +173,7 @@ def form_duplane : GICombineRule <
>;
// Clean up G_UNMERGE(G_DUPLANE16) -> G_DUPLANE16
-class unmerge_duplane<Instruction Op> : GICombineRule <
+class unmerge_duplane<Instruction Op> : GICombineRule<
(defs root:$root),
(match (Op $a, $src, $c),
(G_UNMERGE_VALUES $d1, $d2, $a):$root,
@@ -184,8 +184,22 @@ def unmerge_duplane8 : unmerge_duplane<G_DUPLANE8>;
def unmerge_duplane16 : unmerge_duplane<G_DUPLANE16>;
def unmerge_duplane32 : unmerge_duplane<G_DUPLANE32>;
// G_DUPLANE64 is not included as the result in scalar.
+
+// G_EXTRACT_SUBVECTOR(G_DUPLANE16) -> G_DUPLANE16
+class extract_duplane<Instruction Op> : GICombineRule<
+ (defs root:$root),
+ (match (Op $a, $src, $c),
+ (G_EXTRACT_SUBVECTOR $d1, $a, $l):$root,
+ [{ return MRI.getType(${d1}.getReg()).getSizeInBits() == 64; }]),
+ (apply (Op $d1, $src, $c))
+>;
+def extract_duplane8 : extract_duplane<G_DUPLANE8>;
+def extract_duplane16 : extract_duplane<G_DUPLANE16>;
+def extract_duplane32 : extract_duplane<G_DUPLANE32>;
+
def unmerge_duplanes : GICombineGroup<[unmerge_duplane8, unmerge_duplane16,
- unmerge_duplane32]>;
+ unmerge_duplane32, extract_duplane8,
+ extract_duplane16, extract_duplane32]>;
def shuffle_vector_lowering : GICombineGroup<[dup, form_duplane, rev, ext, zip,
uzp, trn, fullrev, shuf_to_ins]>;
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index 21e6440d8957c..1a6749b9e5c0c 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -7846,19 +7846,28 @@ AArch64InstructionSelector::selectExtractHigh(MachineOperand &Root) const {
if (!Extract)
return std::nullopt;
- if (Extract->MI->getOpcode() == TargetOpcode::G_UNMERGE_VALUES) {
- if (Extract->Reg == Extract->MI->getOperand(1).getReg()) {
- Register ExtReg = Extract->MI->getOperand(2).getReg();
+ if (auto *Unmerge = dyn_cast<GUnmerge>(Extract->MI)) {
+ if (Unmerge->getNumDefs() == 2 &&
+ Extract->Reg == Unmerge->getOperand(1).getReg()) {
+ Register ExtReg = Unmerge->getSourceReg();
return {{[=](MachineInstrBuilder &MIB) { MIB.addUse(ExtReg); }}};
}
}
- if (Extract->MI->getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT) {
- LLT SrcTy = MRI.getType(Extract->MI->getOperand(1).getReg());
- auto LaneIdx = getIConstantVRegValWithLookThrough(
- Extract->MI->getOperand(2).getReg(), MRI);
+ if (auto *ExtElt = dyn_cast<GExtractVectorElement>(Extract->MI)) {
+ LLT SrcTy = MRI.getType(ExtElt->getVectorReg());
+ auto LaneIdx =
+ getIConstantVRegValWithLookThrough(ExtElt->getIndexReg(), MRI);
if (LaneIdx && SrcTy == LLT::fixed_vector(2, 64) &&
LaneIdx->Value.getSExtValue() == 1) {
- Register ExtReg = Extract->MI->getOperand(1).getReg();
+ Register ExtReg = ExtElt->getVectorReg();
+ return {{[=](MachineInstrBuilder &MIB) { MIB.addUse(ExtReg); }}};
+ }
+ }
+ if (auto *Subvec = dyn_cast<GExtractSubvector>(Extract->MI)) {
+ LLT SrcTy = MRI.getType(Subvec->getSrcVec());
+ auto LaneIdx = Subvec->getIndexImm();
+ if (LaneIdx == SrcTy.getNumElements() / 2) {
+ Register ExtReg = Subvec->getSrcVec();
return {{[=](MachineInstrBuilder &MIB) { MIB.addUse(ExtReg); }}};
}
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
index 433de41f997ec..f4e5649b9f449 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
@@ -830,7 +830,9 @@ bool matchScalarizeVectorUnmerge(MachineInstr &MI, MachineRegisterInfo &MRI) {
if (SrcTy.getSizeInBits() != 128 && SrcTy.getSizeInBits() != 64)
return false;
return SrcTy.isVector() && !SrcTy.isScalable() &&
- Unmerge.getNumOperands() == (unsigned)SrcTy.getNumElements() + 1;
+ (Unmerge.getNumOperands() == (unsigned)SrcTy.getNumElements() + 1 ||
+ (Unmerge.getNumDefs() == 2 && SrcTy.getSizeInBits() == 128 &&
+ MRI.getType(Unmerge.getReg(0)).getSizeInBits() == 64));
}
void applyScalarizeVectorUnmerge(MachineInstr &MI, MachineRegisterInfo &MRI,
@@ -838,11 +840,22 @@ void applyScalarizeVectorUnmerge(MachineInstr &MI, MachineRegisterInfo &MRI,
auto &Unmerge = cast<GUnmerge>(MI);
Register Src1Reg = Unmerge.getReg(Unmerge.getNumOperands() - 1);
const LLT SrcTy = MRI.getType(Src1Reg);
+ const LLT DstTy = MRI.getType(Unmerge.getReg(0));
assert((SrcTy.isVector() && !SrcTy.isScalable()) &&
"Expected a fixed length vector");
- for (int I = 0; I < SrcTy.getNumElements(); ++I)
- B.buildExtractVectorElementConstant(Unmerge.getReg(I), Src1Reg, I);
+ if (DstTy.isVector()) {
+ assert(Unmerge.getNumDefs() == 2);
+ if (!MRI.use_nodbg_empty(Unmerge.getReg(0)))
+ B.buildExtractSubvector(Unmerge.getReg(0), Src1Reg, 0);
+ if (!MRI.use_nodbg_empty(Unmerge.getReg(1)))
+ B.buildExtractSubvector(Unmerge.getReg(1), Src1Reg,
+ SrcTy.getNumElements() / 2);
+ } else {
+ for (int I = 0; I < SrcTy.getNumElements(); ++I)
+ if (!MRI.use_nodbg_empty(Unmerge.getReg(I)))
+ B.buildExtractVectorElementConstant(Unmerge.getReg(I), Src1Reg, I);
+ }
MI.eraseFromParent();
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-unmergedup.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-unmergedup.mir
index 0b533ff85fe86..1a9f8ed88ef4b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-unmergedup.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-unmergedup.mir
@@ -10,8 +10,9 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[DUPLANE8_:%[0-9]+]]:_(<8 x s8>) = G_DUPLANE8 [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[DUPLANE8_1:%[0-9]+]]:_(<8 x s8>) = G_DUPLANE8 [[COPY]], [[C]](s64)
; CHECK-NEXT: $d0 = COPY [[DUPLANE8_]](<8 x s8>)
- ; CHECK-NEXT: $d1 = COPY [[DUPLANE8_]](<8 x s8>)
+ ; CHECK-NEXT: $d1 = COPY [[DUPLANE8_1]](<8 x s8>)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(<16 x s8>) = COPY $q0
%1:_(s64) = G_CONSTANT i64 1
@@ -31,8 +32,9 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[DUPLANE16_:%[0-9]+]]:_(<4 x s16>) = G_DUPLANE16 [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[DUPLANE16_1:%[0-9]+]]:_(<4 x s16>) = G_DUPLANE16 [[COPY]], [[C]](s64)
; CHECK-NEXT: $d0 = COPY [[DUPLANE16_]](<4 x s16>)
- ; CHECK-NEXT: $d1 = COPY [[DUPLANE16_]](<4 x s16>)
+ ; CHECK-NEXT: $d1 = COPY [[DUPLANE16_1]](<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(<8 x s16>) = COPY $q0
%1:_(s64) = G_CONSTANT i64 1
@@ -52,8 +54,9 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[DUPLANE32_:%[0-9]+]]:_(<2 x s32>) = G_DUPLANE32 [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[DUPLANE32_1:%[0-9]+]]:_(<2 x s32>) = G_DUPLANE32 [[COPY]], [[C]](s64)
; CHECK-NEXT: $d0 = COPY [[DUPLANE32_]](<2 x s32>)
- ; CHECK-NEXT: $d1 = COPY [[DUPLANE32_]](<2 x s32>)
+ ; CHECK-NEXT: $d1 = COPY [[DUPLANE32_1]](<2 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(<4 x s32>) = COPY $q0
%1:_(s64) = G_CONSTANT i64 1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-unmerge-ext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-unmerge-ext.mir
index 2452c3083cc86..52ef2d3578b33 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-unmerge-ext.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-unmerge-ext.mir
@@ -11,7 +11,7 @@ body: |
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %v1:_(<4 x s32>) = COPY $q0
- ; CHECK-NEXT: %unused:_(<2 x s32>), %unmerge:_(<2 x s32>) = G_UNMERGE_VALUES %v1(<4 x s32>)
+ ; CHECK-NEXT: %unmerge:_(<2 x s32>) = G_EXTRACT_SUBVECTOR %v1(<4 x s32>), 2
; CHECK-NEXT: %fpext:_(<2 x s64>) = G_FPEXT %unmerge(<2 x s32>)
; CHECK-NEXT: $q0 = COPY %fpext(<2 x s64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
@@ -34,7 +34,7 @@ body: |
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %v1:_(<8 x s16>) = COPY $q0
- ; CHECK-NEXT: %unused:_(<4 x s16>), %unmerge:_(<4 x s16>) = G_UNMERGE_VALUES %v1(<8 x s16>)
+ ; CHECK-NEXT: %unmerge:_(<4 x s16>) = G_EXTRACT_SUBVECTOR %v1(<8 x s16>), 4
; CHECK-NEXT: %fpext:_(<4 x s32>) = G_FPEXT %unmerge(<4 x s16>)
; CHECK-NEXT: $q0 = COPY %fpext(<4 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
@@ -57,7 +57,7 @@ body: |
; CHECK: liveins: $q0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %v1:_(<16 x s8>) = COPY $q0
- ; CHECK-NEXT: %unused:_(<8 x s8>), %unmerge:_(<8 x s8>) = G_UNMERGE_VALUES %v1(<16 x s8>)
+ ; CHECK-NEXT: %unmerge:_(<8 x s8>) = G_EXTRACT_SUBVECTOR %v1(<16 x s8>), 8
; CHECK-NEXT: %fpext:_(<8 x s16>) = G_FPEXT %unmerge(<8 x s8>)
; CHECK-NEXT: $q0 = COPY %fpext(<8 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
@@ -83,7 +83,7 @@ body: |
; CHECK-NEXT: %implicit:_(<16 x s8>) = G_IMPLICIT_DEF
; CHECK-NEXT: %C:_(s32) = COPY $w0
; CHECK-NEXT: %ext:_(<16 x s8>) = G_EXT %v1, %implicit, %C(s32)
- ; CHECK-NEXT: %unmerge:_(<8 x s8>), %unused:_(<8 x s8>) = G_UNMERGE_VALUES %ext(<16 x s8>)
+ ; CHECK-NEXT: %unmerge:_(<8 x s8>) = G_EXTRACT_SUBVECTOR %ext(<16 x s8>), 0
; CHECK-NEXT: %fpext:_(<8 x s16>) = G_FPEXT %unmerge(<8 x s8>)
; CHECK-NEXT: $q0 = COPY %fpext(<8 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
@@ -109,7 +109,8 @@ body: |
; CHECK-NEXT: %implicit:_(<16 x s8>) = G_IMPLICIT_DEF
; CHECK-NEXT: %C:_(s32) = G_CONSTANT i32 8
; CHECK-NEXT: %ext:_(<16 x s8>) = G_EXT %v1, %implicit, %C(s32)
- ; CHECK-NEXT: %unmerge:_(<8 x s8>), %unused:_(<8 x s8>) = G_UNMERGE_VALUES %ext(<16 x s8>)
+ ; CHECK-NEXT: %unmerge:_(<8 x s8>) = G_EXTRACT_SUBVECTOR %ext(<16 x s8>), 0
+ ; CHECK-NEXT: %unused:_(<8 x s8>) = G_EXTRACT_SUBVECTOR %ext(<16 x s8>), 8
; CHECK-NEXT: %fpext:_(<8 x s16>) = G_FPEXT %unmerge(<8 x s8>)
; CHECK-NEXT: %fpext2:_(<8 x s16>) = G_FPEXT %unused(<8 x s8>)
; CHECK-NEXT: $q0 = COPY %fpext(<8 x s16>)
@@ -139,7 +140,7 @@ body: |
; CHECK-NEXT: %implicit:_(<4 x s32>) = G_IMPLICIT_DEF
; CHECK-NEXT: %C:_(s32) = G_CONSTANT i32 9
; CHECK-NEXT: %ext:_(<4 x s32>) = G_EXT %v1, %implicit, %C(s32)
- ; CHECK-NEXT: %unmerge:_(<2 x s32>), %unused:_(<2 x s32>) = G_UNMERGE_VALUES %ext(<4 x s32>)
+ ; CHECK-NEXT: %unmerge:_(<2 x s32>) = G_EXTRACT_SUBVECTOR %ext(<4 x s32>), 0
; CHECK-NEXT: %fpext:_(<2 x s64>) = G_FPEXT %unmerge(<2 x s32>)
; CHECK-NEXT: $q0 = COPY %fpext(<2 x s64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
diff --git a/llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll b/llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
index 9dfbe1a7f27e8..2334e0603ee43 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
@@ -308,7 +308,7 @@ define <2 x i16> @dupsext_v2i8_v2i16(i8 %src, <2 x i8> %b) {
; CHECK-GI-NEXT: sbfx w8, w8, #8, #8
; CHECK-GI-NEXT: sshr v0.2s, v0.2s, #24
; CHECK-GI-NEXT: dup v1.4h, w8
-; CHECK-GI-NEXT: ushll v1.4s, v1.4h, #0
+; CHECK-GI-NEXT: zip1 v1.4h, v1.4h, v1.4h
; CHECK-GI-NEXT: mul v0.2s, v1.2s, v0.2s
; CHECK-GI-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll b/llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
index ea55c198a70f1..b6e9d248a2d26 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
@@ -321,8 +321,8 @@ define void @larger_smull(ptr nocapture noundef readonly %x, i16 noundef %y, ptr
; CHECK-GI-NEXT: mov x14, x11
; CHECK-GI-NEXT: subs x13, x13, #16
; CHECK-GI-NEXT: add x12, x12, #32
-; CHECK-GI-NEXT: mov d3, v1.d[1]
-; CHECK-GI-NEXT: mov d4, v2.d[1]
+; CHECK-GI-NEXT: ext v3.16b, v1.16b, v1.16b, #8
+; CHECK-GI-NEXT: ext v4.16b, v2.16b, v2.16b, #8
; CHECK-GI-NEXT: smull v1.4s, v0.4h, v1.4h
; CHECK-GI-NEXT: smull v2.4s, v0.4h, v2.4h
; CHECK-GI-NEXT: smull v3.4s, v0.4h, v3.4h
@@ -481,8 +481,8 @@ define void @larger_umull(ptr nocapture noundef readonly %x, i16 noundef %y, ptr
; CHECK-GI-NEXT: mov x13, x10
; CHECK-GI-NEXT: subs x12, x12, #16
; CHECK-GI-NEXT: add x11, x11, #32
-; CHECK-GI-NEXT: mov d3, v1.d[1]
-; CHECK-GI-NEXT: mov d4, v2.d[1]
+; CHECK-GI-NEXT: ext v3.16b, v1.16b, v1.16b, #8
+; CHECK-GI-NEXT: ext v4.16b, v2.16b, v2.16b, #8
; CHECK-GI-NEXT: xtn v0.4h, v0.4s
; CHECK-GI-NEXT: umull v1.4s, v0.4h, v1.4h
; CHECK-GI-NEXT: umull v3.4s, v0.4h, v3.4h
@@ -909,10 +909,10 @@ define i64 @red_mla_dup_ext_u8_s8_s64(ptr noalias noundef readonly captures(none
; CHECK-GI-NEXT: ushll2 v18.4s, v18.8h, #0
; CHECK-GI-NEXT: ushll v20.4s, v17.4h, #0
; CHECK-GI-NEXT: ushll2 v17.4s, v17.8h, #0
-; CHECK-GI-NEXT: mov d21, v19.d[1]
-; CHECK-GI-NEXT: mov d22, v18.d[1]
-; CHECK-GI-NEXT: mov d23, v20.d[1]
-; CHECK-GI-NEXT: mov d24, v17.d[1]
+; CHECK-GI-NEXT: ext v21.16b, v19.16b, v19.16b, #8
+; CHECK-GI-NEXT: ext v22.16b, v18.16b, v18.16b, #8
+; CHECK-GI-NEXT: ext v23.16b, v20.16b, v20.16b, #8
+; CHECK-GI-NEXT: ext v24.16b, v17.16b, v17.16b, #8
; CHECK-GI-NEXT: smlal v0.2d, v16.2s, v19.2s
; CHECK-GI-NEXT: smlal v2.2d, v16.2s, v18.2s
; CHECK-GI-NEXT: smlal v4.2d, v16.2s, v20.2s
@@ -1176,7 +1176,7 @@ define void @sink_v4i64_1(ptr %p, ptr %d, i64 %n, <2 x i32> %a) {
; CHECK-GI-NEXT: ldr q1, [x0]
; CHECK-GI-NEXT: subs x2, x2, #8
; CHECK-GI-NEXT: add x8, x8, #8
-; CHECK-GI-NEXT: mov d2, v1.d[1]
+; CHECK-GI-NEXT: ext v2.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: smull v1.2d, v1.2s, v0.2s
; CHECK-GI-NEXT: smull v2.2d, v2.2s, v0.2s
; CHECK-GI-NEXT: shrn v1.2s, v1.2d, #15
@@ -1302,7 +1302,7 @@ define void @sink_v16s16_8(ptr %p, ptr %d, i64 %n, <16 x i8> %a) {
; CHECK-GI-NEXT: ldr q1, [x0]
; CHECK-GI-NEXT: subs x2, x2, #8
; CHECK-GI-NEXT: add x8, x8, #8
-; CHECK-GI-NEXT: mov d2, v1.d[1]
+; CHECK-GI-NEXT: ext v2.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: smull v1.8h, v1.8b, v0.8b
; CHECK-GI-NEXT: smull v2.8h, v2.8b, v0.8b
; CHECK-GI-NEXT: cmlt v1.8h, v1.8h, #0
@@ -1460,8 +1460,8 @@ define void @matrix_mul_unsigned_and_double(i32 %N, ptr nocapture %C, ptr nocapt
; CHECK-GI-NEXT: ldur q2, [x9, #8]
; CHECK-GI-NEXT: add x9, x1, w0, uxtw #2
; CHECK-GI-NEXT: add w0, w0, #16
-; CHECK-GI-NEXT: mov d3, v1.d[1]
-; CHECK-GI-NEXT: mov d4, v2.d[1]
+; CHECK-GI-NEXT: ext v3.16b, v1.16b, v1.16b, #8
+; CHECK-GI-NEXT: ext v4.16b, v2.16b, v2.16b, #8
; CHECK-GI-NEXT: umull v1.4s, v0.4h, v1.4h
; CHECK-GI-NEXT: umull v2.4s, v0.4h, v2.4h
; CHECK-GI-NEXT: umull v3.4s, v0.4h, v3.4h
@@ -1731,7 +1731,7 @@ define noundef <8 x i16> @cmplx_mul_combined_re_im(<8 x i16> noundef %a, i64 %sc
; CHECK-GI-NEXT: sqneg v2.8h, v1.8h
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI15_0]
; CHECK-GI-NEXT: tbl v1.16b, { v2.16b, v3.16b }, v1.16b
-; CHECK-GI-NEXT: mov d2, v0.d[1]
+; CHECK-GI-NEXT: ext v2.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: dup v3.8h, w0
; CHECK-GI-NEXT: sqdmull v2.4s, v2.4h, v3.4h
; CHECK-GI-NEXT: sqdmull v5.4s, v4.4h, v1.4h
diff --git a/llvm/test/CodeGen/AArch64/aarch64-mulv.ll b/llvm/test/CodeGen/AArch64/aarch64-mulv.ll
index 954e8e422b55f..ce62dba4400d1 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-mulv.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-mulv.ll
@@ -153,7 +153,7 @@ define i8 @mulv_v16i8(<16 x i8> %a) {
;
; CHECK-GI-LABEL: mulv_v16i8:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: mul v0.8b, v0.8b, v1.8b
; CHECK-GI-NEXT: umov w8, v0.b[0]
; CHECK-GI-NEXT: umov w9, v0.b[1]
@@ -201,8 +201,8 @@ define i8 @mulv_v32i8(<32 x i8> %a) {
;
; CHECK-GI-LABEL: mulv_v32i8:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d2, v0.d[1]
-; CHECK-GI-NEXT: mov d3, v1.d[1]
+; CHECK-GI-NEXT: ext v2.16b, v0.16b, v0.16b, #8
+; CHECK-GI-NEXT: ext v3.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: mul v0.8b, v0.8b, v2.8b
; CHECK-GI-NEXT: mul v1.8b, v1.8b, v3.8b
; CHECK-GI-NEXT: mul v0.8b, v0.8b, v1.8b
@@ -317,7 +317,7 @@ define i16 @mulv_v8i16(<8 x i16> %a) {
;
; CHECK-GI-LABEL: mulv_v8i16:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: mul v0.4h, v0.4h, v1.4h
; CHECK-GI-NEXT: umov w8, v0.h[0]
; CHECK-GI-NEXT: umov w9, v0.h[1]
@@ -349,8 +349,8 @@ define i16 @mulv_v16i16(<16 x i16> %a) {
;
; CHECK-GI-LABEL: mulv_v16i16:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d2, v0.d[1]
-; CHECK-GI-NEXT: mov d3, v1.d[1]
+; CHECK-GI-NEXT: ext v2.16b, v0.16b, v0.16b, #8
+; CHECK-GI-NEXT: ext v3.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: mul v0.4h, v0.4h, v2.4h
; CHECK-GI-NEXT: mul v1.4h, v1.4h, v3.4h
; CHECK-GI-NEXT: mul v0.4h, v0.4h, v1.4h
@@ -414,7 +414,7 @@ define i32 @mulv_v4i32(<4 x i32> %a) {
;
; CHECK-GI-LABEL: mulv_v4i32:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: mul v0.2s, v0.2s, v1.2s
; CHECK-GI-NEXT: mov w8, v0.s[1]
; CHECK-GI-NEXT: fmov w9, s0
@@ -437,8 +437,8 @@ define i32 @mulv_v8i32(<8 x i32> %a) {
;
; CHECK-GI-LABEL: mulv_v8i32:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d2, v0.d[1]
-; CHECK-GI-NEXT: mov d3, v1.d[1]
+; CHECK-GI-NEXT: ext v2.16b, v0.16b, v0.16b, #8
+; CHECK-GI-NEXT: ext v3.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: mul v0.2s, v0.2s, v2.2s
; CHECK-GI-NEXT: mul v1.2s, v1.2s, v3.2s
; CHECK-GI-NEXT: mul v0.2s, v0.2s, v1.2s
diff --git a/llvm/test/CodeGen/AArch64/aarch64-smull.ll b/llvm/test/CodeGen/AArch64/aarch64-smull.ll
index 5896b408be49c..ee5b2e00c6a69 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-smull.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-smull.ll
@@ -1726,7 +1726,7 @@ define <8 x i32> @umull_and_v8i32(<8 x i16> %src1, <8 x i32> %src2) {
; CHECK-GI-NEXT: movi v3.2d, #0x0000ff000000ff
; CHECK-GI-NEXT: and v1.16b, v1.16b, v3.16b
; CHECK-GI-NEXT: and v2.16b, v2.16b, v3.16b
-; CHECK-GI-NEXT: mov d3, v0.d[1]
+; CHECK-GI-NEXT: ext v3.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: xtn v1.4h, v1.4s
; CHECK-GI-NEXT: xtn v2.4h, v2.4s
; CHECK-GI-NEXT: umull v0.4s, v0.4h, v1.4h
@@ -1759,7 +1759,7 @@ define <8 x i32> @umull_and_v8i32_dup(<8 x i16> %src1, i32 %src2) {
; CHECK-GI-LABEL: umull_and_v8i32_dup:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: and w8, w0, #0xff
-; CHECK-GI-NEXT: mov d2, v0.d[1]
+; CHECK-GI-NEXT: ext v2.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: dup v1.4s, w8
; CHECK-GI-NEXT: xtn v1.4h, v1.4s
; CHECK-GI-NEXT: umull v0.4s, v0.4h, v1.4h
@@ -1832,7 +1832,7 @@ define <4 x i64> @umull_and_v4i64(<4 x i32> %src1, <4 x i64> %src2) {
; CHECK-GI-NEXT: movi v3.2d, #0x000000000000ff
; CHECK-GI-NEXT: and v1.16b, v1.16b, v3.16b
; CHECK-GI-NEXT: and v2.16b, v2.16b, v3.16b
-; CHECK-GI-NEXT: mov d3, v0.d[1]
+; CHECK-GI-NEXT: ext v3.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: xtn v1.2s, v1.2d
; CHECK-GI-NEXT: xtn v2.2s, v2.2d
; CHECK-GI-NEXT: umull v0.2d, v0.2s, v1.2s
@@ -1865,7 +1865,7 @@ define <4 x i64> @umull_and_v4i64_dup(<4 x i32> %src1, i64 %src2) {
; CHECK-GI-LABEL: umull_and_v4i64_dup:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: and x8, x0, #0xff
-; CHECK-GI-NEXT: mov d2, v0.d[1]
+; CHECK-GI-NEXT: ext v2.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: dup v1.2d, x8
; CHECK-GI-NEXT: xtn v1.2s, v1.2d
; CHECK-GI-NEXT: umull v0.2d, v0.2s, v1.2s
@@ -1902,7 +1902,7 @@ define void @pmlsl2_v8i16_uzp1(<16 x i8> %0, <8 x i16> %1, ptr %2, ptr %3) {
; CHECK-GI-LABEL: pmlsl2_v8i16_uzp1:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: ldr q2, [x1, #16]
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: xtn v2.8b, v2.8h
; CHECK-GI-NEXT: pmull v0.8h, v0.8b, v2.8b
; CHECK-GI-NEXT: sub v0.8h, v1.8h, v0.8h
@@ -1938,7 +1938,7 @@ define void @smlsl2_v8i16_uzp1(<16 x i8> %0, <8 x i16> %1, ptr %2, ptr %3) {
; CHECK-GI-LABEL: smlsl2_v8i16_uzp1:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: ldr q2, [x1, #16]
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: xtn v2.8b, v2.8h
; CHECK-GI-NEXT: smlsl v1.8h, v0.8b, v2.8b
; CHECK-GI-NEXT: str q1, [x0]
@@ -1973,7 +1973,7 @@ define void @umlsl2_v8i16_uzp1(<16 x i8> %0, <8 x i16> %1, ptr %2, ptr %3) {
; CHECK-GI-LABEL: umlsl2_v8i16_uzp1:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: ldr q2, [x1, #16]
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: xtn v2.8b, v2.8h
; CHECK-GI-NEXT: umlsl v1.8h, v0.8b, v2.8b
; CHECK-GI-NEXT: str q1, [x0]
@@ -2008,7 +2008,7 @@ define void @smlsl2_v4i32_uzp1(<8 x i16> %0, <4 x i32> %1, ptr %2, ptr %3) {
; CHECK-GI-LABEL: smlsl2_v4i32_uzp1:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: ldr q2, [x1, #16]
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: xtn v2.4h, v2.4s
; CHECK-GI-NEXT: smlsl v1.4s, v0.4h, v2.4h
; CHECK-GI-NEXT: str q1, [x0]
@@ -2043,7 +2043,7 @@ define void @umlsl2_v4i32_uzp1(<8 x i16> %0, <4 x i32> %1, ptr %2, ptr %3) {
; CHECK-GI-LABEL: umlsl2_v4i32_uzp1:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: ldr q2, [x1, #16]
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: xtn v2.4h, v2.4s
; CHECK-GI-NEXT: umlsl v1.4s, v0.4h, v2.4h
; CHECK-GI-NEXT: str q1, [x0]
@@ -2084,7 +2084,7 @@ define void @pmlsl_pmlsl2_v8i16_uzp1(<16 x i8> %0, <8 x i16> %1, ptr %2, ptr %3,
; CHECK-GI-LABEL: pmlsl_pmlsl2_v8i16_uzp1:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: ldp q2, q3, [x1]
-; CHECK-GI-NEXT: mov d4, v0.d[1]
+; CHECK-GI-NEXT: ext v4.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: xtn v2.8b, v2.8h
; CHECK-GI-NEXT: xtn v3.8b, v3.8h
; CHECK-GI-NEXT: pmull v0.8h, v0.8b, v2.8b
@@ -2131,7 +2131,7 @@ define void @smlsl_smlsl2_v8i16_uzp1(<16 x i8> %0, <8 x i16> %1, ptr %2, ptr %3,
; CHECK-GI-LABEL: smlsl_smlsl2_v8i16_uzp1:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: ldp q2, q3, [x1]
-; CHECK-GI-NEXT: mov d4, v0.d[1]
+; CHECK-GI-NEXT: ext v4.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: xtn v2.8b, v2.8h
; CHECK-GI-NEXT: xtn v3.8b, v3.8h
; CHECK-GI-NEXT: smlsl v1.8h, v0.8b, v2.8b
@@ -2176,7 +2176,7 @@ define void @umlsl_umlsl2_v8i16_uzp1(<16 x i8> %0, <8 x i16> %1, ptr %2, ptr %3,
; CHECK-GI-LABEL: umlsl_umlsl2_v8i16_uzp1:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: ldp q2, q3, [x1]
-; CHECK-GI-NEXT: mov d4, v0.d[1]
+; CHECK-GI-NEXT: ext v4.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: xtn v2.8b, v2.8h
; CHECK-GI-NEXT: xtn v3.8b, v3.8h
; CHECK-GI-NEXT: umlsl v1.8h, v0.8b, v2.8b
@@ -2221,7 +2221,7 @@ define void @smlsl_smlsl2_v4i32_uzp1(<8 x i16> %0, <4 x i32> %1, ptr %2, ptr %3,
; CHECK-GI-LABEL: smlsl_smlsl2_v4i32_uzp1:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: ldp q2, q3, [x1]
-; CHECK-GI-NEXT: mov d4, v0.d[1]
+; CHECK-GI-NEXT: ext v4.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: xtn v2.4h, v2.4s
; CHECK-GI-NEXT: xtn v3.4h, v3.4s
; CHECK-GI-NEXT: smlsl v1.4s, v0.4h, v2.4h
@@ -2266,7 +2266,7 @@ define void @umlsl_umlsl2_v4i32_uzp1(<8 x i16> %0, <4 x i32> %1, ptr %2, ptr %3,
; CHECK-GI-LABEL: umlsl_umlsl2_v4i32_uzp1:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: ldp q2, q3, [x1]
-; CHECK-GI-NEXT: mov d4, v0.d[1]
+; CHECK-GI-NEXT: ext v4.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: xtn v2.4h, v2.4s
; CHECK-GI-NEXT: xtn v3.4h, v3.4s
; CHECK-GI-NEXT: umlsl v1.4s, v0.4h, v2.4h
@@ -2309,7 +2309,7 @@ define <2 x i32> @do_stuff(<2 x i64> %0, <2 x i64> %1) {
; CHECK-GI-LABEL: do_stuff:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: xtn v0.2s, v0.2d
-; CHECK-GI-NEXT: mov d2, v1.d[1]
+; CHECK-GI-NEXT: ext v2.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: smull v0.2d, v2.2s, v0.2s
; CHECK-GI-NEXT: xtn v0.2s, v0.2d
; CHECK-GI-NEXT: add v0.2s, v0.2s, v1.2s
diff --git a/llvm/test/CodeGen/AArch64/arm64-ext.ll b/llvm/test/CodeGen/AArch64/arm64-ext.ll
index c3670579c9148..85653874c18cb 100644
--- a/llvm/test/CodeGen/AArch64/arm64-ext.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-ext.ll
@@ -146,7 +146,7 @@ define <16 x i8> @reverse_vector_s8x16b(<16 x i8> noundef %x) {
; CHECK-GI-LABEL: reverse_vector_s8x16b:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: rev64 v1.16b, v0.16b
-; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ret
entry:
@@ -167,7 +167,7 @@ define <8 x i16> @reverse_vector_s16x8b(<8 x i16> noundef %x) {
; CHECK-GI-LABEL: reverse_vector_s16x8b:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: rev64 v1.8h, v0.8h
-; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ret
entry:
@@ -188,7 +188,7 @@ define <4 x i32> @reverse_vector_s32x4b(<4 x i32> noundef %x) {
; CHECK-GI-LABEL: reverse_vector_s32x4b:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: rev64 v1.4s, v0.4s
-; CHECK-GI-NEXT: mov d0, v1.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/AArch64/arm64-extract_subvector.ll b/llvm/test/CodeGen/AArch64/arm64-extract_subvector.ll
index aaabb442e764a..1a4c7d8499b43 100644
--- a/llvm/test/CodeGen/AArch64/arm64-extract_subvector.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-extract_subvector.ll
@@ -5,46 +5,31 @@
; Extract of an upper half of a vector is an "ext.16b v0, v0, v0, #8" insn.
define <8 x i8> @v8i8(<16 x i8> %a) nounwind {
-; CHECK-SD-LABEL: v8i8:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext.16b v0, v0, v0, #8
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: v8i8:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d0, v0[1]
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: v8i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext.16b v0, v0, v0, #8
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
%ret = shufflevector <16 x i8> %a, <16 x i8> %a, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
ret <8 x i8> %ret
}
define <4 x i16> @v4i16(<8 x i16> %a) nounwind {
-; CHECK-SD-LABEL: v4i16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext.16b v0, v0, v0, #8
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: v4i16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d0, v0[1]
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: v4i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext.16b v0, v0, v0, #8
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
%ret = shufflevector <8 x i16> %a, <8 x i16> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
ret <4 x i16> %ret
}
define <2 x i32> @v2i32(<4 x i32> %a) nounwind {
-; CHECK-SD-LABEL: v2i32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext.16b v0, v0, v0, #8
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: v2i32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d0, v0[1]
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: v2i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext.16b v0, v0, v0, #8
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
%ret = shufflevector <4 x i32> %a, <4 x i32> %a, <2 x i32> <i32 2, i32 3>
ret <2 x i32> %ret
}
@@ -80,16 +65,11 @@ define <1 x ptr> @v1p0(<2 x ptr> %a) nounwind {
}
define <2 x float> @v2f32(<4 x float> %a) nounwind {
-; CHECK-SD-LABEL: v2f32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext.16b v0, v0, v0, #8
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: v2f32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d0, v0[1]
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: v2f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext.16b v0, v0, v0, #8
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
%ret = shufflevector <4 x float> %a, <4 x float> %a, <2 x i32> <i32 2, i32 3>
ret <2 x float> %ret
}
@@ -109,5 +89,3 @@ define <1 x double> @v1f64(<2 x double> %a) nounwind {
ret <1 x double> %ret
}
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; CHECK: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-2velem-high.ll b/llvm/test/CodeGen/AArch64/arm64-neon-2velem-high.ll
index 7581671a51f60..daf70859abfd6 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-2velem-high.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-2velem-high.ll
@@ -14,7 +14,7 @@ define <4 x i32> @test_vmull_high_n_s16(<8 x i16> %a, i16 %b) #0 {
;
; CHECK-GI-LABEL: test_vmull_high_n_s16:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: dup v1.4h, w0
; CHECK-GI-NEXT: smull v0.4s, v0.4h, v1.4h
; CHECK-GI-NEXT: ret
@@ -38,7 +38,7 @@ define <4 x i32> @test_vmull_high_n_s16_imm(<8 x i16> %a) #0 {
; CHECK-GI-LABEL: test_vmull_high_n_s16_imm:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: movi v1.4h, #29
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: smull v0.4s, v0.4h, v1.4h
; CHECK-GI-NEXT: ret
entry:
@@ -56,7 +56,7 @@ define <2 x i64> @test_vmull_high_n_s32(<4 x i32> %a, i32 %b) #0 {
;
; CHECK-GI-LABEL: test_vmull_high_n_s32:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: dup v1.2s, w0
; CHECK-GI-NEXT: smull v0.2d, v0.2s, v1.2s
; CHECK-GI-NEXT: ret
@@ -78,7 +78,7 @@ define <2 x i64> @test_vmull_high_n_s32_imm(<4 x i32> %a) #0 {
; CHECK-GI-LABEL: test_vmull_high_n_s32_imm:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: movi v1.2s, #1, msl #8
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: smull v0.2d, v0.2s, v1.2s
; CHECK-GI-NEXT: ret
entry:
@@ -96,7 +96,7 @@ define <4 x i32> @test_vmull_high_n_u16(<8 x i16> %a, i16 %b) #0 {
;
; CHECK-GI-LABEL: test_vmull_high_n_u16:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: dup v1.4h, w0
; CHECK-GI-NEXT: umull v0.4s, v0.4h, v1.4h
; CHECK-GI-NEXT: ret
@@ -120,7 +120,7 @@ define <4 x i32> @test_vmull_high_n_u16_imm(<8 x i16> %a) #0 {
; CHECK-GI-LABEL: test_vmull_high_n_u16_imm:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: movi v1.4h, #17, lsl #8
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: umull v0.4s, v0.4h, v1.4h
; CHECK-GI-NEXT: ret
entry:
@@ -138,7 +138,7 @@ define <2 x i64> @test_vmull_high_n_u32(<4 x i32> %a, i32 %b) #0 {
;
; CHECK-GI-LABEL: test_vmull_high_n_u32:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: dup v1.2s, w0
; CHECK-GI-NEXT: umull v0.2d, v0.2s, v1.2s
; CHECK-GI-NEXT: ret
@@ -159,7 +159,7 @@ define <2 x i64> @test_vmull_high_n_u32_imm(<4 x i32> %a) #0 {
;
; CHECK-GI-LABEL: test_vmull_high_n_u32_imm:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: mvni v1.2s, #1, msl #8
; CHECK-GI-NEXT: umull v0.2d, v0.2s, v1.2s
; CHECK-GI-NEXT: ret
@@ -178,7 +178,7 @@ define <4 x i32> @test_vqdmull_high_n_s16(<8 x i16> %a, i16 %b) #0 {
;
; CHECK-GI-LABEL: test_vqdmull_high_n_s16:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: dup v1.4h, w0
; CHECK-GI-NEXT: sqdmull v0.4s, v0.4h, v1.4h
; CHECK-GI-NEXT: ret
@@ -201,7 +201,7 @@ define <4 x i32> @test_vqdmull_high_n_s16_imm(<8 x i16> %a) #0 {
;
; CHECK-GI-LABEL: test_vqdmull_high_n_s16_imm:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: mvni v1.4h, #17, lsl #8
; CHECK-GI-NEXT: sqdmull v0.4s, v0.4h, v1.4h
; CHECK-GI-NEXT: ret
@@ -220,7 +220,7 @@ define <2 x i64> @test_vqdmull_high_n_s32(<4 x i32> %a, i32 %b) #0 {
;
; CHECK-GI-LABEL: test_vqdmull_high_n_s32:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: dup v1.2s, w0
; CHECK-GI-NEXT: sqdmull v0.2d, v0.2s, v1.2s
; CHECK-GI-NEXT: ret
@@ -242,7 +242,7 @@ define <2 x i64> @test_vqdmull_high_n_s32_imm(<4 x i32> %a) #0 {
; CHECK-GI-LABEL: test_vqdmull_high_n_s32_imm:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: movi v1.2s, #29
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: sqdmull v0.2d, v0.2s, v1.2s
; CHECK-GI-NEXT: ret
entry:
@@ -260,7 +260,7 @@ define <4 x i32> @test_vmlal_high_n_s16(<4 x i32> %a, <8 x i16> %b, i16 %c) #0 {
;
; CHECK-GI-LABEL: test_vmlal_high_n_s16:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: dup v2.4h, w0
; CHECK-GI-NEXT: smlal v0.4s, v1.4h, v2.4h
; CHECK-GI-NEXT: ret
@@ -285,7 +285,7 @@ define <4 x i32> @test_vmlal_high_n_s16_imm(<4 x i32> %a, <8 x i16> %b) #0 {
; CHECK-GI-LABEL: test_vmlal_high_n_s16_imm:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: movi v2.4h, #29
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: smlal v0.4s, v1.4h, v2.4h
; CHECK-GI-NEXT: ret
entry:
@@ -304,7 +304,7 @@ define <2 x i64> @test_vmlal_high_n_s32(<2 x i64> %a, <4 x i32> %b, i32 %c) #0 {
;
; CHECK-GI-LABEL: test_vmlal_high_n_s32:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: dup v2.2s, w0
; CHECK-GI-NEXT: smlal v0.2d, v1.2s, v2.2s
; CHECK-GI-NEXT: ret
@@ -327,7 +327,7 @@ define <2 x i64> @test_vmlal_high_n_s32_imm(<2 x i64> %a, <4 x i32> %b) #0 {
; CHECK-GI-LABEL: test_vmlal_high_n_s32_imm:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: movi v2.2s, #29
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: smlal v0.2d, v1.2s, v2.2s
; CHECK-GI-NEXT: ret
entry:
@@ -346,7 +346,7 @@ define <4 x i32> @test_vmlal_high_n_u16(<4 x i32> %a, <8 x i16> %b, i16 %c) #0 {
;
; CHECK-GI-LABEL: test_vmlal_high_n_u16:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: dup v2.4h, w0
; CHECK-GI-NEXT: umlal v0.4s, v1.4h, v2.4h
; CHECK-GI-NEXT: ret
@@ -371,7 +371,7 @@ define <4 x i32> @test_vmlal_high_n_u16_imm(<4 x i32> %a, <8 x i16> %b) #0 {
; CHECK-GI-LABEL: test_vmlal_high_n_u16_imm:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: movi v2.4h, #29
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: umlal v0.4s, v1.4h, v2.4h
; CHECK-GI-NEXT: ret
entry:
@@ -390,7 +390,7 @@ define <2 x i64> @test_vmlal_high_n_u32(<2 x i64> %a, <4 x i32> %b, i32 %c) #0 {
;
; CHECK-GI-LABEL: test_vmlal_high_n_u32:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: dup v2.2s, w0
; CHECK-GI-NEXT: umlal v0.2d, v1.2s, v2.2s
; CHECK-GI-NEXT: ret
@@ -413,7 +413,7 @@ define <2 x i64> @test_vmlal_high_n_u32_imm(<2 x i64> %a, <4 x i32> %b) #0 {
; CHECK-GI-LABEL: test_vmlal_high_n_u32_imm:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: movi v2.2s, #29
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: umlal v0.2d, v1.2s, v2.2s
; CHECK-GI-NEXT: ret
entry:
@@ -432,7 +432,7 @@ define <4 x i32> @test_vqdmlal_high_n_s16(<4 x i32> %a, <8 x i16> %b, i16 %c) #0
;
; CHECK-GI-LABEL: test_vqdmlal_high_n_s16:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: dup v2.4h, w0
; CHECK-GI-NEXT: sqdmlal v0.4s, v1.4h, v2.4h
; CHECK-GI-NEXT: ret
@@ -457,7 +457,7 @@ define <4 x i32> @test_vqdmlal_high_n_s16_imm(<4 x i32> %a, <8 x i16> %b) #0 {
; CHECK-GI-LABEL: test_vqdmlal_high_n_s16_imm:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: movi v2.4h, #29
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: sqdmlal v0.4s, v1.4h, v2.4h
; CHECK-GI-NEXT: ret
entry:
@@ -476,7 +476,7 @@ define <2 x i64> @test_vqdmlal_high_n_s32(<2 x i64> %a, <4 x i32> %b, i32 %c) #0
;
; CHECK-GI-LABEL: test_vqdmlal_high_n_s32:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: dup v2.2s, w0
; CHECK-GI-NEXT: sqdmlal v0.2d, v1.2s, v2.2s
; CHECK-GI-NEXT: ret
@@ -499,7 +499,7 @@ define <2 x i64> @test_vqdmlal_high_n_s32_imm(<2 x i64> %a, <4 x i32> %b) #0 {
; CHECK-GI-LABEL: test_vqdmlal_high_n_s32_imm:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: movi v2.2s, #29
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: sqdmlal v0.2d, v1.2s, v2.2s
; CHECK-GI-NEXT: ret
entry:
@@ -518,7 +518,7 @@ define <4 x i32> @test_vmlsl_high_n_s16(<4 x i32> %a, <8 x i16> %b, i16 %c) #0 {
;
; CHECK-GI-LABEL: test_vmlsl_high_n_s16:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: dup v2.4h, w0
; CHECK-GI-NEXT: smlsl v0.4s, v1.4h, v2.4h
; CHECK-GI-NEXT: ret
@@ -543,7 +543,7 @@ define <4 x i32> @test_vmlsl_high_n_s16_imm(<4 x i32> %a, <8 x i16> %b) #0 {
; CHECK-GI-LABEL: test_vmlsl_high_n_s16_imm:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: movi v2.4h, #29
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: smlsl v0.4s, v1.4h, v2.4h
; CHECK-GI-NEXT: ret
entry:
@@ -562,7 +562,7 @@ define <2 x i64> @test_vmlsl_high_n_s32(<2 x i64> %a, <4 x i32> %b, i32 %c) #0 {
;
; CHECK-GI-LABEL: test_vmlsl_high_n_s32:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: dup v2.2s, w0
; CHECK-GI-NEXT: smlsl v0.2d, v1.2s, v2.2s
; CHECK-GI-NEXT: ret
@@ -585,7 +585,7 @@ define <2 x i64> @test_vmlsl_high_n_s32_imm(<2 x i64> %a, <4 x i32> %b) #0 {
; CHECK-GI-LABEL: test_vmlsl_high_n_s32_imm:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: movi v2.2s, #29
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: smlsl v0.2d, v1.2s, v2.2s
; CHECK-GI-NEXT: ret
entry:
@@ -604,7 +604,7 @@ define <4 x i32> @test_vmlsl_high_n_u16(<4 x i32> %a, <8 x i16> %b, i16 %c) #0 {
;
; CHECK-GI-LABEL: test_vmlsl_high_n_u16:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: dup v2.4h, w0
; CHECK-GI-NEXT: umlsl v0.4s, v1.4h, v2.4h
; CHECK-GI-NEXT: ret
@@ -629,7 +629,7 @@ define <4 x i32> @test_vmlsl_high_n_u16_imm(<4 x i32> %a, <8 x i16> %b) #0 {
; CHECK-GI-LABEL: test_vmlsl_high_n_u16_imm:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: movi v2.4h, #29
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: umlsl v0.4s, v1.4h, v2.4h
; CHECK-GI-NEXT: ret
entry:
@@ -648,7 +648,7 @@ define <2 x i64> @test_vmlsl_high_n_u32(<2 x i64> %a, <4 x i32> %b, i32 %c) #0 {
;
; CHECK-GI-LABEL: test_vmlsl_high_n_u32:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: dup v2.2s, w0
; CHECK-GI-NEXT: umlsl v0.2d, v1.2s, v2.2s
; CHECK-GI-NEXT: ret
@@ -671,7 +671,7 @@ define <2 x i64> @test_vmlsl_high_n_u32_imm(<2 x i64> %a, <4 x i32> %b) #0 {
; CHECK-GI-LABEL: test_vmlsl_high_n_u32_imm:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: movi v2.2s, #29
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: umlsl v0.2d, v1.2s, v2.2s
; CHECK-GI-NEXT: ret
entry:
@@ -690,7 +690,7 @@ define <4 x i32> @test_vqdmlsl_high_n_s16(<4 x i32> %a, <8 x i16> %b, i16 %c) #0
;
; CHECK-GI-LABEL: test_vqdmlsl_high_n_s16:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: dup v2.4h, w0
; CHECK-GI-NEXT: sqdmlsl v0.4s, v1.4h, v2.4h
; CHECK-GI-NEXT: ret
@@ -715,7 +715,7 @@ define <4 x i32> @test_vqdmlsl_high_n_s16_imm(<4 x i32> %a, <8 x i16> %b) #0 {
; CHECK-GI-LABEL: test_vqdmlsl_high_n_s16_imm:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: movi v2.4h, #29
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: sqdmlsl v0.4s, v1.4h, v2.4h
; CHECK-GI-NEXT: ret
entry:
@@ -734,7 +734,7 @@ define <2 x i64> @test_vqdmlsl_high_n_s32(<2 x i64> %a, <4 x i32> %b, i32 %c) #0
;
; CHECK-GI-LABEL: test_vqdmlsl_high_n_s32:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: dup v2.2s, w0
; CHECK-GI-NEXT: sqdmlsl v0.2d, v1.2s, v2.2s
; CHECK-GI-NEXT: ret
@@ -757,7 +757,7 @@ define <2 x i64> @test_vqdmlsl_high_n_s32_imm(<2 x i64> %a, <4 x i32> %b) #0 {
; CHECK-GI-LABEL: test_vqdmlsl_high_n_s32_imm:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: movi v2.2s, #29
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: sqdmlsl v0.2d, v1.2s, v2.2s
; CHECK-GI-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-2velem.ll b/llvm/test/CodeGen/AArch64/arm64-neon-2velem.ll
index 85d8b7c3e2866..49ab7ae56d106 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-2velem.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-2velem.ll
@@ -812,7 +812,7 @@ define <4 x i32> @test_vmlal_high_lane_s16(<4 x i32> %a, <8 x i16> %b, <4 x i16>
;
; CHECK-GI-LABEL: test_vmlal_high_lane_s16:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2
; CHECK-GI-NEXT: smlal v0.4s, v1.4h, v2.h[3]
; CHECK-GI-NEXT: ret
@@ -833,7 +833,7 @@ define <2 x i64> @test_vmlal_high_lane_s32(<2 x i64> %a, <4 x i32> %b, <2 x i32>
;
; CHECK-GI-LABEL: test_vmlal_high_lane_s32:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2
; CHECK-GI-NEXT: smlal v0.2d, v1.2s, v2.s[1]
; CHECK-GI-NEXT: ret
@@ -853,7 +853,7 @@ define <4 x i32> @test_vmlal_high_laneq_s16(<4 x i32> %a, <8 x i16> %b, <8 x i16
;
; CHECK-GI-LABEL: test_vmlal_high_laneq_s16:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: smlal v0.4s, v1.4h, v2.h[7]
; CHECK-GI-NEXT: ret
entry:
@@ -872,7 +872,7 @@ define <2 x i64> @test_vmlal_high_laneq_s32(<2 x i64> %a, <4 x i32> %b, <4 x i32
;
; CHECK-GI-LABEL: test_vmlal_high_laneq_s32:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: smlal v0.2d, v1.2s, v2.s[3]
; CHECK-GI-NEXT: ret
entry:
@@ -942,7 +942,7 @@ define <4 x i32> @test_vmlsl_high_lane_s16(<4 x i32> %a, <8 x i16> %b, <4 x i16>
;
; CHECK-GI-LABEL: test_vmlsl_high_lane_s16:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2
; CHECK-GI-NEXT: smlsl v0.4s, v1.4h, v2.h[3]
; CHECK-GI-NEXT: ret
@@ -963,7 +963,7 @@ define <2 x i64> @test_vmlsl_high_lane_s32(<2 x i64> %a, <4 x i32> %b, <2 x i32>
;
; CHECK-GI-LABEL: test_vmlsl_high_lane_s32:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2
; CHECK-GI-NEXT: smlsl v0.2d, v1.2s, v2.s[1]
; CHECK-GI-NEXT: ret
@@ -983,7 +983,7 @@ define <4 x i32> @test_vmlsl_high_laneq_s16(<4 x i32> %a, <8 x i16> %b, <8 x i16
;
; CHECK-GI-LABEL: test_vmlsl_high_laneq_s16:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: smlsl v0.4s, v1.4h, v2.h[7]
; CHECK-GI-NEXT: ret
entry:
@@ -1002,7 +1002,7 @@ define <2 x i64> @test_vmlsl_high_laneq_s32(<2 x i64> %a, <4 x i32> %b, <4 x i32
;
; CHECK-GI-LABEL: test_vmlsl_high_laneq_s32:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: smlsl v0.2d, v1.2s, v2.s[3]
; CHECK-GI-NEXT: ret
entry:
@@ -1072,7 +1072,7 @@ define <4 x i32> @test_vmlal_high_lane_u16(<4 x i32> %a, <8 x i16> %b, <4 x i16>
;
; CHECK-GI-LABEL: test_vmlal_high_lane_u16:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2
; CHECK-GI-NEXT: umlal v0.4s, v1.4h, v2.h[3]
; CHECK-GI-NEXT: ret
@@ -1093,7 +1093,7 @@ define <2 x i64> @test_vmlal_high_lane_u32(<2 x i64> %a, <4 x i32> %b, <2 x i32>
;
; CHECK-GI-LABEL: test_vmlal_high_lane_u32:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2
; CHECK-GI-NEXT: umlal v0.2d, v1.2s, v2.s[1]
; CHECK-GI-NEXT: ret
@@ -1113,7 +1113,7 @@ define <4 x i32> @test_vmlal_high_laneq_u16(<4 x i32> %a, <8 x i16> %b, <8 x i16
;
; CHECK-GI-LABEL: test_vmlal_high_laneq_u16:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: umlal v0.4s, v1.4h, v2.h[7]
; CHECK-GI-NEXT: ret
entry:
@@ -1132,7 +1132,7 @@ define <2 x i64> @test_vmlal_high_laneq_u32(<2 x i64> %a, <4 x i32> %b, <4 x i32
;
; CHECK-GI-LABEL: test_vmlal_high_laneq_u32:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: umlal v0.2d, v1.2s, v2.s[3]
; CHECK-GI-NEXT: ret
entry:
@@ -1202,7 +1202,7 @@ define <4 x i32> @test_vmlsl_high_lane_u16(<4 x i32> %a, <8 x i16> %b, <4 x i16>
;
; CHECK-GI-LABEL: test_vmlsl_high_lane_u16:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2
; CHECK-GI-NEXT: umlsl v0.4s, v1.4h, v2.h[3]
; CHECK-GI-NEXT: ret
@@ -1223,7 +1223,7 @@ define <2 x i64> @test_vmlsl_high_lane_u32(<2 x i64> %a, <4 x i32> %b, <2 x i32>
;
; CHECK-GI-LABEL: test_vmlsl_high_lane_u32:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2
; CHECK-GI-NEXT: umlsl v0.2d, v1.2s, v2.s[1]
; CHECK-GI-NEXT: ret
@@ -1243,7 +1243,7 @@ define <4 x i32> @test_vmlsl_high_laneq_u16(<4 x i32> %a, <8 x i16> %b, <8 x i16
;
; CHECK-GI-LABEL: test_vmlsl_high_laneq_u16:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: umlsl v0.4s, v1.4h, v2.h[7]
; CHECK-GI-NEXT: ret
entry:
@@ -1262,7 +1262,7 @@ define <2 x i64> @test_vmlsl_high_laneq_u32(<2 x i64> %a, <4 x i32> %b, <4 x i32
;
; CHECK-GI-LABEL: test_vmlsl_high_laneq_u32:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: umlsl v0.2d, v1.2s, v2.s[3]
; CHECK-GI-NEXT: ret
entry:
@@ -1330,7 +1330,7 @@ define <4 x i32> @test_vmull_high_lane_s16(<8 x i16> %a, <4 x i16> %v) {
;
; CHECK-GI-LABEL: test_vmull_high_lane_s16:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-GI-NEXT: smull v0.4s, v0.4h, v1.h[3]
; CHECK-GI-NEXT: ret
@@ -1350,7 +1350,7 @@ define <2 x i64> @test_vmull_high_lane_s32(<4 x i32> %a, <2 x i32> %v) {
;
; CHECK-GI-LABEL: test_vmull_high_lane_s32:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-GI-NEXT: smull v0.2d, v0.2s, v1.s[1]
; CHECK-GI-NEXT: ret
@@ -1370,7 +1370,7 @@ define <4 x i32> @test_vmull_high_lane_u16(<8 x i16> %a, <4 x i16> %v) {
;
; CHECK-GI-LABEL: test_vmull_high_lane_u16:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-GI-NEXT: umull v0.4s, v0.4h, v1.h[3]
; CHECK-GI-NEXT: ret
@@ -1390,7 +1390,7 @@ define <2 x i64> @test_vmull_high_lane_u32(<4 x i32> %a, <2 x i32> %v) {
;
; CHECK-GI-LABEL: test_vmull_high_lane_u32:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-GI-NEXT: umull v0.2d, v0.2s, v1.s[1]
; CHECK-GI-NEXT: ret
@@ -1453,7 +1453,7 @@ define <4 x i32> @test_vmull_high_laneq_s16(<8 x i16> %a, <8 x i16> %v) {
;
; CHECK-GI-LABEL: test_vmull_high_laneq_s16:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: smull v0.4s, v0.4h, v1.h[7]
; CHECK-GI-NEXT: ret
entry:
@@ -1471,7 +1471,7 @@ define <2 x i64> @test_vmull_high_laneq_s32(<4 x i32> %a, <4 x i32> %v) {
;
; CHECK-GI-LABEL: test_vmull_high_laneq_s32:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: smull v0.2d, v0.2s, v1.s[3]
; CHECK-GI-NEXT: ret
entry:
@@ -1489,7 +1489,7 @@ define <4 x i32> @test_vmull_high_laneq_u16(<8 x i16> %a, <8 x i16> %v) {
;
; CHECK-GI-LABEL: test_vmull_high_laneq_u16:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: umull v0.4s, v0.4h, v1.h[7]
; CHECK-GI-NEXT: ret
entry:
@@ -1507,7 +1507,7 @@ define <2 x i64> @test_vmull_high_laneq_u32(<4 x i32> %a, <4 x i32> %v) {
;
; CHECK-GI-LABEL: test_vmull_high_laneq_u32:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: umull v0.2d, v0.2s, v1.s[3]
; CHECK-GI-NEXT: ret
entry:
@@ -1552,7 +1552,7 @@ define <4 x i32> @test_vqdmlal_high_lane_s16(<4 x i32> %a, <8 x i16> %b, <4 x i1
;
; CHECK-GI-LABEL: test_vqdmlal_high_lane_s16:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2
; CHECK-GI-NEXT: sqdmlal v0.4s, v1.4h, v2.h[3]
; CHECK-GI-NEXT: ret
@@ -1573,7 +1573,7 @@ define <2 x i64> @test_vqdmlal_high_lane_s32(<2 x i64> %a, <4 x i32> %b, <2 x i3
;
; CHECK-GI-LABEL: test_vqdmlal_high_lane_s32:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2
; CHECK-GI-NEXT: sqdmlal v0.2d, v1.2s, v2.s[1]
; CHECK-GI-NEXT: ret
@@ -1620,7 +1620,7 @@ define <4 x i32> @test_vqdmlsl_high_lane_s16(<4 x i32> %a, <8 x i16> %b, <4 x i1
;
; CHECK-GI-LABEL: test_vqdmlsl_high_lane_s16:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2
; CHECK-GI-NEXT: sqdmlsl v0.4s, v1.4h, v2.h[3]
; CHECK-GI-NEXT: ret
@@ -1641,7 +1641,7 @@ define <2 x i64> @test_vqdmlsl_high_lane_s32(<2 x i64> %a, <4 x i32> %b, <2 x i3
;
; CHECK-GI-LABEL: test_vqdmlsl_high_lane_s32:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2
; CHECK-GI-NEXT: sqdmlsl v0.2d, v1.2s, v2.s[1]
; CHECK-GI-NEXT: ret
@@ -1708,7 +1708,7 @@ define <4 x i32> @test_vqdmull_high_lane_s16(<8 x i16> %a, <4 x i16> %v) {
;
; CHECK-GI-LABEL: test_vqdmull_high_lane_s16:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-GI-NEXT: sqdmull v0.4s, v0.4h, v1.h[3]
; CHECK-GI-NEXT: ret
@@ -1728,7 +1728,7 @@ define <2 x i64> @test_vqdmull_high_lane_s32(<4 x i32> %a, <2 x i32> %v) {
;
; CHECK-GI-LABEL: test_vqdmull_high_lane_s32:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-GI-NEXT: sqdmull v0.2d, v0.2s, v1.s[1]
; CHECK-GI-NEXT: ret
@@ -1747,7 +1747,7 @@ define <4 x i32> @test_vqdmull_high_laneq_s16(<8 x i16> %a, <8 x i16> %v) {
;
; CHECK-GI-LABEL: test_vqdmull_high_laneq_s16:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: sqdmull v0.4s, v0.4h, v1.h[7]
; CHECK-GI-NEXT: ret
entry:
@@ -1765,7 +1765,7 @@ define <2 x i64> @test_vqdmull_high_laneq_s32(<4 x i32> %a, <4 x i32> %v) {
;
; CHECK-GI-LABEL: test_vqdmull_high_laneq_s32:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: sqdmull v0.2d, v0.2s, v1.s[3]
; CHECK-GI-NEXT: ret
entry:
@@ -2268,7 +2268,7 @@ define <4 x i16> @test_vadd_lane5_i16_bitcast_bigger_aligned(<4 x i16> %a, <16 x
;
; CHECK-GI-LABEL: test_vadd_lane5_i16_bitcast_bigger_aligned:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: dup v1.4h, v1.h[1]
; CHECK-GI-NEXT: add v0.4h, v1.4h, v0.4h
; CHECK-GI-NEXT: ret
@@ -3002,7 +3002,7 @@ define <4 x i32> @test_vmlal_high_lane_s16_0(<4 x i32> %a, <8 x i16> %b, <4 x i1
;
; CHECK-GI-LABEL: test_vmlal_high_lane_s16_0:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2
; CHECK-GI-NEXT: smlal v0.4s, v1.4h, v2.h[0]
; CHECK-GI-NEXT: ret
@@ -3023,7 +3023,7 @@ define <2 x i64> @test_vmlal_high_lane_s32_0(<2 x i64> %a, <4 x i32> %b, <2 x i3
;
; CHECK-GI-LABEL: test_vmlal_high_lane_s32_0:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2
; CHECK-GI-NEXT: smlal v0.2d, v1.2s, v2.s[0]
; CHECK-GI-NEXT: ret
@@ -3043,7 +3043,7 @@ define <4 x i32> @test_vmlal_high_laneq_s16_0(<4 x i32> %a, <8 x i16> %b, <8 x i
;
; CHECK-GI-LABEL: test_vmlal_high_laneq_s16_0:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: smlal v0.4s, v1.4h, v2.h[0]
; CHECK-GI-NEXT: ret
entry:
@@ -3062,7 +3062,7 @@ define <2 x i64> @test_vmlal_high_laneq_s32_0(<2 x i64> %a, <4 x i32> %b, <4 x i
;
; CHECK-GI-LABEL: test_vmlal_high_laneq_s32_0:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: smlal v0.2d, v1.2s, v2.s[0]
; CHECK-GI-NEXT: ret
entry:
@@ -3132,7 +3132,7 @@ define <4 x i32> @test_vmlsl_high_lane_s16_0(<4 x i32> %a, <8 x i16> %b, <4 x i1
;
; CHECK-GI-LABEL: test_vmlsl_high_lane_s16_0:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2
; CHECK-GI-NEXT: smlsl v0.4s, v1.4h, v2.h[0]
; CHECK-GI-NEXT: ret
@@ -3153,7 +3153,7 @@ define <2 x i64> @test_vmlsl_high_lane_s32_0(<2 x i64> %a, <4 x i32> %b, <2 x i3
;
; CHECK-GI-LABEL: test_vmlsl_high_lane_s32_0:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2
; CHECK-GI-NEXT: smlsl v0.2d, v1.2s, v2.s[0]
; CHECK-GI-NEXT: ret
@@ -3173,7 +3173,7 @@ define <4 x i32> @test_vmlsl_high_laneq_s16_0(<4 x i32> %a, <8 x i16> %b, <8 x i
;
; CHECK-GI-LABEL: test_vmlsl_high_laneq_s16_0:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: smlsl v0.4s, v1.4h, v2.h[0]
; CHECK-GI-NEXT: ret
entry:
@@ -3192,7 +3192,7 @@ define <2 x i64> @test_vmlsl_high_laneq_s32_0(<2 x i64> %a, <4 x i32> %b, <4 x i
;
; CHECK-GI-LABEL: test_vmlsl_high_laneq_s32_0:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: smlsl v0.2d, v1.2s, v2.s[0]
; CHECK-GI-NEXT: ret
entry:
@@ -3262,7 +3262,7 @@ define <4 x i32> @test_vmlal_high_lane_u16_0(<4 x i32> %a, <8 x i16> %b, <4 x i1
;
; CHECK-GI-LABEL: test_vmlal_high_lane_u16_0:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2
; CHECK-GI-NEXT: umlal v0.4s, v1.4h, v2.h[0]
; CHECK-GI-NEXT: ret
@@ -3283,7 +3283,7 @@ define <2 x i64> @test_vmlal_high_lane_u32_0(<2 x i64> %a, <4 x i32> %b, <2 x i3
;
; CHECK-GI-LABEL: test_vmlal_high_lane_u32_0:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2
; CHECK-GI-NEXT: umlal v0.2d, v1.2s, v2.s[0]
; CHECK-GI-NEXT: ret
@@ -3303,7 +3303,7 @@ define <4 x i32> @test_vmlal_high_laneq_u16_0(<4 x i32> %a, <8 x i16> %b, <8 x i
;
; CHECK-GI-LABEL: test_vmlal_high_laneq_u16_0:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: umlal v0.4s, v1.4h, v2.h[0]
; CHECK-GI-NEXT: ret
entry:
@@ -3322,7 +3322,7 @@ define <2 x i64> @test_vmlal_high_laneq_u32_0(<2 x i64> %a, <4 x i32> %b, <4 x i
;
; CHECK-GI-LABEL: test_vmlal_high_laneq_u32_0:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: umlal v0.2d, v1.2s, v2.s[0]
; CHECK-GI-NEXT: ret
entry:
@@ -3392,7 +3392,7 @@ define <4 x i32> @test_vmlsl_high_lane_u16_0(<4 x i32> %a, <8 x i16> %b, <4 x i1
;
; CHECK-GI-LABEL: test_vmlsl_high_lane_u16_0:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2
; CHECK-GI-NEXT: umlsl v0.4s, v1.4h, v2.h[0]
; CHECK-GI-NEXT: ret
@@ -3413,7 +3413,7 @@ define <2 x i64> @test_vmlsl_high_lane_u32_0(<2 x i64> %a, <4 x i32> %b, <2 x i3
;
; CHECK-GI-LABEL: test_vmlsl_high_lane_u32_0:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2
; CHECK-GI-NEXT: umlsl v0.2d, v1.2s, v2.s[0]
; CHECK-GI-NEXT: ret
@@ -3433,7 +3433,7 @@ define <4 x i32> @test_vmlsl_high_laneq_u16_0(<4 x i32> %a, <8 x i16> %b, <8 x i
;
; CHECK-GI-LABEL: test_vmlsl_high_laneq_u16_0:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: umlsl v0.4s, v1.4h, v2.h[0]
; CHECK-GI-NEXT: ret
entry:
@@ -3452,7 +3452,7 @@ define <2 x i64> @test_vmlsl_high_laneq_u32_0(<2 x i64> %a, <4 x i32> %b, <4 x i
;
; CHECK-GI-LABEL: test_vmlsl_high_laneq_u32_0:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: umlsl v0.2d, v1.2s, v2.s[0]
; CHECK-GI-NEXT: ret
entry:
@@ -3520,7 +3520,7 @@ define <4 x i32> @test_vmull_high_lane_s16_0(<8 x i16> %a, <4 x i16> %v) {
;
; CHECK-GI-LABEL: test_vmull_high_lane_s16_0:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-GI-NEXT: smull v0.4s, v0.4h, v1.h[0]
; CHECK-GI-NEXT: ret
@@ -3540,7 +3540,7 @@ define <2 x i64> @test_vmull_high_lane_s32_0(<4 x i32> %a, <2 x i32> %v) {
;
; CHECK-GI-LABEL: test_vmull_high_lane_s32_0:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-GI-NEXT: smull v0.2d, v0.2s, v1.s[0]
; CHECK-GI-NEXT: ret
@@ -3560,7 +3560,7 @@ define <4 x i32> @test_vmull_high_lane_u16_0(<8 x i16> %a, <4 x i16> %v) {
;
; CHECK-GI-LABEL: test_vmull_high_lane_u16_0:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-GI-NEXT: umull v0.4s, v0.4h, v1.h[0]
; CHECK-GI-NEXT: ret
@@ -3580,7 +3580,7 @@ define <2 x i64> @test_vmull_high_lane_u32_0(<4 x i32> %a, <2 x i32> %v) {
;
; CHECK-GI-LABEL: test_vmull_high_lane_u32_0:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-GI-NEXT: umull v0.2d, v0.2s, v1.s[0]
; CHECK-GI-NEXT: ret
@@ -3643,7 +3643,7 @@ define <4 x i32> @test_vmull_high_laneq_s16_0(<8 x i16> %a, <8 x i16> %v) {
;
; CHECK-GI-LABEL: test_vmull_high_laneq_s16_0:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: smull v0.4s, v0.4h, v1.h[0]
; CHECK-GI-NEXT: ret
entry:
@@ -3661,7 +3661,7 @@ define <2 x i64> @test_vmull_high_laneq_s32_0(<4 x i32> %a, <4 x i32> %v) {
;
; CHECK-GI-LABEL: test_vmull_high_laneq_s32_0:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: smull v0.2d, v0.2s, v1.s[0]
; CHECK-GI-NEXT: ret
entry:
@@ -3679,7 +3679,7 @@ define <4 x i32> @test_vmull_high_laneq_u16_0(<8 x i16> %a, <8 x i16> %v) {
;
; CHECK-GI-LABEL: test_vmull_high_laneq_u16_0:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: umull v0.4s, v0.4h, v1.h[0]
; CHECK-GI-NEXT: ret
entry:
@@ -3697,7 +3697,7 @@ define <2 x i64> @test_vmull_high_laneq_u32_0(<4 x i32> %a, <4 x i32> %v) {
;
; CHECK-GI-LABEL: test_vmull_high_laneq_u32_0:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: umull v0.2d, v0.2s, v1.s[0]
; CHECK-GI-NEXT: ret
entry:
@@ -3742,7 +3742,7 @@ define <4 x i32> @test_vqdmlal_high_lane_s16_0(<4 x i32> %a, <8 x i16> %b, <4 x
;
; CHECK-GI-LABEL: test_vqdmlal_high_lane_s16_0:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2
; CHECK-GI-NEXT: sqdmlal v0.4s, v1.4h, v2.h[0]
; CHECK-GI-NEXT: ret
@@ -3763,7 +3763,7 @@ define <2 x i64> @test_vqdmlal_high_lane_s32_0(<2 x i64> %a, <4 x i32> %b, <2 x
;
; CHECK-GI-LABEL: test_vqdmlal_high_lane_s32_0:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2
; CHECK-GI-NEXT: sqdmlal v0.2d, v1.2s, v2.s[0]
; CHECK-GI-NEXT: ret
@@ -3810,7 +3810,7 @@ define <4 x i32> @test_vqdmlsl_high_lane_s16_0(<4 x i32> %a, <8 x i16> %b, <4 x
;
; CHECK-GI-LABEL: test_vqdmlsl_high_lane_s16_0:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2
; CHECK-GI-NEXT: sqdmlsl v0.4s, v1.4h, v2.h[0]
; CHECK-GI-NEXT: ret
@@ -3831,7 +3831,7 @@ define <2 x i64> @test_vqdmlsl_high_lane_s32_0(<2 x i64> %a, <4 x i32> %b, <2 x
;
; CHECK-GI-LABEL: test_vqdmlsl_high_lane_s32_0:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2
; CHECK-GI-NEXT: sqdmlsl v0.2d, v1.2s, v2.s[0]
; CHECK-GI-NEXT: ret
@@ -3898,7 +3898,7 @@ define <4 x i32> @test_vqdmull_high_lane_s16_0(<8 x i16> %a, <4 x i16> %v) {
;
; CHECK-GI-LABEL: test_vqdmull_high_lane_s16_0:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-GI-NEXT: sqdmull v0.4s, v0.4h, v1.h[0]
; CHECK-GI-NEXT: ret
@@ -3918,7 +3918,7 @@ define <2 x i64> @test_vqdmull_high_lane_s32_0(<4 x i32> %a, <2 x i32> %v) {
;
; CHECK-GI-LABEL: test_vqdmull_high_lane_s32_0:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-GI-NEXT: sqdmull v0.2d, v0.2s, v1.s[0]
; CHECK-GI-NEXT: ret
@@ -3937,7 +3937,7 @@ define <4 x i32> @test_vqdmull_high_laneq_s16_0(<8 x i16> %a, <8 x i16> %v) {
;
; CHECK-GI-LABEL: test_vqdmull_high_laneq_s16_0:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: sqdmull v0.4s, v0.4h, v1.h[0]
; CHECK-GI-NEXT: ret
entry:
@@ -3955,7 +3955,7 @@ define <2 x i64> @test_vqdmull_high_laneq_s32_0(<4 x i32> %a, <4 x i32> %v) {
;
; CHECK-GI-LABEL: test_vqdmull_high_laneq_s32_0:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: sqdmull v0.2d, v0.2s, v1.s[0]
; CHECK-GI-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-3v
diff .ll b/llvm/test/CodeGen/AArch64/arm64-neon-3v
diff .ll
index 79822682c2178..9aec2f1925b79 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-3v
diff .ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-3v
diff .ll
@@ -2768,7 +2768,7 @@ define <8 x i16> @cmplx_mul_combined_re_im(<8 x i16> noundef %a, i64 %scale.coer
; CHECK-GI-NEXT: dup v2.8h, v1.h[0]
; CHECK-GI-NEXT: sqneg v1.8h, v2.8h
; CHECK-GI-NEXT: tbl v1.16b, { v1.16b, v2.16b }, v3.16b
-; CHECK-GI-NEXT: mov d2, v0.d[1]
+; CHECK-GI-NEXT: ext v2.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: fmov d3, x0
; CHECK-GI-NEXT: sqdmull v2.4s, v2.4h, v3.h[0]
; CHECK-GI-NEXT: sqdmull v5.4s, v4.4h, v1.4h
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-add-pairwise.ll b/llvm/test/CodeGen/AArch64/arm64-neon-add-pairwise.ll
index 0ede4bc7a4d6c..aba73cf745c22 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-add-pairwise.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-add-pairwise.ll
@@ -137,7 +137,7 @@ define i32 @addp_v4i32(<4 x i32> %a, <4 x i32> %b) {
; CHECK-GI-LABEL: addp_v4i32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: add v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: addp v0.2s, v0.2s, v1.2s
; CHECK-GI-NEXT: dup v1.2s, v0.s[1]
; CHECK-GI-NEXT: add v0.2s, v0.2s, v1.2s
@@ -164,7 +164,7 @@ define <4 x i16> @addp_v8i16(<8 x i16> %a, <8 x i16> %b) {
; CHECK-GI-LABEL: addp_v8i16:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: add v0.8h, v0.8h, v1.8h
-; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: addp v0.4h, v0.4h, v1.4h
; CHECK-GI-NEXT: ret
%1 = add <8 x i16> %a, %b
@@ -185,7 +185,7 @@ define <8 x i8> @addp_v16i8(<16 x i8> %a, <16 x i8> %b) {
; CHECK-GI-LABEL: addp_v16i8:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: add v0.16b, v0.16b, v1.16b
-; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: addp v0.8b, v0.8b, v1.8b
; CHECK-GI-NEXT: ret
%1 = add <16 x i8> %a, %b
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-mul-div.ll b/llvm/test/CodeGen/AArch64/arm64-neon-mul-div.ll
index cd101afe57c40..dcd34af7c93cb 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-mul-div.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-mul-div.ll
@@ -2014,7 +2014,7 @@ define <8 x i8> @urem8x8(<8 x i8> %A, <8 x i8> %B) {
; CHECK-GI-NEXT: ushll v0.4s, v2.4h, #0
; CHECK-GI-NEXT: ushll v3.4s, v1.4h, #0
; CHECK-GI-NEXT: ushll2 v2.4s, v2.8h, #0
-; CHECK-GI-NEXT: mov d5, v1.d[1]
+; CHECK-GI-NEXT: ext v5.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: fmov w8, s0
; CHECK-GI-NEXT: fmov w9, s3
; CHECK-GI-NEXT: mov w10, v0.s[1]
@@ -2173,8 +2173,8 @@ define <16 x i8> @urem16x8(<16 x i8> %A, <16 x i8> %B) {
; CHECK-GI-NEXT: ushll v5.4s, v3.4h, #0
; CHECK-GI-NEXT: ushll2 v4.4s, v4.8h, #0
; CHECK-GI-NEXT: ushll v6.4s, v1.4h, #0
-; CHECK-GI-NEXT: mov d18, v3.d[1]
-; CHECK-GI-NEXT: mov d19, v1.d[1]
+; CHECK-GI-NEXT: ext v18.16b, v3.16b, v3.16b, #8
+; CHECK-GI-NEXT: ext v19.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: fmov w8, s2
; CHECK-GI-NEXT: fmov w9, s5
; CHECK-GI-NEXT: mov w12, v2.s[3]
@@ -2390,7 +2390,7 @@ define <8 x i16> @urem8x16(<8 x i16> %A, <8 x i16> %B) {
; CHECK-GI-NEXT: ushll v2.4s, v0.4h, #0
; CHECK-GI-NEXT: ushll v3.4s, v1.4h, #0
; CHECK-GI-NEXT: ushll2 v0.4s, v0.8h, #0
-; CHECK-GI-NEXT: mov d5, v1.d[1]
+; CHECK-GI-NEXT: ext v5.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: fmov w8, s2
; CHECK-GI-NEXT: fmov w9, s3
; CHECK-GI-NEXT: mov w10, v2.s[1]
diff --git a/llvm/test/CodeGen/AArch64/arm64-vabs.ll b/llvm/test/CodeGen/AArch64/arm64-vabs.ll
index d175247cca3d9..0a03c81f9ecd8 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vabs.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vabs.ll
@@ -1663,7 +1663,7 @@ define <2 x i64> @uabdl2_from_extract_dup(<4 x i32> %lhs, i32 %rhs) {
; CHECK-GI-LABEL: uabdl2_from_extract_dup:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: dup.2s v1, w0
-; CHECK-GI-NEXT: mov d0, v0[1]
+; CHECK-GI-NEXT: ext.16b v0, v0, v0, #8
; CHECK-GI-NEXT: uabdl.2d v0, v0, v1
; CHECK-GI-NEXT: ret
%rhsvec.tmp = insertelement <2 x i32> undef, i32 %rhs, i32 0
@@ -1698,7 +1698,7 @@ define <2 x i64> @sabdl2_from_extract_dup(<4 x i32> %lhs, i32 %rhs) {
; CHECK-GI-LABEL: sabdl2_from_extract_dup:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: dup.2s v1, w0
-; CHECK-GI-NEXT: mov d0, v0[1]
+; CHECK-GI-NEXT: ext.16b v0, v0, v0, #8
; CHECK-GI-NEXT: sabdl.2d v0, v0, v1
; CHECK-GI-NEXT: ret
%rhsvec.tmp = insertelement <2 x i32> undef, i32 %rhs, i32 0
@@ -2033,7 +2033,7 @@ define <16 x i16> @uabd16b_i16_const_select(<16 x i8> %a) {
; CHECK-GI-LABEL: uabd16b_i16_const_select:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: adrp x8, .LCPI106_1
-; CHECK-GI-NEXT: mov d3, v0[1]
+; CHECK-GI-NEXT: ext.16b v3, v0, v0, #8
; CHECK-GI-NEXT: ushll.8h v4, v0, #0
; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI106_1]
; CHECK-GI-NEXT: adrp x8, .LCPI106_0
@@ -2075,7 +2075,7 @@ define <16 x i16> @sabd16b_i16_const_select(<16 x i8> %a) {
; CHECK-GI-LABEL: sabd16b_i16_const_select:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: adrp x8, .LCPI107_1
-; CHECK-GI-NEXT: mov d3, v0[1]
+; CHECK-GI-NEXT: ext.16b v3, v0, v0, #8
; CHECK-GI-NEXT: sshll.8h v4, v0, #0
; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI107_1]
; CHECK-GI-NEXT: adrp x8, .LCPI107_0
diff --git a/llvm/test/CodeGen/AArch64/arm64-vadd.ll b/llvm/test/CodeGen/AArch64/arm64-vadd.ll
index 3cf01150712c9..9a2f7768dded5 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vadd.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vadd.ll
@@ -1041,7 +1041,7 @@ define <2 x i64> @usubl2_duprhs(<4 x i32> %lhs, i32 %rhs) {
; CHECK-GI-LABEL: usubl2_duprhs:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: dup v1.2s, w0
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: usubl v0.2d, v0.2s, v1.2s
; CHECK-GI-NEXT: ret
%rhsvec.tmp = insertelement <2 x i32> undef, i32 %rhs, i32 0
diff --git a/llvm/test/CodeGen/AArch64/arm64-vhadd.ll b/llvm/test/CodeGen/AArch64/arm64-vhadd.ll
index 8de97b01d5ae4..565d0af8ab831 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vhadd.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vhadd.ll
@@ -1202,8 +1202,7 @@ define <2 x i16> @hadd8x2_sext_asr(<2 x i8> %src1, <2 x i8> %src2) {
; CHECK-GI-NEXT: ssra.2s v1, v0, #24
; CHECK-GI-NEXT: uzp1.4h v0, v1, v0
; CHECK-GI-NEXT: sshr.4h v0, v0, #1
-; CHECK-GI-NEXT: ushll.4s v0, v0, #0
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: zip1.4h v0, v0, v0
; CHECK-GI-NEXT: ret
%zextsrc1 = sext <2 x i8> %src1 to <2 x i16>
%zextsrc2 = sext <2 x i8> %src2 to <2 x i16>
@@ -1229,8 +1228,7 @@ define <2 x i16> @hadd8x2_zext_asr(<2 x i8> %src1, <2 x i8> %src2) {
; CHECK-GI-NEXT: add.2s v0, v0, v1
; CHECK-GI-NEXT: uzp1.4h v0, v0, v0
; CHECK-GI-NEXT: ushr.4h v0, v0, #1
-; CHECK-GI-NEXT: ushll.4s v0, v0, #0
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: zip1.4h v0, v0, v0
; CHECK-GI-NEXT: ret
%zextsrc1 = zext <2 x i8> %src1 to <2 x i16>
%zextsrc2 = zext <2 x i8> %src2 to <2 x i16>
@@ -1259,8 +1257,7 @@ define <2 x i16> @hadd8x2_sext_lsr(<2 x i8> %src1, <2 x i8> %src2) {
; CHECK-GI-NEXT: ssra.2s v1, v0, #24
; CHECK-GI-NEXT: uzp1.4h v0, v1, v0
; CHECK-GI-NEXT: ushr.4h v0, v0, #1
-; CHECK-GI-NEXT: ushll.4s v0, v0, #0
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: zip1.4h v0, v0, v0
; CHECK-GI-NEXT: ret
%zextsrc1 = sext <2 x i8> %src1 to <2 x i16>
%zextsrc2 = sext <2 x i8> %src2 to <2 x i16>
@@ -1286,8 +1283,7 @@ define <2 x i16> @hadd8x2_zext_lsr(<2 x i8> %src1, <2 x i8> %src2) {
; CHECK-GI-NEXT: add.2s v0, v0, v1
; CHECK-GI-NEXT: uzp1.4h v0, v0, v0
; CHECK-GI-NEXT: ushr.4h v0, v0, #1
-; CHECK-GI-NEXT: ushll.4s v0, v0, #0
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: zip1.4h v0, v0, v0
; CHECK-GI-NEXT: ret
%zextsrc1 = zext <2 x i8> %src1 to <2 x i16>
%zextsrc2 = zext <2 x i8> %src2 to <2 x i16>
@@ -1426,8 +1422,7 @@ define <2 x i16> @rhadd8x2_sext_asr(<2 x i8> %src1, <2 x i8> %src2) {
; CHECK-GI-NEXT: add.2s v0, v1, v2
; CHECK-GI-NEXT: uzp1.4h v0, v0, v0
; CHECK-GI-NEXT: sshr.4h v0, v0, #1
-; CHECK-GI-NEXT: ushll.4s v0, v0, #0
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: zip1.4h v0, v0, v0
; CHECK-GI-NEXT: ret
%zextsrc1 = sext <2 x i8> %src1 to <2 x i16>
%zextsrc2 = sext <2 x i8> %src2 to <2 x i16>
@@ -1456,8 +1451,7 @@ define <2 x i16> @rhadd8x2_zext_asr(<2 x i8> %src1, <2 x i8> %src2) {
; CHECK-GI-NEXT: add.2s v0, v0, v2
; CHECK-GI-NEXT: uzp1.4h v0, v0, v0
; CHECK-GI-NEXT: ushr.4h v0, v0, #1
-; CHECK-GI-NEXT: ushll.4s v0, v0, #0
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: zip1.4h v0, v0, v0
; CHECK-GI-NEXT: ret
%zextsrc1 = zext <2 x i8> %src1 to <2 x i16>
%zextsrc2 = zext <2 x i8> %src2 to <2 x i16>
@@ -1491,8 +1485,7 @@ define <2 x i16> @rhadd8x2_sext_lsr(<2 x i8> %src1, <2 x i8> %src2) {
; CHECK-GI-NEXT: add.2s v0, v1, v2
; CHECK-GI-NEXT: uzp1.4h v0, v0, v0
; CHECK-GI-NEXT: ushr.4h v0, v0, #1
-; CHECK-GI-NEXT: ushll.4s v0, v0, #0
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: zip1.4h v0, v0, v0
; CHECK-GI-NEXT: ret
%zextsrc1 = sext <2 x i8> %src1 to <2 x i16>
%zextsrc2 = sext <2 x i8> %src2 to <2 x i16>
@@ -1521,8 +1514,7 @@ define <2 x i16> @rhadd8x2_zext_lsr(<2 x i8> %src1, <2 x i8> %src2) {
; CHECK-GI-NEXT: add.2s v0, v0, v2
; CHECK-GI-NEXT: uzp1.4h v0, v0, v0
; CHECK-GI-NEXT: ushr.4h v0, v0, #1
-; CHECK-GI-NEXT: ushll.4s v0, v0, #0
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: zip1.4h v0, v0, v0
; CHECK-GI-NEXT: ret
%zextsrc1 = zext <2 x i8> %src1 to <2 x i16>
%zextsrc2 = zext <2 x i8> %src2 to <2 x i16>
diff --git a/llvm/test/CodeGen/AArch64/arm64-vmul.ll b/llvm/test/CodeGen/AArch64/arm64-vmul.ll
index fbf6df2b1fda4..611079ef6ad89 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vmul.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vmul.ll
@@ -1542,7 +1542,7 @@ define <4 x i32> @sqdmull2_lane_4s(<8 x i16> %A, <8 x i16> %B) nounwind {
;
; CHECK-GI-LABEL: sqdmull2_lane_4s:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: sqdmull v0.4s, v0.4h, v1.h[1]
; CHECK-GI-NEXT: ret
%tmp1 = shufflevector <8 x i16> %A, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -1559,7 +1559,7 @@ define <2 x i64> @sqdmull2_lane_2d(<4 x i32> %A, <4 x i32> %B) nounwind {
;
; CHECK-GI-LABEL: sqdmull2_lane_2d:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: sqdmull v0.2d, v0.2s, v1.s[1]
; CHECK-GI-NEXT: ret
%tmp1 = shufflevector <4 x i32> %A, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
@@ -1673,7 +1673,7 @@ define <4 x i32> @sqdmlal2_lane_4s(<8 x i16> %A, <8 x i16> %B, <4 x i32> %C) nou
;
; CHECK-GI-LABEL: sqdmlal2_lane_4s:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d3, v0.d[1]
+; CHECK-GI-NEXT: ext v3.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: mov v0.16b, v2.16b
; CHECK-GI-NEXT: sqdmlal v0.4s, v3.4h, v1.h[1]
; CHECK-GI-NEXT: ret
@@ -1693,7 +1693,7 @@ define <2 x i64> @sqdmlal2_lane_2d(<4 x i32> %A, <4 x i32> %B, <2 x i64> %C) nou
;
; CHECK-GI-LABEL: sqdmlal2_lane_2d:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d3, v0.d[1]
+; CHECK-GI-NEXT: ext v3.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: mov v0.16b, v2.16b
; CHECK-GI-NEXT: sqdmlal v0.2d, v3.2s, v1.s[1]
; CHECK-GI-NEXT: ret
@@ -1978,7 +1978,7 @@ define <4 x i32> @sqdmlsl2_lane_4s(<8 x i16> %A, <8 x i16> %B, <4 x i32> %C) nou
;
; CHECK-GI-LABEL: sqdmlsl2_lane_4s:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d3, v0.d[1]
+; CHECK-GI-NEXT: ext v3.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: mov v0.16b, v2.16b
; CHECK-GI-NEXT: sqdmlsl v0.4s, v3.4h, v1.h[1]
; CHECK-GI-NEXT: ret
@@ -1998,7 +1998,7 @@ define <2 x i64> @sqdmlsl2_lane_2d(<4 x i32> %A, <4 x i32> %B, <2 x i64> %C) nou
;
; CHECK-GI-LABEL: sqdmlsl2_lane_2d:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d3, v0.d[1]
+; CHECK-GI-NEXT: ext v3.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: mov v0.16b, v2.16b
; CHECK-GI-NEXT: sqdmlsl v0.2d, v3.2s, v1.s[1]
; CHECK-GI-NEXT: ret
@@ -2908,7 +2908,7 @@ define <2 x i64> @mull_from_extract_dup_high(<4 x i32> %lhs, i32 %rhs) {
; CHECK-GI-LABEL: mull_from_extract_dup_high:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: dup v1.2s, w0
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: sqdmull v0.2d, v0.2s, v1.2s
; CHECK-GI-NEXT: ret
%rhsvec.tmp = insertelement <2 x i32> undef, i32 %rhs, i32 0
@@ -2945,7 +2945,7 @@ define <8 x i16> @pmull_from_extract_dup_high(<16 x i8> %lhs, i8 %rhs) {
; CHECK-GI-LABEL: pmull_from_extract_dup_high:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: dup v1.8b, w0
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: pmull v0.8h, v0.8b, v1.8b
; CHECK-GI-NEXT: ret
%rhsvec.0 = insertelement <8 x i8> undef, i8 %rhs, i32 0
@@ -2982,7 +2982,7 @@ define <8 x i16> @pmull_from_extract_duplane_high(<16 x i8> %lhs, <8 x i8> %rhs)
; CHECK-GI-LABEL: pmull_from_extract_duplane_high:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: dup v1.8b, v1.b[0]
; CHECK-GI-NEXT: pmull v0.8h, v0.8b, v1.8b
; CHECK-GI-NEXT: ret
@@ -3013,7 +3013,7 @@ define <2 x i64> @sqdmull_from_extract_duplane_high(<4 x i32> %lhs, <4 x i32> %r
;
; CHECK-GI-LABEL: sqdmull_from_extract_duplane_high:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: sqdmull v0.2d, v0.2s, v1.s[0]
; CHECK-GI-NEXT: ret
%lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
@@ -3044,7 +3044,7 @@ define <2 x i64> @sqdmlal_from_extract_duplane_high(<2 x i64> %accum, <4 x i32>
;
; CHECK-GI-LABEL: sqdmlal_from_extract_duplane_high:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: sqdmlal v0.2d, v1.2s, v2.s[0]
; CHECK-GI-NEXT: ret
%lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
@@ -3076,7 +3076,7 @@ define <2 x i64> @umlal_from_extract_duplane_high(<2 x i64> %accum, <4 x i32> %l
;
; CHECK-GI-LABEL: umlal_from_extract_duplane_high:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: umlal v0.2d, v1.2s, v2.s[0]
; CHECK-GI-NEXT: ret
%lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
@@ -3495,7 +3495,7 @@ define <4 x i32> @sqdmlal2_lane_4s_lib(<4 x i32> %dst, <8 x i16> %v1, <8 x i16>
;
; CHECK-GI-LABEL: sqdmlal2_lane_4s_lib:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: sqdmlal v0.4s, v1.4h, v2.h[7]
; CHECK-GI-NEXT: ret
%tmp0 = shufflevector <8 x i16> %v1, <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -3513,7 +3513,7 @@ define <2 x i64> @sqdmlal2_lane_2d_lib(<2 x i64> %dst, <4 x i32> %v1, <4 x i32>
;
; CHECK-GI-LABEL: sqdmlal2_lane_2d_lib:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: sqdmlal v0.2d, v1.2s, v2.s[1]
; CHECK-GI-NEXT: ret
%tmp0 = shufflevector <4 x i32> %v1, <4 x i32> poison, <2 x i32> <i32 2, i32 3>
@@ -3599,7 +3599,7 @@ define <4 x i32> @sqdmlsl2_lane_4s_lib(<4 x i32> %dst, <8 x i16> %v1, <8 x i16>
;
; CHECK-GI-LABEL: sqdmlsl2_lane_4s_lib:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: sqdmlsl v0.4s, v1.4h, v2.h[7]
; CHECK-GI-NEXT: ret
%tmp0 = shufflevector <8 x i16> %v1, <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -3617,7 +3617,7 @@ define <2 x i64> @sqdmlsl2_lane_2d_lib(<2 x i64> %dst, <4 x i32> %v1, <4 x i32>
;
; CHECK-GI-LABEL: sqdmlsl2_lane_2d_lib:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: sqdmlsl v0.2d, v1.2s, v2.s[1]
; CHECK-GI-NEXT: ret
%tmp0 = shufflevector <4 x i32> %v1, <4 x i32> poison, <2 x i32> <i32 2, i32 3>
@@ -3688,7 +3688,7 @@ define <16 x i16> @or_sext_idx_v16i8_i16(<16 x i8> %s0, <16 x i8> %s1, <16 x i16
; CHECK-GI-LABEL: or_sext_idx_v16i8_i16:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: dup v0.8b, v0.b[3]
-; CHECK-GI-NEXT: mov d4, v1.d[1]
+; CHECK-GI-NEXT: ext v4.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: smlal v2.8h, v0.8b, v1.8b
; CHECK-GI-NEXT: smlal v3.8h, v0.8b, v4.8b
; CHECK-GI-NEXT: mov v0.16b, v2.16b
@@ -3716,7 +3716,7 @@ define <16 x i16> @or_zext_idx_v16i8_i16(<16 x i8> %s0, <16 x i8> %s1, <16 x i16
; CHECK-GI-LABEL: or_zext_idx_v16i8_i16:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: dup v0.8b, v0.b[3]
-; CHECK-GI-NEXT: mov d4, v1.d[1]
+; CHECK-GI-NEXT: ext v4.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: umlal v2.8h, v0.8b, v1.8b
; CHECK-GI-NEXT: umlal v3.8h, v0.8b, v4.8b
; CHECK-GI-NEXT: mov v0.16b, v2.16b
@@ -3793,7 +3793,7 @@ define <8 x i32> @or_sext_idx_v8i16_i32(<8 x i16> %s0, <8 x i16> %s1, <8 x i32>
;
; CHECK-GI-LABEL: or_sext_idx_v8i16_i32:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d4, v1.d[1]
+; CHECK-GI-NEXT: ext v4.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: smlal v2.4s, v1.4h, v0.h[3]
; CHECK-GI-NEXT: smlal v3.4s, v4.4h, v0.h[3]
; CHECK-GI-NEXT: mov v0.16b, v2.16b
@@ -3819,7 +3819,7 @@ define <8 x i32> @or_zext_idx_v8i16_i32(<8 x i16> %s0, <8 x i16> %s1, <8 x i32>
;
; CHECK-GI-LABEL: or_zext_idx_v8i16_i32:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d4, v1.d[1]
+; CHECK-GI-NEXT: ext v4.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: umlal v2.4s, v1.4h, v0.h[3]
; CHECK-GI-NEXT: umlal v3.4s, v4.4h, v0.h[3]
; CHECK-GI-NEXT: mov v0.16b, v2.16b
@@ -3893,7 +3893,7 @@ define <4 x i64> @or_sext_idx_v4i32_i64(<4 x i32> %s0, <4 x i32> %s1, <4 x i64>
;
; CHECK-GI-LABEL: or_sext_idx_v4i32_i64:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d4, v1.d[1]
+; CHECK-GI-NEXT: ext v4.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: smlal v2.2d, v1.2s, v0.s[3]
; CHECK-GI-NEXT: smlal v3.2d, v4.2s, v0.s[3]
; CHECK-GI-NEXT: mov v0.16b, v2.16b
@@ -3919,7 +3919,7 @@ define <4 x i64> @or_zext_idx_v4i32_i64(<4 x i32> %s0, <4 x i32> %s1, <4 x i64>
;
; CHECK-GI-LABEL: or_zext_idx_v4i32_i64:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d4, v1.d[1]
+; CHECK-GI-NEXT: ext v4.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: umlal v2.2d, v1.2s, v0.s[3]
; CHECK-GI-NEXT: umlal v3.2d, v4.2s, v0.s[3]
; CHECK-GI-NEXT: mov v0.16b, v2.16b
diff --git a/llvm/test/CodeGen/AArch64/arm64-vshift.ll b/llvm/test/CodeGen/AArch64/arm64-vshift.ll
index 8d17836a2b761..aaf00dbb8dc7a 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vshift.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vshift.ll
@@ -2252,7 +2252,7 @@ define <8 x i16> @ushll2_8h(ptr %A) nounwind {
; CHECK-GI-LABEL: ushll2_8h:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: ldr q0, [x0]
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #1
; CHECK-GI-NEXT: ret
%load1 = load <16 x i8>, ptr %A
@@ -2272,7 +2272,7 @@ define <4 x i32> @ushll2_4s(ptr %A) nounwind {
; CHECK-GI-LABEL: ushll2_4s:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: ldr q0, [x0]
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #1
; CHECK-GI-NEXT: ret
%load1 = load <8 x i16>, ptr %A
@@ -2292,7 +2292,7 @@ define <2 x i64> @ushll2_2d(ptr %A) nounwind {
; CHECK-GI-LABEL: ushll2_2d:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: ldr q0, [x0]
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: ushll v0.2d, v0.2s, #1
; CHECK-GI-NEXT: ret
%load1 = load <4 x i32>, ptr %A
@@ -2892,7 +2892,7 @@ define <8 x i16> @sshll2_8h(ptr %A) nounwind {
; CHECK-GI-LABEL: sshll2_8h:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: ldr q0, [x0]
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #1
; CHECK-GI-NEXT: ret
%load1 = load <16 x i8>, ptr %A
@@ -2912,7 +2912,7 @@ define <4 x i32> @sshll2_4s(ptr %A) nounwind {
; CHECK-GI-LABEL: sshll2_4s:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: ldr q0, [x0]
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: sshll v0.4s, v0.4h, #1
; CHECK-GI-NEXT: ret
%load1 = load <8 x i16>, ptr %A
@@ -2932,7 +2932,7 @@ define <2 x i64> @sshll2_2d(ptr %A) nounwind {
; CHECK-GI-LABEL: sshll2_2d:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: ldr q0, [x0]
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: sshll v0.2d, v0.2s, #1
; CHECK-GI-NEXT: ret
%load1 = load <4 x i32>, ptr %A
diff --git a/llvm/test/CodeGen/AArch64/bitreverse.ll b/llvm/test/CodeGen/AArch64/bitreverse.ll
index 9e2228aa47c63..61f67328be38e 100644
--- a/llvm/test/CodeGen/AArch64/bitreverse.ll
+++ b/llvm/test/CodeGen/AArch64/bitreverse.ll
@@ -19,8 +19,7 @@ define <2 x i16> @f(<2 x i16> %a) {
; GISEL-NEXT: uzp1 v0.4h, v0.4h, v0.4h
; GISEL-NEXT: rev16 v0.8b, v0.8b
; GISEL-NEXT: rbit v0.8b, v0.8b
-; GISEL-NEXT: ushll v0.4s, v0.4h, #0
-; GISEL-NEXT: // kill: def $d0 killed $d0 killed $q0
+; GISEL-NEXT: zip1 v0.4h, v0.4h, v0.4h
; GISEL-NEXT: ret
%b = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> %a)
ret <2 x i16> %b
@@ -157,8 +156,7 @@ define <4 x i8> @g_vec_4x8(<4 x i8> %a) {
; GISEL: // %bb.0:
; GISEL-NEXT: uzp1 v0.8b, v0.8b, v0.8b
; GISEL-NEXT: rbit v0.8b, v0.8b
-; GISEL-NEXT: ushll v0.8h, v0.8b, #0
-; GISEL-NEXT: // kill: def $d0 killed $d0 killed $q0
+; GISEL-NEXT: zip1 v0.8b, v0.8b, v0.8b
; GISEL-NEXT: ret
%b = call <4 x i8> @llvm.bitreverse.v4i8(<4 x i8> %a)
ret <4 x i8> %b
diff --git a/llvm/test/CodeGen/AArch64/bswap.ll b/llvm/test/CodeGen/AArch64/bswap.ll
index f5a455917a1e3..8b297b77fe2f4 100644
--- a/llvm/test/CodeGen/AArch64/bswap.ll
+++ b/llvm/test/CodeGen/AArch64/bswap.ll
@@ -184,8 +184,7 @@ define <2 x i16> @bswap_v2i16(<2 x i16> %a){
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: uzp1 v0.4h, v0.4h, v0.4h
; CHECK-GI-NEXT: rev16 v0.8b, v0.8b
-; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: zip1 v0.4h, v0.4h, v0.4h
; CHECK-GI-NEXT: ret
entry:
%res = call <2 x i16> @llvm.bswap.v2i16(<2 x i16> %a)
diff --git a/llvm/test/CodeGen/AArch64/concat-vector.ll b/llvm/test/CodeGen/AArch64/concat-vector.ll
index e6e863b074592..bbeea72d9055f 100644
--- a/llvm/test/CodeGen/AArch64/concat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/concat-vector.ll
@@ -338,7 +338,7 @@ define <8 x i16> @concat_high_low_v8i16(<8 x i16> %a_vec, <8 x i16> %b_vec) {
;
; CHECK-GI-LABEL: concat_high_low_v8i16:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT: ret
entry:
@@ -349,17 +349,11 @@ entry:
}
define <8 x i16> @concat_low_high_v8i16(<8 x i16> %a_vec, <8 x i16> %b_vec) {
-; CHECK-SD-LABEL: concat_low_high_v8i16:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: concat_low_high_v8i16:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
-; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: concat_low_high_v8i16:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v1.16b, v1.16b, v1.16b, #8
+; CHECK-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-NEXT: ret
entry:
%shuffle.i3 = shufflevector <8 x i16> %a_vec, <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%shuffle.i = shufflevector <8 x i16> %b_vec, <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
diff --git a/llvm/test/CodeGen/AArch64/double_reduct.ll b/llvm/test/CodeGen/AArch64/double_reduct.ll
index 3172735481d70..ac23d7d360fe5 100644
--- a/llvm/test/CodeGen/AArch64/double_reduct.ll
+++ b/llvm/test/CodeGen/AArch64/double_reduct.ll
@@ -62,8 +62,8 @@ define float @fmul_f32(<8 x float> %a, <4 x float> %b) {
; CHECK-GI-LABEL: fmul_f32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: fmul v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: mov d3, v2.d[1]
-; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: ext v3.16b, v2.16b, v2.16b, #8
+; CHECK-GI-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: fmul v0.2s, v0.2s, v1.2s
; CHECK-GI-NEXT: fmul v1.2s, v2.2s, v3.2s
; CHECK-GI-NEXT: mov s2, v0.s[1]
@@ -90,8 +90,8 @@ define float @fmul_f32_same(<4 x float> %a, <4 x float> %b) {
;
; CHECK-GI-LABEL: fmul_f32_same:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d2, v0.d[1]
-; CHECK-GI-NEXT: mov d3, v1.d[1]
+; CHECK-GI-NEXT: ext v2.16b, v0.16b, v0.16b, #8
+; CHECK-GI-NEXT: ext v3.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: fmul v0.2s, v0.2s, v2.2s
; CHECK-GI-NEXT: fmul v1.2s, v1.2s, v3.2s
; CHECK-GI-NEXT: mov s2, v0.s[1]
@@ -386,11 +386,11 @@ define i32 @mul_i32(<8 x i32> %a, <4 x i32> %b) {
;
; CHECK-GI-LABEL: mul_i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d3, v0.d[1]
-; CHECK-GI-NEXT: mov d4, v1.d[1]
+; CHECK-GI-NEXT: ext v3.16b, v0.16b, v0.16b, #8
+; CHECK-GI-NEXT: ext v4.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: mul v0.2s, v0.2s, v3.2s
; CHECK-GI-NEXT: mul v1.2s, v1.2s, v4.2s
-; CHECK-GI-NEXT: mov d3, v2.d[1]
+; CHECK-GI-NEXT: ext v3.16b, v2.16b, v2.16b, #8
; CHECK-GI-NEXT: mul v0.2s, v0.2s, v1.2s
; CHECK-GI-NEXT: mul v1.2s, v2.2s, v3.2s
; CHECK-GI-NEXT: mov w8, v0.s[1]
@@ -419,8 +419,8 @@ define i32 @mul_i32_same(<4 x i32> %a, <4 x i32> %b) {
;
; CHECK-GI-LABEL: mul_i32_same:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d2, v0.d[1]
-; CHECK-GI-NEXT: mov d3, v1.d[1]
+; CHECK-GI-NEXT: ext v2.16b, v0.16b, v0.16b, #8
+; CHECK-GI-NEXT: ext v3.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: mul v0.2s, v0.2s, v2.2s
; CHECK-GI-NEXT: mul v1.2s, v1.2s, v3.2s
; CHECK-GI-NEXT: mov w8, v0.s[1]
@@ -452,8 +452,8 @@ define i32 @and_i32(<8 x i32> %a, <4 x i32> %b) {
; CHECK-GI-LABEL: and_i32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
-; CHECK-GI-NEXT: mov d1, v2.d[1]
-; CHECK-GI-NEXT: mov d3, v0.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v2.16b, v2.16b, #8
+; CHECK-GI-NEXT: ext v3.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: and v1.8b, v2.8b, v1.8b
; CHECK-GI-NEXT: and v0.8b, v0.8b, v3.8b
; CHECK-GI-NEXT: mov w8, v1.s[1]
@@ -483,8 +483,8 @@ define i32 @and_i32_same(<4 x i32> %a, <4 x i32> %b) {
;
; CHECK-GI-LABEL: and_i32_same:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d2, v0.d[1]
-; CHECK-GI-NEXT: mov d3, v1.d[1]
+; CHECK-GI-NEXT: ext v2.16b, v0.16b, v0.16b, #8
+; CHECK-GI-NEXT: ext v3.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: and v0.8b, v0.8b, v2.8b
; CHECK-GI-NEXT: and v1.8b, v1.8b, v3.8b
; CHECK-GI-NEXT: mov w8, v0.s[1]
@@ -516,8 +516,8 @@ define i32 @or_i32(<8 x i32> %a, <4 x i32> %b) {
; CHECK-GI-LABEL: or_i32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
-; CHECK-GI-NEXT: mov d1, v2.d[1]
-; CHECK-GI-NEXT: mov d3, v0.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v2.16b, v2.16b, #8
+; CHECK-GI-NEXT: ext v3.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: orr v1.8b, v2.8b, v1.8b
; CHECK-GI-NEXT: orr v0.8b, v0.8b, v3.8b
; CHECK-GI-NEXT: mov w8, v1.s[1]
@@ -547,8 +547,8 @@ define i32 @or_i32_same(<4 x i32> %a, <4 x i32> %b) {
;
; CHECK-GI-LABEL: or_i32_same:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d2, v0.d[1]
-; CHECK-GI-NEXT: mov d3, v1.d[1]
+; CHECK-GI-NEXT: ext v2.16b, v0.16b, v0.16b, #8
+; CHECK-GI-NEXT: ext v3.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: orr v0.8b, v0.8b, v2.8b
; CHECK-GI-NEXT: orr v1.8b, v1.8b, v3.8b
; CHECK-GI-NEXT: mov w8, v0.s[1]
@@ -580,8 +580,8 @@ define i32 @xor_i32(<8 x i32> %a, <4 x i32> %b) {
; CHECK-GI-LABEL: xor_i32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: eor v0.16b, v0.16b, v1.16b
-; CHECK-GI-NEXT: mov d1, v2.d[1]
-; CHECK-GI-NEXT: mov d3, v0.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v2.16b, v2.16b, #8
+; CHECK-GI-NEXT: ext v3.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: eor v1.8b, v2.8b, v1.8b
; CHECK-GI-NEXT: eor v0.8b, v0.8b, v3.8b
; CHECK-GI-NEXT: mov w8, v1.s[1]
@@ -611,8 +611,8 @@ define i32 @xor_i32_same(<4 x i32> %a, <4 x i32> %b) {
;
; CHECK-GI-LABEL: xor_i32_same:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d2, v0.d[1]
-; CHECK-GI-NEXT: mov d3, v1.d[1]
+; CHECK-GI-NEXT: ext v2.16b, v0.16b, v0.16b, #8
+; CHECK-GI-NEXT: ext v3.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: eor v0.8b, v0.8b, v2.8b
; CHECK-GI-NEXT: eor v1.8b, v1.8b, v3.8b
; CHECK-GI-NEXT: mov w8, v0.s[1]
@@ -913,8 +913,8 @@ define float @nested_mul_f32(<4 x float> %a, <4 x float> %b, float %c, float %d)
;
; CHECK-GI-LABEL: nested_mul_f32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d4, v0.d[1]
-; CHECK-GI-NEXT: mov d5, v1.d[1]
+; CHECK-GI-NEXT: ext v4.16b, v0.16b, v0.16b, #8
+; CHECK-GI-NEXT: ext v5.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: fmul v0.2s, v0.2s, v4.2s
; CHECK-GI-NEXT: fmul v1.2s, v1.2s, v5.2s
; CHECK-GI-NEXT: mov s4, v0.s[1]
@@ -1065,8 +1065,8 @@ define i32 @nested_mul_i32(<4 x i32> %a, <4 x i32> %b, i32 %c, i32 %d) {
;
; CHECK-GI-LABEL: nested_mul_i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d2, v0.d[1]
-; CHECK-GI-NEXT: mov d3, v1.d[1]
+; CHECK-GI-NEXT: ext v2.16b, v0.16b, v0.16b, #8
+; CHECK-GI-NEXT: ext v3.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: mul v0.2s, v0.2s, v2.2s
; CHECK-GI-NEXT: mul v1.2s, v1.2s, v3.2s
; CHECK-GI-NEXT: mov w8, v0.s[1]
@@ -1102,8 +1102,8 @@ define i32 @nested_and_i32(<4 x i32> %a, <4 x i32> %b, i32 %c, i32 %d) {
;
; CHECK-GI-LABEL: nested_and_i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d2, v0.d[1]
-; CHECK-GI-NEXT: mov d3, v1.d[1]
+; CHECK-GI-NEXT: ext v2.16b, v0.16b, v0.16b, #8
+; CHECK-GI-NEXT: ext v3.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: and v0.8b, v0.8b, v2.8b
; CHECK-GI-NEXT: and v1.8b, v1.8b, v3.8b
; CHECK-GI-NEXT: mov w8, v0.s[1]
@@ -1139,8 +1139,8 @@ define i32 @nested_or_i32(<4 x i32> %a, <4 x i32> %b, i32 %c, i32 %d) {
;
; CHECK-GI-LABEL: nested_or_i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d2, v0.d[1]
-; CHECK-GI-NEXT: mov d3, v1.d[1]
+; CHECK-GI-NEXT: ext v2.16b, v0.16b, v0.16b, #8
+; CHECK-GI-NEXT: ext v3.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: orr v0.8b, v0.8b, v2.8b
; CHECK-GI-NEXT: orr v1.8b, v1.8b, v3.8b
; CHECK-GI-NEXT: mov w8, v0.s[1]
@@ -1176,8 +1176,8 @@ define i32 @nested_xor_i32(<4 x i32> %a, <4 x i32> %b, i32 %c, i32 %d) {
;
; CHECK-GI-LABEL: nested_xor_i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d2, v0.d[1]
-; CHECK-GI-NEXT: mov d3, v1.d[1]
+; CHECK-GI-NEXT: ext v2.16b, v0.16b, v0.16b, #8
+; CHECK-GI-NEXT: ext v3.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: eor v0.8b, v0.8b, v2.8b
; CHECK-GI-NEXT: eor v1.8b, v1.8b, v3.8b
; CHECK-GI-NEXT: mov w8, v0.s[1]
diff --git a/llvm/test/CodeGen/AArch64/dup.ll b/llvm/test/CodeGen/AArch64/dup.ll
index d4da0e8038cd4..7d5a2fad6de6b 100644
--- a/llvm/test/CodeGen/AArch64/dup.ll
+++ b/llvm/test/CodeGen/AArch64/dup.ll
@@ -199,8 +199,7 @@ define <4 x i8> @dup_v4i8(i8 %a) {
; CHECK-GI-LABEL: dup_v4i8:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: dup v0.8b, w0
-; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: zip1 v0.8b, v0.8b, v0.8b
; CHECK-GI-NEXT: ret
entry:
%b = insertelement <4 x i8> poison, i8 %a, i64 0
@@ -219,8 +218,7 @@ define <4 x i8> @duplane0_v4i8(<4 x i8> %b) {
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b
; CHECK-GI-NEXT: dup v0.8b, v0.b[0]
-; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: zip1 v0.8b, v0.8b, v0.8b
; CHECK-GI-NEXT: ret
entry:
%c = shufflevector <4 x i8> %b, <4 x i8> poison, <4 x i32> zeroinitializer
@@ -237,8 +235,7 @@ define <4 x i8> @loaddup_v4i8(ptr %p) {
; CHECK-GI-LABEL: loaddup_v4i8:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: ld1r { v0.8b }, [x0]
-; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: zip1 v0.8b, v0.8b, v0.8b
; CHECK-GI-NEXT: ret
entry:
%a = load i8, ptr %p
@@ -260,8 +257,7 @@ define <4 x i8> @loaddup_str_v4i8(ptr %p) {
; CHECK-GI-NEXT: ldr b0, [x0]
; CHECK-GI-NEXT: strb wzr, [x0]
; CHECK-GI-NEXT: dup v0.8b, v0.b[0]
-; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: zip1 v0.8b, v0.8b, v0.8b
; CHECK-GI-NEXT: ret
entry:
%a = load i8, ptr %p
@@ -454,8 +450,7 @@ define <2 x i16> @dup_v2i16(i16 %a) {
; CHECK-GI-LABEL: dup_v2i16:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: dup v0.4h, w0
-; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: zip1 v0.4h, v0.4h, v0.4h
; CHECK-GI-NEXT: ret
entry:
%b = insertelement <2 x i16> poison, i16 %a, i64 0
@@ -474,8 +469,7 @@ define <2 x i16> @duplane0_v2i16(<2 x i16> %b) {
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: uzp1 v0.4h, v0.4h, v0.4h
; CHECK-GI-NEXT: dup v0.4h, v0.h[0]
-; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: zip1 v0.4h, v0.4h, v0.4h
; CHECK-GI-NEXT: ret
entry:
%c = shufflevector <2 x i16> %b, <2 x i16> poison, <2 x i32> zeroinitializer
@@ -492,8 +486,7 @@ define <2 x i16> @loaddup_v2i16(ptr %p) {
; CHECK-GI-LABEL: loaddup_v2i16:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: ld1r { v0.4h }, [x0]
-; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: zip1 v0.4h, v0.4h, v0.4h
; CHECK-GI-NEXT: ret
entry:
%a = load i16, ptr %p
@@ -515,8 +508,7 @@ define <2 x i16> @loaddup_str_v2i16(ptr %p) {
; CHECK-GI-NEXT: ldr h0, [x0]
; CHECK-GI-NEXT: strh wzr, [x0]
; CHECK-GI-NEXT: dup v0.4h, v0.h[0]
-; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: zip1 v0.4h, v0.4h, v0.4h
; CHECK-GI-NEXT: ret
entry:
%a = load i16, ptr %p
diff --git a/llvm/test/CodeGen/AArch64/ext-narrow-index.ll b/llvm/test/CodeGen/AArch64/ext-narrow-index.ll
index f62cfef9baf28..268d2144662fe 100644
--- a/llvm/test/CodeGen/AArch64/ext-narrow-index.ll
+++ b/llvm/test/CodeGen/AArch64/ext-narrow-index.ll
@@ -28,16 +28,11 @@ entry:
}
define <8 x i8> @i8_off8(<16 x i8> %arg1, <16 x i8> %arg2) {
-; CHECK-SD-LABEL: i8_off8:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GISEL-LABEL: i8_off8:
-; CHECK-GISEL: // %bb.0: // %entry
-; CHECK-GISEL-NEXT: mov d0, v0.d[1]
-; CHECK-GISEL-NEXT: ret
+; CHECK-LABEL: i8_off8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
entry:
%shuffle = shufflevector <16 x i8> %arg1, <16 x i8> %arg2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
ret <8 x i8> %shuffle
@@ -220,16 +215,11 @@ entry:
}
define <8 x i8> @i8_zero_off8(<16 x i8> %arg1) {
-; CHECK-SD-LABEL: i8_zero_off8:
-; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GISEL-LABEL: i8_zero_off8:
-; CHECK-GISEL: // %bb.0: // %entry
-; CHECK-GISEL-NEXT: mov d0, v0.d[1]
-; CHECK-GISEL-NEXT: ret
+; CHECK-LABEL: i8_zero_off8:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: ret
entry:
%shuffle = shufflevector <16 x i8> %arg1, <16 x i8> zeroinitializer, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
ret <8 x i8> %shuffle
diff --git a/llvm/test/CodeGen/AArch64/fptoi.ll b/llvm/test/CodeGen/AArch64/fptoi.ll
index d82bcb90c8975..caffdd548e710 100644
--- a/llvm/test/CodeGen/AArch64/fptoi.ll
+++ b/llvm/test/CodeGen/AArch64/fptoi.ll
@@ -5732,8 +5732,7 @@ define <2 x i16> @fptos_v2f16_v2i16(<2 x half> %a) {
; CHECK-FP16-GI-LABEL: fptos_v2f16_v2i16:
; CHECK-FP16-GI: // %bb.0: // %entry
; CHECK-FP16-GI-NEXT: fcvtzs v0.4h, v0.4h
-; CHECK-FP16-GI-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-FP16-GI-NEXT: zip1 v0.4h, v0.4h, v0.4h
; CHECK-FP16-GI-NEXT: ret
entry:
%c = fptosi <2 x half> %a to <2 x i16>
@@ -5764,8 +5763,7 @@ define <2 x i16> @fptou_v2f16_v2i16(<2 x half> %a) {
; CHECK-FP16-GI-LABEL: fptou_v2f16_v2i16:
; CHECK-FP16-GI: // %bb.0: // %entry
; CHECK-FP16-GI-NEXT: fcvtzu v0.4h, v0.4h
-; CHECK-FP16-GI-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-FP16-GI-NEXT: zip1 v0.4h, v0.4h, v0.4h
; CHECK-FP16-GI-NEXT: ret
entry:
%c = fptoui <2 x half> %a to <2 x i16>
@@ -5998,8 +5996,7 @@ define <2 x i8> @fptos_v2f16_v2i8(<2 x half> %a) {
; CHECK-FP16-GI-LABEL: fptos_v2f16_v2i8:
; CHECK-FP16-GI: // %bb.0: // %entry
; CHECK-FP16-GI-NEXT: fcvtzs v0.4h, v0.4h
-; CHECK-FP16-GI-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-FP16-GI-NEXT: zip1 v0.4h, v0.4h, v0.4h
; CHECK-FP16-GI-NEXT: ret
entry:
%c = fptosi <2 x half> %a to <2 x i8>
@@ -6030,8 +6027,7 @@ define <2 x i8> @fptou_v2f16_v2i8(<2 x half> %a) {
; CHECK-FP16-GI-LABEL: fptou_v2f16_v2i8:
; CHECK-FP16-GI: // %bb.0: // %entry
; CHECK-FP16-GI-NEXT: fcvtzu v0.4h, v0.4h
-; CHECK-FP16-GI-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-FP16-GI-NEXT: zip1 v0.4h, v0.4h, v0.4h
; CHECK-FP16-GI-NEXT: ret
entry:
%c = fptoui <2 x half> %a to <2 x i8>
diff --git a/llvm/test/CodeGen/AArch64/highextractbitcast.ll b/llvm/test/CodeGen/AArch64/highextractbitcast.ll
index de2911b8a5127..f3dd4975336b5 100644
--- a/llvm/test/CodeGen/AArch64/highextractbitcast.ll
+++ b/llvm/test/CodeGen/AArch64/highextractbitcast.ll
@@ -162,7 +162,7 @@ define <4 x i32> @test_smull_high_s16_bitcasta1_wrongindex(<2 x i64> %aa, <8 x i
; CHECK-GI-LABEL: test_smull_high_s16_bitcasta1_wrongindex:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #4
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: smull v0.4s, v0.4h, v1.4h
; CHECK-GI-NEXT: ret
entry:
@@ -197,7 +197,7 @@ define <4 x i32> @test_smull_high_s16_bitcastb1_wrongindex(<8 x i16> %a, <16 x i
;
; CHECK-GI-LABEL: test_smull_high_s16_bitcastb1_wrongindex:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: ext v1.16b, v1.16b, v0.16b, #6
; CHECK-GI-NEXT: smull v0.4s, v0.4h, v1.4h
; CHECK-GI-NEXT: ret
@@ -210,12 +210,12 @@ entry:
}
define <4 x i32> @test_smull_high_s16_bitcasta2_wrongindex(<4 x i32> %a, <8 x i16> %b) #0 {
-; CHECK-LE-LABEL: test_smull_high_s16_bitcasta2_wrongindex:
-; CHECK-LE: // %bb.0: // %entry
-; CHECK-LE-NEXT: ext v0.16b, v0.16b, v0.16b, #4
-; CHECK-LE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-LE-NEXT: smull v0.4s, v0.4h, v1.4h
-; CHECK-LE-NEXT: ret
+; CHECK-LABEL: test_smull_high_s16_bitcasta2_wrongindex:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #4
+; CHECK-NEXT: ext v1.16b, v1.16b, v1.16b, #8
+; CHECK-NEXT: smull v0.4s, v0.4h, v1.4h
+; CHECK-NEXT: ret
;
; CHECK-BE-LABEL: test_smull_high_s16_bitcasta2_wrongindex:
; CHECK-BE: // %bb.0: // %entry
@@ -230,13 +230,6 @@ define <4 x i32> @test_smull_high_s16_bitcasta2_wrongindex(<4 x i32> %a, <8 x i1
; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-BE-NEXT: ret
-;
-; CHECK-GI-LABEL: test_smull_high_s16_bitcasta2_wrongindex:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #4
-; CHECK-GI-NEXT: mov d1, v1.d[1]
-; CHECK-GI-NEXT: smull v0.4s, v0.4h, v1.4h
-; CHECK-GI-NEXT: ret
entry:
%s1a = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 1, i32 2>
%s1 = bitcast <2 x i32> %s1a to <4 x i16>
@@ -269,7 +262,7 @@ define <4 x i32> @test_smull_high_s16_bitcastb2_wrongindex(<8 x i16> %a, <16 x i
;
; CHECK-GI-LABEL: test_smull_high_s16_bitcastb2_wrongindex:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: ext v1.16b, v1.16b, v0.16b, #4
; CHECK-GI-NEXT: smull v0.4s, v0.4h, v1.4h
; CHECK-GI-NEXT: ret
@@ -301,7 +294,7 @@ define <4 x i32> @test_smull_high_s16_splata1(<2 x i64> %aa, <8 x i16> %b) #0 {
;
; CHECK-GI-LABEL: test_smull_high_s16_splata1:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: smull v0.4s, v1.4h, v0.h[3]
; CHECK-GI-NEXT: ret
entry:
@@ -331,7 +324,7 @@ define <4 x i32> @test_smull_high_s16_splatb1(<8 x i16> %a, <16 x i8> %bb) #0 {
;
; CHECK-GI-LABEL: test_smull_high_s16_splatb1:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: smull v0.4s, v0.4h, v1.h[3]
; CHECK-GI-NEXT: ret
entry:
@@ -343,12 +336,12 @@ entry:
}
define <4 x i32> @test_smull_high_s16_splata2(<4 x i32> %a, <8 x i16> %b) #0 {
-; CHECK-LE-LABEL: test_smull_high_s16_splata2:
-; CHECK-LE: // %bb.0: // %entry
-; CHECK-LE-NEXT: dup v0.2s, v0.s[3]
-; CHECK-LE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
-; CHECK-LE-NEXT: smull v0.4s, v0.4h, v1.4h
-; CHECK-LE-NEXT: ret
+; CHECK-LABEL: test_smull_high_s16_splata2:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: dup v0.2s, v0.s[3]
+; CHECK-NEXT: ext v1.16b, v1.16b, v1.16b, #8
+; CHECK-NEXT: smull v0.4s, v0.4h, v1.4h
+; CHECK-NEXT: ret
;
; CHECK-BE-LABEL: test_smull_high_s16_splata2:
; CHECK-BE: // %bb.0: // %entry
@@ -363,13 +356,6 @@ define <4 x i32> @test_smull_high_s16_splata2(<4 x i32> %a, <8 x i16> %b) #0 {
; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-BE-NEXT: ret
-;
-; CHECK-GI-LABEL: test_smull_high_s16_splata2:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: dup v0.2s, v0.s[3]
-; CHECK-GI-NEXT: mov d1, v1.d[1]
-; CHECK-GI-NEXT: smull v0.4s, v0.4h, v1.4h
-; CHECK-GI-NEXT: ret
entry:
%s1a = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 3, i32 3>
%s1 = bitcast <2 x i32> %s1a to <4 x i16>
@@ -379,12 +365,12 @@ entry:
}
define <4 x i32> @test_smull_high_s16_splatb2(<8 x i16> %a, <16 x i8> %b) #0 {
-; CHECK-LE-LABEL: test_smull_high_s16_splatb2:
-; CHECK-LE: // %bb.0: // %entry
-; CHECK-LE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-LE-NEXT: dup v1.8b, v1.b[3]
-; CHECK-LE-NEXT: smull v0.4s, v0.4h, v1.4h
-; CHECK-LE-NEXT: ret
+; CHECK-LABEL: test_smull_high_s16_splatb2:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: dup v1.8b, v1.b[3]
+; CHECK-NEXT: smull v0.4s, v0.4h, v1.4h
+; CHECK-NEXT: ret
;
; CHECK-BE-LABEL: test_smull_high_s16_splatb2:
; CHECK-BE: // %bb.0: // %entry
@@ -399,13 +385,6 @@ define <4 x i32> @test_smull_high_s16_splatb2(<8 x i16> %a, <16 x i8> %b) #0 {
; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-BE-NEXT: ret
-;
-; CHECK-GI-LABEL: test_smull_high_s16_splatb2:
-; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d0, v0.d[1]
-; CHECK-GI-NEXT: dup v1.8b, v1.b[3]
-; CHECK-GI-NEXT: smull v0.4s, v0.4h, v1.4h
-; CHECK-GI-NEXT: ret
entry:
%s1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%s2a = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
@@ -632,7 +611,7 @@ define <2 x i64> @hadd32_zext_asr(<16 x i8> %src1a) {
;
; CHECK-GI-LABEL: hadd32_zext_asr:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: ushll v0.2d, v0.2s, #1
; CHECK-GI-NEXT: ret
%src1 = bitcast <16 x i8> %src1a to <4 x i32>
@@ -660,7 +639,7 @@ define <2 x i64> @test_umull_high_s16_splata1(<2 x i64> %aa, <4 x i32> %b) #0 {
;
; CHECK-GI-LABEL: test_umull_high_s16_splata1:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: mov d1, v1.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: umull v0.2d, v1.2s, v0.s[1]
; CHECK-GI-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/AArch64/neon-extadd.ll b/llvm/test/CodeGen/AArch64/neon-extadd.ll
index f5e566f49b91e..627dab6402791 100644
--- a/llvm/test/CodeGen/AArch64/neon-extadd.ll
+++ b/llvm/test/CodeGen/AArch64/neon-extadd.ll
@@ -1266,97 +1266,95 @@ define <20 x i32> @v20(<20 x i8> %s0, <20 x i8> %s1) {
;
; CHECK-GI-LABEL: v20:
; CHECK-GI: // %bb.0: // %entry
-; CHECK-GI-NEXT: and w9, w0, #0xff
; CHECK-GI-NEXT: ldrb w10, [sp, #96]
-; CHECK-GI-NEXT: and w11, w1, #0xff
+; CHECK-GI-NEXT: and w9, w0, #0xff
+; CHECK-GI-NEXT: ldrb w12, [sp, #104]
; CHECK-GI-NEXT: fmov s0, w9
; CHECK-GI-NEXT: ldrb w9, [sp]
-; CHECK-GI-NEXT: ldrb w12, [sp, #104]
-; CHECK-GI-NEXT: fmov s2, w10
+; CHECK-GI-NEXT: and w11, w1, #0xff
+; CHECK-GI-NEXT: fmov s1, w10
; CHECK-GI-NEXT: ldrb w10, [sp, #160]
-; CHECK-GI-NEXT: fmov s1, w9
+; CHECK-GI-NEXT: fmov s2, w9
; CHECK-GI-NEXT: ldrb w9, [sp, #168]
+; CHECK-GI-NEXT: fmov s3, w10
; CHECK-GI-NEXT: mov v0.h[1], w11
; CHECK-GI-NEXT: ldrb w11, [sp, #8]
-; CHECK-GI-NEXT: fmov s3, w10
-; CHECK-GI-NEXT: mov v2.h[1], w12
+; CHECK-GI-NEXT: mov v1.h[1], w12
; CHECK-GI-NEXT: and w10, w2, #0xff
; CHECK-GI-NEXT: and w12, w5, #0xff
-; CHECK-GI-NEXT: mov v1.h[1], w11
+; CHECK-GI-NEXT: mov v2.h[1], w11
; CHECK-GI-NEXT: and w11, w4, #0xff
; CHECK-GI-NEXT: mov v3.h[1], w9
; CHECK-GI-NEXT: ldrb w9, [sp, #112]
; CHECK-GI-NEXT: mov v0.h[2], w10
; CHECK-GI-NEXT: ldrb w10, [sp, #16]
-; CHECK-GI-NEXT: mov v2.h[2], w9
+; CHECK-GI-NEXT: mov v1.h[2], w9
; CHECK-GI-NEXT: ldrb w9, [sp, #176]
-; CHECK-GI-NEXT: mov v1.h[2], w10
+; CHECK-GI-NEXT: mov v2.h[2], w10
; CHECK-GI-NEXT: and w10, w3, #0xff
; CHECK-GI-NEXT: mov v3.h[2], w9
; CHECK-GI-NEXT: ldrb w9, [sp, #120]
; CHECK-GI-NEXT: mov v0.h[3], w10
; CHECK-GI-NEXT: ldrb w10, [sp, #24]
-; CHECK-GI-NEXT: mov v2.h[3], w9
+; CHECK-GI-NEXT: mov v1.h[3], w9
; CHECK-GI-NEXT: ldrb w9, [sp, #184]
-; CHECK-GI-NEXT: mov v1.h[3], w10
-; CHECK-GI-NEXT: ldr w10, [sp, #64]
+; CHECK-GI-NEXT: mov v2.h[3], w10
+; CHECK-GI-NEXT: ldrb w10, [sp, #128]
; CHECK-GI-NEXT: mov v3.h[3], w9
-; CHECK-GI-NEXT: ldrb w9, [sp, #128]
+; CHECK-GI-NEXT: ldrb w9, [sp, #32]
; CHECK-GI-NEXT: mov v0.h[4], w11
-; CHECK-GI-NEXT: ldrb w11, [sp, #32]
-; CHECK-GI-NEXT: fmov s4, w10
+; CHECK-GI-NEXT: ldr w11, [sp, #64]
+; CHECK-GI-NEXT: mov v1.h[4], w10
; CHECK-GI-NEXT: ldrb w10, [sp, #192]
+; CHECK-GI-NEXT: fmov s4, w11
+; CHECK-GI-NEXT: ldrb w11, [sp, #136]
; CHECK-GI-NEXT: mov v2.h[4], w9
-; CHECK-GI-NEXT: ldr w9, [sp, #72]
-; CHECK-GI-NEXT: mov v1.h[4], w11
-; CHECK-GI-NEXT: ldr w11, [sp, #224]
+; CHECK-GI-NEXT: ldr w9, [sp, #224]
; CHECK-GI-NEXT: mov v3.h[4], w10
-; CHECK-GI-NEXT: ldrb w10, [sp, #136]
-; CHECK-GI-NEXT: mov v4.b[1], w9
-; CHECK-GI-NEXT: fmov s5, w11
-; CHECK-GI-NEXT: ldr w11, [sp, #232]
+; CHECK-GI-NEXT: ldrb w10, [sp, #40]
; CHECK-GI-NEXT: mov v0.h[5], w12
-; CHECK-GI-NEXT: ldrb w12, [sp, #40]
+; CHECK-GI-NEXT: ldr w12, [sp, #72]
+; CHECK-GI-NEXT: fmov s5, w9
+; CHECK-GI-NEXT: mov v1.h[5], w11
+; CHECK-GI-NEXT: ldrb w9, [sp, #200]
; CHECK-GI-NEXT: mov v2.h[5], w10
-; CHECK-GI-NEXT: ldrb w10, [sp, #200]
+; CHECK-GI-NEXT: ldr w10, [sp, #232]
+; CHECK-GI-NEXT: mov v4.b[1], w12
+; CHECK-GI-NEXT: mov v3.h[5], w9
; CHECK-GI-NEXT: ldrb w9, [sp, #144]
-; CHECK-GI-NEXT: mov v5.b[1], w11
-; CHECK-GI-NEXT: mov v1.h[5], w12
-; CHECK-GI-NEXT: mov v3.h[5], w10
-; CHECK-GI-NEXT: ldr w10, [sp, #80]
-; CHECK-GI-NEXT: ldr w12, [sp, #240]
; CHECK-GI-NEXT: and w11, w6, #0xff
+; CHECK-GI-NEXT: mov v5.b[1], w10
+; CHECK-GI-NEXT: ldrb w10, [sp, #48]
; CHECK-GI-NEXT: mov v0.h[6], w11
-; CHECK-GI-NEXT: ldrb w11, [sp, #48]
-; CHECK-GI-NEXT: mov v2.h[6], w9
+; CHECK-GI-NEXT: mov v1.h[6], w9
; CHECK-GI-NEXT: ldrb w9, [sp, #208]
-; CHECK-GI-NEXT: mov v4.b[2], w10
-; CHECK-GI-NEXT: ldrb w10, [sp, #152]
-; CHECK-GI-NEXT: mov v5.b[2], w12
-; CHECK-GI-NEXT: mov v1.h[6], w11
-; CHECK-GI-NEXT: ldr w11, [sp, #248]
+; CHECK-GI-NEXT: ldr w11, [sp, #80]
+; CHECK-GI-NEXT: mov v2.h[6], w10
+; CHECK-GI-NEXT: ldr w10, [sp, #240]
; CHECK-GI-NEXT: mov v3.h[6], w9
-; CHECK-GI-NEXT: ldr w9, [sp, #88]
-; CHECK-GI-NEXT: and w12, w7, #0xff
-; CHECK-GI-NEXT: mov v0.h[7], w12
+; CHECK-GI-NEXT: ldrb w9, [sp, #152]
+; CHECK-GI-NEXT: mov v4.b[2], w11
+; CHECK-GI-NEXT: mov v5.b[2], w10
+; CHECK-GI-NEXT: ldrb w10, [sp, #56]
+; CHECK-GI-NEXT: and w11, w7, #0xff
+; CHECK-GI-NEXT: mov v1.h[7], w9
+; CHECK-GI-NEXT: ldrb w9, [sp, #216]
+; CHECK-GI-NEXT: mov v0.h[7], w11
; CHECK-GI-NEXT: mov v2.h[7], w10
-; CHECK-GI-NEXT: ldrb w12, [sp, #56]
-; CHECK-GI-NEXT: mov v4.b[3], w9
-; CHECK-GI-NEXT: ldrb w10, [sp, #216]
-; CHECK-GI-NEXT: mov v5.b[3], w11
-; CHECK-GI-NEXT: mov v1.h[7], w12
-; CHECK-GI-NEXT: mov v3.h[7], w10
-; CHECK-GI-NEXT: add v0.8h, v0.8h, v2.8h
-; CHECK-GI-NEXT: ushll v2.8h, v4.8b, #0
-; CHECK-GI-NEXT: ushll v4.8h, v5.8b, #0
-; CHECK-GI-NEXT: add v1.8h, v1.8h, v3.8h
-; CHECK-GI-NEXT: ushll v3.4s, v0.4h, #0
+; CHECK-GI-NEXT: ldr w10, [sp, #88]
+; CHECK-GI-NEXT: mov v3.h[7], w9
+; CHECK-GI-NEXT: ldr w9, [sp, #248]
+; CHECK-GI-NEXT: mov v4.b[3], w10
+; CHECK-GI-NEXT: mov v5.b[3], w9
+; CHECK-GI-NEXT: add v0.8h, v0.8h, v1.8h
+; CHECK-GI-NEXT: add v1.8h, v2.8h, v3.8h
+; CHECK-GI-NEXT: ushll v2.4s, v0.4h, #0
; CHECK-GI-NEXT: ushll2 v0.4s, v0.8h, #0
-; CHECK-GI-NEXT: add v2.4h, v2.4h, v4.4h
+; CHECK-GI-NEXT: uaddl v3.8h, v4.8b, v5.8b
; CHECK-GI-NEXT: ushll v4.4s, v1.4h, #0
; CHECK-GI-NEXT: ushll2 v1.4s, v1.8h, #0
-; CHECK-GI-NEXT: stp q3, q0, [x8]
-; CHECK-GI-NEXT: ushll v2.4s, v2.4h, #0
+; CHECK-GI-NEXT: stp q2, q0, [x8]
+; CHECK-GI-NEXT: ushll v2.4s, v3.4h, #0
; CHECK-GI-NEXT: stp q4, q1, [x8, #32]
; CHECK-GI-NEXT: str q2, [x8, #64]
; CHECK-GI-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/neon-perm.ll b/llvm/test/CodeGen/AArch64/neon-perm.ll
index 7218204ba844c..bf9e79e74f1f8 100644
--- a/llvm/test/CodeGen/AArch64/neon-perm.ll
+++ b/llvm/test/CodeGen/AArch64/neon-perm.ll
@@ -1792,16 +1792,10 @@ entry:
}
define <4 x i8> @test_vzip1_v4i8(<8 x i8> %p) {
-; CHECK-SD-LABEL: test_vzip1_v4i8:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: zip1 v0.8b, v0.8b, v0.8b
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: test_vzip1_v4i8:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: test_vzip1_v4i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: zip1 v0.8b, v0.8b, v0.8b
+; CHECK-NEXT: ret
%lo = shufflevector <8 x i8> %p, <8 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x i8> %lo
}
diff --git a/llvm/test/CodeGen/AArch64/neon-shift-left-long.ll b/llvm/test/CodeGen/AArch64/neon-shift-left-long.ll
index a8c55b476b810..50a022f632577 100644
--- a/llvm/test/CodeGen/AArch64/neon-shift-left-long.ll
+++ b/llvm/test/CodeGen/AArch64/neon-shift-left-long.ll
@@ -154,7 +154,7 @@ define <8 x i16> @test_sshll2_v16i8(<16 x i8> %a) {
;
; CHECK-GI-LABEL: test_sshll2_v16i8:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #3
; CHECK-GI-NEXT: ret
%1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -189,7 +189,7 @@ define <4 x i32> @test_sshll2_v8i16(<8 x i16> %a) {
;
; CHECK-GI-LABEL: test_sshll2_v8i16:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: sshll v0.4s, v0.4h, #9
; CHECK-GI-NEXT: ret
%1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -224,7 +224,7 @@ define <2 x i64> @test_sshll2_v4i32(<4 x i32> %a) {
;
; CHECK-GI-LABEL: test_sshll2_v4i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: sshll v0.2d, v0.2s, #19
; CHECK-GI-NEXT: ret
%1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
@@ -259,7 +259,7 @@ define <8 x i16> @test_ushll2_v16i8(<16 x i8> %a) {
;
; CHECK-GI-LABEL: test_ushll2_v16i8:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #3
; CHECK-GI-NEXT: ret
%1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -288,7 +288,7 @@ define <4 x i32> @test_ushll2_v8i16(<8 x i16> %a) {
;
; CHECK-GI-LABEL: test_ushll2_v8i16:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #9
; CHECK-GI-NEXT: ret
%1 = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -317,7 +317,7 @@ define <2 x i64> @test_ushll2_v4i32(<4 x i32> %a) {
;
; CHECK-GI-LABEL: test_ushll2_v4i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d0, v0.d[1]
+; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: ushll v0.2d, v0.2s, #19
; CHECK-GI-NEXT: ret
%1 = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
diff --git a/llvm/test/CodeGen/AArch64/phi.ll b/llvm/test/CodeGen/AArch64/phi.ll
index 02842c04bf7bf..cad959c077990 100644
--- a/llvm/test/CodeGen/AArch64/phi.ll
+++ b/llvm/test/CodeGen/AArch64/phi.ll
@@ -391,13 +391,11 @@ define <4 x i8> @tv4i8(i1 %c, ptr %p, <4 x i8> %a, <4 x i8> %b) {
; CHECK-GI-NEXT: // %bb.1: // %t
; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b
; CHECK-GI-NEXT: str wzr, [x1]
-; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: zip1 v0.8b, v0.8b, v0.8b
; CHECK-GI-NEXT: ret
; CHECK-GI-NEXT: .LBB12_2:
; CHECK-GI-NEXT: uzp1 v0.8b, v1.8b, v0.8b
-; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: zip1 v0.8b, v0.8b, v0.8b
; CHECK-GI-NEXT: ret
entry:
br i1 %c, label %t, label %e
@@ -501,13 +499,11 @@ define <2 x i16> @tv2i16(i1 %c, ptr %p, <2 x i16> %a, <2 x i16> %b) {
; CHECK-GI-NEXT: // %bb.1: // %t
; CHECK-GI-NEXT: uzp1 v0.4h, v0.4h, v0.4h
; CHECK-GI-NEXT: str wzr, [x1]
-; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: zip1 v0.4h, v0.4h, v0.4h
; CHECK-GI-NEXT: ret
; CHECK-GI-NEXT: .LBB16_2:
; CHECK-GI-NEXT: uzp1 v0.4h, v1.4h, v0.4h
-; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: zip1 v0.4h, v0.4h, v0.4h
; CHECK-GI-NEXT: ret
entry:
br i1 %c, label %t, label %e
diff --git a/llvm/test/CodeGen/AArch64/reduce-and.ll b/llvm/test/CodeGen/AArch64/reduce-and.ll
index 21696cf7325c9..cea7028b322a4 100644
--- a/llvm/test/CodeGen/AArch64/reduce-and.ll
+++ b/llvm/test/CodeGen/AArch64/reduce-and.ll
@@ -294,7 +294,7 @@ define i8 @test_redand_v16i8(<16 x i8> %a) {
;
; CHECK-GI-LABEL: test_redand_v16i8:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-GI-NEXT: umov w8, v0.b[0]
; CHECK-GI-NEXT: umov w9, v0.b[1]
@@ -332,7 +332,7 @@ define i8 @test_redand_v32i8(<32 x i8> %a) {
; CHECK-GI-LABEL: test_redand_v32i8:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
-; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-GI-NEXT: umov w8, v0.b[0]
; CHECK-GI-NEXT: umov w9, v0.b[1]
@@ -391,7 +391,7 @@ define i16 @test_redand_v8i16(<8 x i16> %a) {
;
; CHECK-GI-LABEL: test_redand_v8i16:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-GI-NEXT: umov w8, v0.h[0]
; CHECK-GI-NEXT: umov w9, v0.h[1]
@@ -420,7 +420,7 @@ define i16 @test_redand_v16i16(<16 x i16> %a) {
; CHECK-GI-LABEL: test_redand_v16i16:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
-; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-GI-NEXT: umov w8, v0.h[0]
; CHECK-GI-NEXT: umov w9, v0.h[1]
@@ -465,7 +465,7 @@ define i32 @test_redand_v4i32(<4 x i32> %a) {
;
; CHECK-GI-LABEL: test_redand_v4i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-GI-NEXT: mov w8, v0.s[1]
; CHECK-GI-NEXT: fmov w9, s0
@@ -489,7 +489,7 @@ define i32 @test_redand_v8i32(<8 x i32> %a) {
; CHECK-GI-LABEL: test_redand_v8i32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
-; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-GI-NEXT: mov w8, v0.s[1]
; CHECK-GI-NEXT: fmov w9, s0
diff --git a/llvm/test/CodeGen/AArch64/reduce-or.ll b/llvm/test/CodeGen/AArch64/reduce-or.ll
index c52c5e5d34f1d..71f21f316d9e1 100644
--- a/llvm/test/CodeGen/AArch64/reduce-or.ll
+++ b/llvm/test/CodeGen/AArch64/reduce-or.ll
@@ -295,7 +295,7 @@ define i8 @test_redor_v16i8(<16 x i8> %a) {
;
; CHECK-GI-LABEL: test_redor_v16i8:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-GI-NEXT: umov w8, v0.b[0]
; CHECK-GI-NEXT: umov w9, v0.b[1]
@@ -333,7 +333,7 @@ define i8 @test_redor_v32i8(<32 x i8> %a) {
; CHECK-GI-LABEL: test_redor_v32i8:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
-; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-GI-NEXT: umov w8, v0.b[0]
; CHECK-GI-NEXT: umov w9, v0.b[1]
@@ -392,7 +392,7 @@ define i16 @test_redor_v8i16(<8 x i16> %a) {
;
; CHECK-GI-LABEL: test_redor_v8i16:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-GI-NEXT: umov w8, v0.h[0]
; CHECK-GI-NEXT: umov w9, v0.h[1]
@@ -421,7 +421,7 @@ define i16 @test_redor_v16i16(<16 x i16> %a) {
; CHECK-GI-LABEL: test_redor_v16i16:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
-; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-GI-NEXT: umov w8, v0.h[0]
; CHECK-GI-NEXT: umov w9, v0.h[1]
@@ -466,7 +466,7 @@ define i32 @test_redor_v4i32(<4 x i32> %a) {
;
; CHECK-GI-LABEL: test_redor_v4i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-GI-NEXT: mov w8, v0.s[1]
; CHECK-GI-NEXT: fmov w9, s0
@@ -490,7 +490,7 @@ define i32 @test_redor_v8i32(<8 x i32> %a) {
; CHECK-GI-LABEL: test_redor_v8i32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
-; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
; CHECK-GI-NEXT: mov w8, v0.s[1]
; CHECK-GI-NEXT: fmov w9, s0
diff --git a/llvm/test/CodeGen/AArch64/reduce-xor.ll b/llvm/test/CodeGen/AArch64/reduce-xor.ll
index 50cc845f2756b..39e0d28c81eea 100644
--- a/llvm/test/CodeGen/AArch64/reduce-xor.ll
+++ b/llvm/test/CodeGen/AArch64/reduce-xor.ll
@@ -284,7 +284,7 @@ define i8 @test_redxor_v16i8(<16 x i8> %a) {
;
; CHECK-GI-LABEL: test_redxor_v16i8:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-GI-NEXT: umov w8, v0.b[0]
; CHECK-GI-NEXT: umov w9, v0.b[1]
@@ -322,7 +322,7 @@ define i8 @test_redxor_v32i8(<32 x i8> %a) {
; CHECK-GI-LABEL: test_redxor_v32i8:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: eor v0.16b, v0.16b, v1.16b
-; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-GI-NEXT: umov w8, v0.b[0]
; CHECK-GI-NEXT: umov w9, v0.b[1]
@@ -381,7 +381,7 @@ define i16 @test_redxor_v8i16(<8 x i16> %a) {
;
; CHECK-GI-LABEL: test_redxor_v8i16:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-GI-NEXT: umov w8, v0.h[0]
; CHECK-GI-NEXT: umov w9, v0.h[1]
@@ -410,7 +410,7 @@ define i16 @test_redxor_v16i16(<16 x i16> %a) {
; CHECK-GI-LABEL: test_redxor_v16i16:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: eor v0.16b, v0.16b, v1.16b
-; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-GI-NEXT: umov w8, v0.h[0]
; CHECK-GI-NEXT: umov w9, v0.h[1]
@@ -455,7 +455,7 @@ define i32 @test_redxor_v4i32(<4 x i32> %a) {
;
; CHECK-GI-LABEL: test_redxor_v4i32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-GI-NEXT: mov w8, v0.s[1]
; CHECK-GI-NEXT: fmov w9, s0
@@ -479,7 +479,7 @@ define i32 @test_redxor_v8i32(<8 x i32> %a) {
; CHECK-GI-LABEL: test_redxor_v8i32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: eor v0.16b, v0.16b, v1.16b
-; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: eor v0.8b, v0.8b, v1.8b
; CHECK-GI-NEXT: mov w8, v0.s[1]
; CHECK-GI-NEXT: fmov w9, s0
diff --git a/llvm/test/CodeGen/AArch64/rem-by-const.ll b/llvm/test/CodeGen/AArch64/rem-by-const.ll
index cafdcc7fd5d71..5ec5475ce6c25 100644
--- a/llvm/test/CodeGen/AArch64/rem-by-const.ll
+++ b/llvm/test/CodeGen/AArch64/rem-by-const.ll
@@ -684,6 +684,7 @@ define <2 x i8> @sv2i8_7(<2 x i8> %d, <2 x i8> %e) {
; CHECK-GI-LABEL: sv2i8_7:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: mvni v1.4h, #108
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-GI-NEXT: shl v2.2s, v0.2s, #24
; CHECK-GI-NEXT: movi v3.2s, #7
; CHECK-GI-NEXT: shl v1.4h, v1.4h, #8
@@ -696,8 +697,7 @@ define <2 x i8> @sv2i8_7(<2 x i8> %d, <2 x i8> %e) {
; CHECK-GI-NEXT: mul v1.2s, v2.2s, v1.2s
; CHECK-GI-NEXT: uzp1 v1.4h, v1.4h, v0.4h
; CHECK-GI-NEXT: sshr v1.4h, v1.4h, #8
-; CHECK-GI-NEXT: ushll v1.4s, v1.4h, #0
-; CHECK-GI-NEXT: add v1.2s, v1.2s, v0.2s
+; CHECK-GI-NEXT: uaddw v1.4s, v0.4s, v1.4h
; CHECK-GI-NEXT: mov w8, v1.s[1]
; CHECK-GI-NEXT: mov v1.b[1], w8
; CHECK-GI-NEXT: sshr v1.8b, v1.8b, #2
@@ -712,6 +712,7 @@ define <2 x i8> @sv2i8_7(<2 x i8> %d, <2 x i8> %e) {
; CHECK-GI-NEXT: mov v2.s[1], w11
; CHECK-GI-NEXT: add v1.2s, v1.2s, v2.2s
; CHECK-GI-NEXT: mls v0.2s, v1.2s, v3.2s
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
entry:
%s = srem <2 x i8> %d, <i8 7, i8 7>
@@ -901,9 +902,7 @@ define <4 x i8> @sv4i8_7(<4 x i8> %d, <4 x i8> %e) {
; CHECK-GI-NEXT: uzp1 v1.8b, v2.8b, v0.8b
; CHECK-GI-NEXT: sshr v1.8b, v1.8b, #2
; CHECK-GI-NEXT: ushr v2.8b, v1.8b, #7
-; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #0
-; CHECK-GI-NEXT: ushll v2.8h, v2.8b, #0
-; CHECK-GI-NEXT: add v1.4h, v1.4h, v2.4h
+; CHECK-GI-NEXT: uaddl v1.8h, v1.8b, v2.8b
; CHECK-GI-NEXT: mls v0.4h, v1.4h, v3.4h
; CHECK-GI-NEXT: ret
entry:
@@ -938,9 +937,7 @@ define <4 x i8> @sv4i8_100(<4 x i8> %d, <4 x i8> %e) {
; CHECK-GI-NEXT: uzp1 v1.8b, v1.8b, v0.8b
; CHECK-GI-NEXT: sshr v1.8b, v1.8b, #4
; CHECK-GI-NEXT: ushr v2.8b, v1.8b, #7
-; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #0
-; CHECK-GI-NEXT: ushll v2.8h, v2.8b, #0
-; CHECK-GI-NEXT: add v1.4h, v1.4h, v2.4h
+; CHECK-GI-NEXT: uaddl v1.8h, v1.8b, v2.8b
; CHECK-GI-NEXT: mls v0.4h, v1.4h, v3.4h
; CHECK-GI-NEXT: ret
entry:
@@ -1086,12 +1083,12 @@ define <2 x i8> @uv2i8_7(<2 x i8> %d, <2 x i8> %e) {
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: movi d1, #0x0000ff000000ff
; CHECK-GI-NEXT: movi v2.2s, #37
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-GI-NEXT: and v1.8b, v0.8b, v1.8b
; CHECK-GI-NEXT: mul v1.2s, v1.2s, v2.2s
; CHECK-GI-NEXT: uzp1 v1.4h, v1.4h, v0.4h
; CHECK-GI-NEXT: ushr v1.4h, v1.4h, #8
-; CHECK-GI-NEXT: ushll v1.4s, v1.4h, #0
-; CHECK-GI-NEXT: sub v2.2s, v0.2s, v1.2s
+; CHECK-GI-NEXT: usubw v2.4s, v0.4s, v1.4h
; CHECK-GI-NEXT: mov w8, v2.s[1]
; CHECK-GI-NEXT: mov v2.b[1], w8
; CHECK-GI-NEXT: ushr v2.8b, v2.8b, #1
@@ -1099,7 +1096,7 @@ define <2 x i8> @uv2i8_7(<2 x i8> %d, <2 x i8> %e) {
; CHECK-GI-NEXT: umov w9, v2.b[1]
; CHECK-GI-NEXT: fmov s2, w8
; CHECK-GI-NEXT: mov v2.s[1], w9
-; CHECK-GI-NEXT: add v1.2s, v2.2s, v1.2s
+; CHECK-GI-NEXT: uaddw v1.4s, v2.4s, v1.4h
; CHECK-GI-NEXT: movi v2.2s, #7
; CHECK-GI-NEXT: mov w8, v1.s[1]
; CHECK-GI-NEXT: mov v1.b[1], w8
@@ -1109,6 +1106,7 @@ define <2 x i8> @uv2i8_7(<2 x i8> %d, <2 x i8> %e) {
; CHECK-GI-NEXT: fmov s1, w8
; CHECK-GI-NEXT: mov v1.s[1], w9
; CHECK-GI-NEXT: mls v0.2s, v1.2s, v2.2s
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT: ret
entry:
%s = urem <2 x i8> %d, <i8 7, i8 7>
@@ -1288,16 +1286,15 @@ define <4 x i8> @uv4i8_7(<4 x i8> %d, <4 x i8> %e) {
; CHECK-GI-NEXT: and v1.8b, v0.8b, v1.8b
; CHECK-GI-NEXT: ushll v2.8h, v2.8b, #0
; CHECK-GI-NEXT: mul v1.4h, v1.4h, v2.4h
-; CHECK-GI-NEXT: ushr v2.4h, v1.4h, #8
-; CHECK-GI-NEXT: sub v2.4h, v0.4h, v2.4h
+; CHECK-GI-NEXT: ushr v1.4h, v1.4h, #8
+; CHECK-GI-NEXT: sub v2.4h, v0.4h, v1.4h
; CHECK-GI-NEXT: uzp1 v2.8b, v2.8b, v0.8b
; CHECK-GI-NEXT: ushr v2.8b, v2.8b, #1
-; CHECK-GI-NEXT: ushll v2.8h, v2.8b, #0
-; CHECK-GI-NEXT: usra v2.4h, v1.4h, #8
-; CHECK-GI-NEXT: uzp1 v1.8b, v2.8b, v0.8b
+; CHECK-GI-NEXT: uaddw v1.8h, v1.8h, v2.8b
; CHECK-GI-NEXT: movi v2.4h, #7
+; CHECK-GI-NEXT: uzp1 v1.8b, v1.8b, v0.8b
; CHECK-GI-NEXT: ushr v1.8b, v1.8b, #2
-; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #0
+; CHECK-GI-NEXT: zip1 v1.8b, v1.8b, v1.8b
; CHECK-GI-NEXT: mls v0.4h, v1.4h, v2.4h
; CHECK-GI-NEXT: ret
entry:
@@ -1328,7 +1325,7 @@ define <4 x i8> @uv4i8_100(<4 x i8> %d, <4 x i8> %e) {
; CHECK-GI-NEXT: ushr v1.4h, v1.4h, #8
; CHECK-GI-NEXT: uzp1 v1.8b, v1.8b, v0.8b
; CHECK-GI-NEXT: ushr v1.8b, v1.8b, #4
-; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #0
+; CHECK-GI-NEXT: zip1 v1.8b, v1.8b, v1.8b
; CHECK-GI-NEXT: mls v0.4h, v1.4h, v2.4h
; CHECK-GI-NEXT: ret
entry:
@@ -1456,9 +1453,7 @@ define <2 x i16> @sv2i16_7(<2 x i16> %d, <2 x i16> %e) {
; CHECK-GI-NEXT: uzp1 v1.4h, v1.4h, v0.4h
; CHECK-GI-NEXT: sshr v1.4h, v1.4h, #1
; CHECK-GI-NEXT: ushr v2.4h, v1.4h, #15
-; CHECK-GI-NEXT: ushll v1.4s, v1.4h, #0
-; CHECK-GI-NEXT: ushll v2.4s, v2.4h, #0
-; CHECK-GI-NEXT: add v1.2s, v1.2s, v2.2s
+; CHECK-GI-NEXT: uaddl v1.4s, v1.4h, v2.4h
; CHECK-GI-NEXT: mls v0.2s, v1.2s, v3.2s
; CHECK-GI-NEXT: ret
entry:
@@ -1495,9 +1490,7 @@ define <2 x i16> @sv2i16_100(<2 x i16> %d, <2 x i16> %e) {
; CHECK-GI-NEXT: uzp1 v1.4h, v1.4h, v0.4h
; CHECK-GI-NEXT: sshr v1.4h, v1.4h, #3
; CHECK-GI-NEXT: ushr v2.4h, v1.4h, #15
-; CHECK-GI-NEXT: ushll v1.4s, v1.4h, #0
-; CHECK-GI-NEXT: ushll v2.4s, v2.4h, #0
-; CHECK-GI-NEXT: add v1.2s, v1.2s, v2.2s
+; CHECK-GI-NEXT: uaddl v1.4s, v1.4h, v2.4h
; CHECK-GI-NEXT: mls v0.2s, v1.2s, v3.2s
; CHECK-GI-NEXT: ret
entry:
@@ -1770,16 +1763,15 @@ define <2 x i16> @uv2i16_7(<2 x i16> %d, <2 x i16> %e) {
; CHECK-GI-NEXT: ushll v2.4s, v2.4h, #0
; CHECK-GI-NEXT: and v1.8b, v0.8b, v1.8b
; CHECK-GI-NEXT: mul v1.2s, v1.2s, v2.2s
-; CHECK-GI-NEXT: ushr v2.2s, v1.2s, #16
-; CHECK-GI-NEXT: sub v2.2s, v0.2s, v2.2s
+; CHECK-GI-NEXT: ushr v1.2s, v1.2s, #16
+; CHECK-GI-NEXT: sub v2.2s, v0.2s, v1.2s
; CHECK-GI-NEXT: uzp1 v2.4h, v2.4h, v0.4h
; CHECK-GI-NEXT: ushr v2.4h, v2.4h, #1
-; CHECK-GI-NEXT: ushll v2.4s, v2.4h, #0
-; CHECK-GI-NEXT: usra v2.2s, v1.2s, #16
-; CHECK-GI-NEXT: uzp1 v1.4h, v2.4h, v0.4h
+; CHECK-GI-NEXT: uaddw v1.4s, v1.4s, v2.4h
; CHECK-GI-NEXT: movi v2.2s, #7
+; CHECK-GI-NEXT: uzp1 v1.4h, v1.4h, v0.4h
; CHECK-GI-NEXT: ushr v1.4h, v1.4h, #2
-; CHECK-GI-NEXT: ushll v1.4s, v1.4h, #0
+; CHECK-GI-NEXT: zip1 v1.4h, v1.4h, v1.4h
; CHECK-GI-NEXT: mls v0.2s, v1.2s, v2.2s
; CHECK-GI-NEXT: ret
entry:
@@ -1814,7 +1806,7 @@ define <2 x i16> @uv2i16_100(<2 x i16> %d, <2 x i16> %e) {
; CHECK-GI-NEXT: ushr v1.2s, v1.2s, #16
; CHECK-GI-NEXT: uzp1 v1.4h, v1.4h, v0.4h
; CHECK-GI-NEXT: ushr v1.4h, v1.4h, #1
-; CHECK-GI-NEXT: ushll v1.4s, v1.4h, #0
+; CHECK-GI-NEXT: zip1 v1.4h, v1.4h, v1.4h
; CHECK-GI-NEXT: mls v0.2s, v1.2s, v2.2s
; CHECK-GI-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/AArch64/rem.ll b/llvm/test/CodeGen/AArch64/rem.ll
index 5dc5aa52b9155..32bcd5a697d17 100644
--- a/llvm/test/CodeGen/AArch64/rem.ll
+++ b/llvm/test/CodeGen/AArch64/rem.ll
@@ -1276,7 +1276,7 @@ define <8 x i8> @uv8i8(<8 x i8> %d, <8 x i8> %e) {
; CHECK-GI-NEXT: ushll v0.4s, v2.4h, #0
; CHECK-GI-NEXT: ushll v3.4s, v1.4h, #0
; CHECK-GI-NEXT: ushll2 v2.4s, v2.8h, #0
-; CHECK-GI-NEXT: mov d5, v1.d[1]
+; CHECK-GI-NEXT: ext v5.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: fmov w8, s0
; CHECK-GI-NEXT: fmov w9, s3
; CHECK-GI-NEXT: mov w10, v0.s[1]
@@ -1436,8 +1436,8 @@ define <16 x i8> @uv16i8(<16 x i8> %d, <16 x i8> %e) {
; CHECK-GI-NEXT: ushll v5.4s, v3.4h, #0
; CHECK-GI-NEXT: ushll2 v4.4s, v4.8h, #0
; CHECK-GI-NEXT: ushll v6.4s, v1.4h, #0
-; CHECK-GI-NEXT: mov d18, v3.d[1]
-; CHECK-GI-NEXT: mov d19, v1.d[1]
+; CHECK-GI-NEXT: ext v18.16b, v3.16b, v3.16b, #8
+; CHECK-GI-NEXT: ext v19.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: fmov w8, s2
; CHECK-GI-NEXT: fmov w9, s5
; CHECK-GI-NEXT: mov w12, v2.s[3]
@@ -1860,8 +1860,8 @@ define <32 x i8> @uv32i8(<32 x i8> %d, <32 x i8> %e) {
; CHECK-GI-NEXT: mov v20.h[1], w15
; CHECK-GI-NEXT: ushll v2.8h, v2.8b, #0
; CHECK-GI-NEXT: ushll v7.4s, v4.4h, #0
-; CHECK-GI-NEXT: mov d29, v4.d[1]
-; CHECK-GI-NEXT: mov d28, v2.d[1]
+; CHECK-GI-NEXT: ext v29.16b, v4.16b, v4.16b, #8
+; CHECK-GI-NEXT: ext v28.16b, v2.16b, v2.16b, #8
; CHECK-GI-NEXT: umlsl v26.4s, v19.4h, v2.4h
; CHECK-GI-NEXT: fmov w17, s7
; CHECK-GI-NEXT: udiv w12, w12, w16
@@ -1937,8 +1937,8 @@ define <32 x i8> @uv32i8(<32 x i8> %d, <32 x i8> %e) {
; CHECK-GI-NEXT: mov v23.h[1], w23
; CHECK-GI-NEXT: ushll v3.8h, v3.8b, #0
; CHECK-GI-NEXT: ushll v18.4s, v7.4h, #0
-; CHECK-GI-NEXT: mov d31, v7.d[1]
-; CHECK-GI-NEXT: mov d30, v3.d[1]
+; CHECK-GI-NEXT: ext v31.16b, v7.16b, v7.16b, #8
+; CHECK-GI-NEXT: ext v30.16b, v3.16b, v3.16b, #8
; CHECK-GI-NEXT: umlsl v27.4s, v22.4h, v3.4h
; CHECK-GI-NEXT: fmov w25, s18
; CHECK-GI-NEXT: mov w28, v18.s[3]
@@ -2668,7 +2668,7 @@ define <8 x i16> @uv8i16(<8 x i16> %d, <8 x i16> %e) {
; CHECK-GI-NEXT: ushll v2.4s, v0.4h, #0
; CHECK-GI-NEXT: ushll v3.4s, v1.4h, #0
; CHECK-GI-NEXT: ushll2 v0.4s, v0.8h, #0
-; CHECK-GI-NEXT: mov d5, v1.d[1]
+; CHECK-GI-NEXT: ext v5.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: fmov w8, s2
; CHECK-GI-NEXT: fmov w9, s3
; CHECK-GI-NEXT: mov w10, v2.s[1]
@@ -2851,8 +2851,8 @@ define <16 x i16> @uv16i16(<16 x i16> %d, <16 x i16> %e) {
; CHECK-GI-NEXT: ushll v4.4s, v0.4h, #0
; CHECK-GI-NEXT: ushll v5.4s, v2.4h, #0
; CHECK-GI-NEXT: ushll v6.4s, v3.4h, #0
-; CHECK-GI-NEXT: mov d18, v2.d[1]
-; CHECK-GI-NEXT: mov d19, v3.d[1]
+; CHECK-GI-NEXT: ext v18.16b, v2.16b, v2.16b, #8
+; CHECK-GI-NEXT: ext v19.16b, v3.16b, v3.16b, #8
; CHECK-GI-NEXT: fmov w8, s4
; CHECK-GI-NEXT: fmov w9, s5
; CHECK-GI-NEXT: mov w12, v5.s[3]
diff --git a/llvm/test/CodeGen/AArch64/shift.ll b/llvm/test/CodeGen/AArch64/shift.ll
index 58397602658b6..574afd32eecc0 100644
--- a/llvm/test/CodeGen/AArch64/shift.ll
+++ b/llvm/test/CodeGen/AArch64/shift.ll
@@ -528,8 +528,7 @@ define <4 x i8> @shl_v4i8(<4 x i8> %0, <4 x i8> %1){
; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b
; CHECK-GI-NEXT: uzp1 v1.8b, v1.8b, v0.8b
; CHECK-GI-NEXT: ushl v0.8b, v0.8b, v1.8b
-; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: zip1 v0.8b, v0.8b, v0.8b
; CHECK-GI-NEXT: ret
%3 = shl <4 x i8> %0, %1
ret <4 x i8> %3
@@ -564,8 +563,7 @@ define <2 x i16> @shl_v2i16(<2 x i16> %0, <2 x i16> %1){
; CHECK-GI-NEXT: uzp1 v0.4h, v0.4h, v0.4h
; CHECK-GI-NEXT: uzp1 v1.4h, v1.4h, v0.4h
; CHECK-GI-NEXT: ushl v0.4h, v0.4h, v1.4h
-; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: zip1 v0.4h, v0.4h, v0.4h
; CHECK-GI-NEXT: ret
%3 = shl <2 x i16> %0, %1
ret <2 x i16> %3
@@ -707,8 +705,7 @@ define <4 x i8> @ashr_v4i8(<4 x i8> %0, <4 x i8> %1){
; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b
; CHECK-GI-NEXT: neg v1.8b, v1.8b
; CHECK-GI-NEXT: sshl v0.8b, v0.8b, v1.8b
-; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: zip1 v0.8b, v0.8b, v0.8b
; CHECK-GI-NEXT: ret
%3 = ashr <4 x i8> %0, %1
ret <4 x i8> %3
@@ -743,8 +740,7 @@ define <2 x i16> @ashr_v2i16(<2 x i16> %0, <2 x i16> %1){
; CHECK-GI-NEXT: uzp1 v0.4h, v0.4h, v0.4h
; CHECK-GI-NEXT: neg v1.4h, v1.4h
; CHECK-GI-NEXT: sshl v0.4h, v0.4h, v1.4h
-; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: zip1 v0.4h, v0.4h, v0.4h
; CHECK-GI-NEXT: ret
%3 = ashr <2 x i16> %0, %1
ret <2 x i16> %3
@@ -880,8 +876,7 @@ define <4 x i8> @lshr_v4i8(<4 x i8> %0, <4 x i8> %1){
; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b
; CHECK-GI-NEXT: neg v1.8b, v1.8b
; CHECK-GI-NEXT: ushl v0.8b, v0.8b, v1.8b
-; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: zip1 v0.8b, v0.8b, v0.8b
; CHECK-GI-NEXT: ret
%3 = lshr <4 x i8> %0, %1
ret <4 x i8> %3
@@ -915,8 +910,7 @@ define <2 x i16> @lshr_v2i16(<2 x i16> %0, <2 x i16> %1){
; CHECK-GI-NEXT: uzp1 v0.4h, v0.4h, v0.4h
; CHECK-GI-NEXT: neg v1.4h, v1.4h
; CHECK-GI-NEXT: ushl v0.4h, v0.4h, v1.4h
-; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: zip1 v0.4h, v0.4h, v0.4h
; CHECK-GI-NEXT: ret
%3 = lshr <2 x i16> %0, %1
ret <2 x i16> %3
diff --git a/llvm/test/CodeGen/AArch64/st1-lane.ll b/llvm/test/CodeGen/AArch64/st1-lane.ll
index a210339a3968e..06128df3b934a 100644
--- a/llvm/test/CodeGen/AArch64/st1-lane.ll
+++ b/llvm/test/CodeGen/AArch64/st1-lane.ll
@@ -132,21 +132,13 @@ define ptr @post_v2i64(<2 x i64> %a, ptr %p1, ptr %p2) {
}
define ptr @post_v4i32(<4 x i32> %a, ptr %p1, ptr %p2) {
-; CHECK-SD-LABEL: post_v4i32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-SD-NEXT: str d0, [x0]
-; CHECK-SD-NEXT: str d1, [x1], #8
-; CHECK-SD-NEXT: mov x0, x1
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: post_v4i32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: str d0, [x0]
-; CHECK-GI-NEXT: str d1, [x1], #8
-; CHECK-GI-NEXT: mov x0, x1
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: post_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: str d0, [x0]
+; CHECK-NEXT: str d1, [x1], #8
+; CHECK-NEXT: mov x0, x1
+; CHECK-NEXT: ret
%s1 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 0, i32 1>
store <2 x i32> %s1, ptr %p1, align 8
%s2 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 2, i32 3>
@@ -156,21 +148,13 @@ define ptr @post_v4i32(<4 x i32> %a, ptr %p1, ptr %p2) {
}
define ptr @post_v8i16(<8 x i16> %a, ptr %p1, ptr %p2) {
-; CHECK-SD-LABEL: post_v8i16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-SD-NEXT: str d0, [x0]
-; CHECK-SD-NEXT: str d1, [x1], #8
-; CHECK-SD-NEXT: mov x0, x1
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: post_v8i16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: str d0, [x0]
-; CHECK-GI-NEXT: str d1, [x1], #8
-; CHECK-GI-NEXT: mov x0, x1
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: post_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: str d0, [x0]
+; CHECK-NEXT: str d1, [x1], #8
+; CHECK-NEXT: mov x0, x1
+; CHECK-NEXT: ret
%s1 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
store <4 x i16> %s1, ptr %p1, align 8
%s2 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -180,21 +164,13 @@ define ptr @post_v8i16(<8 x i16> %a, ptr %p1, ptr %p2) {
}
define ptr @post_v16i8(<16 x i8> %a, ptr %p1, ptr %p2) {
-; CHECK-SD-LABEL: post_v16i8:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-SD-NEXT: str d0, [x0]
-; CHECK-SD-NEXT: str d1, [x1], #8
-; CHECK-SD-NEXT: mov x0, x1
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: post_v16i8:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: str d0, [x0]
-; CHECK-GI-NEXT: str d1, [x1], #8
-; CHECK-GI-NEXT: mov x0, x1
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: post_v16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: str d0, [x0]
+; CHECK-NEXT: str d1, [x1], #8
+; CHECK-NEXT: mov x0, x1
+; CHECK-NEXT: ret
%s1 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
store <8 x i8> %s1, ptr %p1, align 8
%s2 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -228,21 +204,13 @@ define ptr @post_v2f64(<2 x double> %a, ptr %p1, ptr %p2) {
}
define ptr @post_v4f32(<4 x float> %a, ptr %p1, ptr %p2) {
-; CHECK-SD-LABEL: post_v4f32:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-SD-NEXT: str d0, [x0]
-; CHECK-SD-NEXT: str d1, [x1], #8
-; CHECK-SD-NEXT: mov x0, x1
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: post_v4f32:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: str d0, [x0]
-; CHECK-GI-NEXT: str d1, [x1], #8
-; CHECK-GI-NEXT: mov x0, x1
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: post_v4f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: str d0, [x0]
+; CHECK-NEXT: str d1, [x1], #8
+; CHECK-NEXT: mov x0, x1
+; CHECK-NEXT: ret
%s1 = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 0, i32 1>
store <2 x float> %s1, ptr %p1, align 8
%s2 = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 2, i32 3>
@@ -252,21 +220,13 @@ define ptr @post_v4f32(<4 x float> %a, ptr %p1, ptr %p2) {
}
define ptr @post_v8f16(<8 x half> %a, ptr %p1, ptr %p2) {
-; CHECK-SD-LABEL: post_v8f16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-SD-NEXT: str d0, [x0]
-; CHECK-SD-NEXT: str d1, [x1], #8
-; CHECK-SD-NEXT: mov x0, x1
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: post_v8f16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: str d0, [x0]
-; CHECK-GI-NEXT: str d1, [x1], #8
-; CHECK-GI-NEXT: mov x0, x1
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: post_v8f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: str d0, [x0]
+; CHECK-NEXT: str d1, [x1], #8
+; CHECK-NEXT: mov x0, x1
+; CHECK-NEXT: ret
%s1 = shufflevector <8 x half> %a, <8 x half> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
store <4 x half> %s1, ptr %p1, align 8
%s2 = shufflevector <8 x half> %a, <8 x half> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -276,21 +236,13 @@ define ptr @post_v8f16(<8 x half> %a, ptr %p1, ptr %p2) {
}
define ptr @post_v8bf16(<8 x bfloat> %a, ptr %p1, ptr %p2) {
-; CHECK-SD-LABEL: post_v8bf16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-SD-NEXT: str d0, [x0]
-; CHECK-SD-NEXT: str d1, [x1], #8
-; CHECK-SD-NEXT: mov x0, x1
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: post_v8bf16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d1, v0.d[1]
-; CHECK-GI-NEXT: str d0, [x0]
-; CHECK-GI-NEXT: str d1, [x1], #8
-; CHECK-GI-NEXT: mov x0, x1
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: post_v8bf16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: str d0, [x0]
+; CHECK-NEXT: str d1, [x1], #8
+; CHECK-NEXT: mov x0, x1
+; CHECK-NEXT: ret
%s1 = shufflevector <8 x bfloat> %a, <8 x bfloat> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
store <4 x bfloat> %s1, ptr %p1, align 8
%s2 = shufflevector <8 x bfloat> %a, <8 x bfloat> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
diff --git a/llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll b/llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
index 0866701c34921..9bd4714667b12 100644
--- a/llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
+++ b/llvm/test/CodeGen/AArch64/vec-combine-compare-to-bitmask.ll
@@ -1005,7 +1005,7 @@ define <2 x i8> @vector_to_vector_cast(<16 x i1> %arg) nounwind {
; CHECK-GI: ; %bb.0:
; CHECK-GI-NEXT: sub sp, sp, #16
; CHECK-GI-NEXT: umov.b w8, v0[1]
-; CHECK-GI-NEXT: mov d1, v0[1]
+; CHECK-GI-NEXT: ext.16b v1, v0, v0, #8
; CHECK-GI-NEXT: umov.b w10, v0[1]
; CHECK-GI-NEXT: umov.b w9, v0[0]
; CHECK-GI-NEXT: umov.b w13, v0[0]
diff --git a/llvm/test/CodeGen/AArch64/vecreduce-fmul.ll b/llvm/test/CodeGen/AArch64/vecreduce-fmul.ll
index dd633ca379941..8a68c90cd2660 100644
--- a/llvm/test/CodeGen/AArch64/vecreduce-fmul.ll
+++ b/llvm/test/CodeGen/AArch64/vecreduce-fmul.ll
@@ -50,7 +50,7 @@ define half @mul_HalfH(<4 x half> %bin.rdx) {
; CHECK-GI-NOFP16-LABEL: mul_HalfH:
; CHECK-GI-NOFP16: // %bb.0:
; CHECK-GI-NOFP16-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-GI-NOFP16-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NOFP16-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-GI-NOFP16-NEXT: fmul v0.2s, v0.2s, v1.2s
; CHECK-GI-NOFP16-NEXT: mov s1, v0.s[1]
; CHECK-GI-NOFP16-NEXT: fmul s0, s0, s1
@@ -98,7 +98,7 @@ define half @mul_H(<8 x half> %bin.rdx) {
; CHECK-GI-NOFP16-NEXT: fcvtl v1.4s, v0.4h
; CHECK-GI-NOFP16-NEXT: fcvtl2 v0.4s, v0.8h
; CHECK-GI-NOFP16-NEXT: fmul v0.4s, v1.4s, v0.4s
-; CHECK-GI-NOFP16-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NOFP16-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-GI-NOFP16-NEXT: fmul v0.2s, v0.2s, v1.2s
; CHECK-GI-NOFP16-NEXT: mov s1, v0.s[1]
; CHECK-GI-NOFP16-NEXT: fmul s0, s0, s1
@@ -107,7 +107,7 @@ define half @mul_H(<8 x half> %bin.rdx) {
;
; CHECK-GI-FP16-LABEL: mul_H:
; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: mov d1, v0.d[1]
+; CHECK-GI-FP16-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-GI-FP16-NEXT: fmul v0.4h, v0.4h, v1.4h
; CHECK-GI-FP16-NEXT: mov h1, v0.h[1]
; CHECK-GI-FP16-NEXT: mov h2, v0.h[2]
@@ -131,7 +131,7 @@ define float @mul_S(<4 x float> %bin.rdx) {
;
; CHECK-GI-LABEL: mul_S:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: fmul v0.2s, v0.2s, v1.2s
; CHECK-GI-NEXT: mov s1, v0.s[1]
; CHECK-GI-NEXT: fmul s0, s0, s1
@@ -188,7 +188,7 @@ define half @mul_2H(<16 x half> %bin.rdx) {
; CHECK-GI-NOFP16-NEXT: fmul v0.4s, v2.4s, v0.4s
; CHECK-GI-NOFP16-NEXT: fmul v1.4s, v3.4s, v1.4s
; CHECK-GI-NOFP16-NEXT: fmul v0.4s, v0.4s, v1.4s
-; CHECK-GI-NOFP16-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NOFP16-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-GI-NOFP16-NEXT: fmul v0.2s, v0.2s, v1.2s
; CHECK-GI-NOFP16-NEXT: mov s1, v0.s[1]
; CHECK-GI-NOFP16-NEXT: fmul s0, s0, s1
@@ -198,7 +198,7 @@ define half @mul_2H(<16 x half> %bin.rdx) {
; CHECK-GI-FP16-LABEL: mul_2H:
; CHECK-GI-FP16: // %bb.0:
; CHECK-GI-FP16-NEXT: fmul v0.8h, v0.8h, v1.8h
-; CHECK-GI-FP16-NEXT: mov d1, v0.d[1]
+; CHECK-GI-FP16-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-GI-FP16-NEXT: fmul v0.4h, v0.4h, v1.4h
; CHECK-GI-FP16-NEXT: mov h1, v0.h[1]
; CHECK-GI-FP16-NEXT: mov h2, v0.h[2]
@@ -224,7 +224,7 @@ define float @mul_2S(<8 x float> %bin.rdx) {
; CHECK-GI-LABEL: mul_2S:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: fmul v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: fmul v0.2s, v0.2s, v1.2s
; CHECK-GI-NEXT: mov s1, v0.s[1]
; CHECK-GI-NEXT: fmul s0, s0, s1
@@ -257,7 +257,7 @@ define float @mul_S_init_42(<4 x float> %bin.rdx) {
;
; CHECK-GI-LABEL: mul_S_init_42:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: ext v1.16b, v0.16b, v0.16b, #8
; CHECK-GI-NEXT: mov w8, #1109917696 // =0x42280000
; CHECK-GI-NEXT: fmul v0.2s, v0.2s, v1.2s
; CHECK-GI-NEXT: mov s1, v0.s[1]
@@ -311,8 +311,8 @@ define half @fmul_reduct_reassoc_v8f16(<8 x half> %a, <8 x half> %b) {
; CHECK-GI-NOFP16-NEXT: fcvtl2 v1.4s, v1.8h
; CHECK-GI-NOFP16-NEXT: fmul v0.4s, v2.4s, v0.4s
; CHECK-GI-NOFP16-NEXT: fmul v1.4s, v3.4s, v1.4s
-; CHECK-GI-NOFP16-NEXT: mov d2, v0.d[1]
-; CHECK-GI-NOFP16-NEXT: mov d3, v1.d[1]
+; CHECK-GI-NOFP16-NEXT: ext v2.16b, v0.16b, v0.16b, #8
+; CHECK-GI-NOFP16-NEXT: ext v3.16b, v1.16b, v1.16b, #8
; CHECK-GI-NOFP16-NEXT: fmul v0.2s, v0.2s, v2.2s
; CHECK-GI-NOFP16-NEXT: fmul v1.2s, v1.2s, v3.2s
; CHECK-GI-NOFP16-NEXT: mov s2, v0.s[1]
@@ -329,8 +329,8 @@ define half @fmul_reduct_reassoc_v8f16(<8 x half> %a, <8 x half> %b) {
;
; CHECK-GI-FP16-LABEL: fmul_reduct_reassoc_v8f16:
; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: mov d2, v0.d[1]
-; CHECK-GI-FP16-NEXT: mov d3, v1.d[1]
+; CHECK-GI-FP16-NEXT: ext v2.16b, v0.16b, v0.16b, #8
+; CHECK-GI-FP16-NEXT: ext v3.16b, v1.16b, v1.16b, #8
; CHECK-GI-FP16-NEXT: fmul v0.4h, v0.4h, v2.4h
; CHECK-GI-FP16-NEXT: fmul v1.4h, v1.4h, v3.4h
; CHECK-GI-FP16-NEXT: mov h2, v0.h[1]
@@ -369,8 +369,8 @@ define float @fmul_reduct_reassoc_v8f32(<8 x float> %a, <8 x float> %b) {
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: fmul v0.4s, v0.4s, v1.4s
; CHECK-GI-NEXT: fmul v1.4s, v2.4s, v3.4s
-; CHECK-GI-NEXT: mov d2, v0.d[1]
-; CHECK-GI-NEXT: mov d3, v1.d[1]
+; CHECK-GI-NEXT: ext v2.16b, v0.16b, v0.16b, #8
+; CHECK-GI-NEXT: ext v3.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: fmul v0.2s, v0.2s, v2.2s
; CHECK-GI-NEXT: fmul v1.2s, v1.2s, v3.2s
; CHECK-GI-NEXT: mov s2, v0.s[1]
@@ -397,8 +397,8 @@ define float @fmul_reduct_reassoc_v4f32(<4 x float> %a, <4 x float> %b) {
;
; CHECK-GI-LABEL: fmul_reduct_reassoc_v4f32:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d2, v0.d[1]
-; CHECK-GI-NEXT: mov d3, v1.d[1]
+; CHECK-GI-NEXT: ext v2.16b, v0.16b, v0.16b, #8
+; CHECK-GI-NEXT: ext v3.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: fmul v0.2s, v0.2s, v2.2s
; CHECK-GI-NEXT: fmul v1.2s, v1.2s, v3.2s
; CHECK-GI-NEXT: mov s2, v0.s[1]
@@ -428,9 +428,9 @@ define float @fmul_reduct_reassoc_v4f32_init(float %i, <4 x float> %a, <4 x floa
;
; CHECK-GI-LABEL: fmul_reduct_reassoc_v4f32_init:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d3, v1.d[1]
+; CHECK-GI-NEXT: ext v3.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: fmul v1.2s, v1.2s, v3.2s
-; CHECK-GI-NEXT: mov d3, v2.d[1]
+; CHECK-GI-NEXT: ext v3.16b, v2.16b, v2.16b, #8
; CHECK-GI-NEXT: mov s4, v1.s[1]
; CHECK-GI-NEXT: fmul v2.2s, v2.2s, v3.2s
; CHECK-GI-NEXT: fmul s1, s1, s4
@@ -459,8 +459,8 @@ define float @fmul_reduct_reassoc_v4v8f32(<4 x float> %a, <8 x float> %b) {
; CHECK-GI-LABEL: fmul_reduct_reassoc_v4v8f32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: fmul v1.4s, v1.4s, v2.4s
-; CHECK-GI-NEXT: mov d2, v0.d[1]
-; CHECK-GI-NEXT: mov d3, v1.d[1]
+; CHECK-GI-NEXT: ext v2.16b, v0.16b, v0.16b, #8
+; CHECK-GI-NEXT: ext v3.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: fmul v0.2s, v0.2s, v2.2s
; CHECK-GI-NEXT: fmul v1.2s, v1.2s, v3.2s
; CHECK-GI-NEXT: mov s2, v0.s[1]
@@ -513,8 +513,8 @@ define float @fmul_reduct_reassoc_v4f32_extrause(<4 x float> %a, <4 x float> %b)
;
; CHECK-GI-LABEL: fmul_reduct_reassoc_v4f32_extrause:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: mov d2, v0.d[1]
-; CHECK-GI-NEXT: mov d3, v1.d[1]
+; CHECK-GI-NEXT: ext v2.16b, v0.16b, v0.16b, #8
+; CHECK-GI-NEXT: ext v3.16b, v1.16b, v1.16b, #8
; CHECK-GI-NEXT: fmul v0.2s, v0.2s, v2.2s
; CHECK-GI-NEXT: fmul v1.2s, v1.2s, v3.2s
; CHECK-GI-NEXT: mov s2, v0.s[1]
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