[llvm] 6f5570c - [AMDGPU][NFC] Autogenerate check lines for llvm.amdgcn.rsq.clamp.ll and llvm.amdgcn.rsq.ll (#195867)
via llvm-commits
llvm-commits at lists.llvm.org
Tue May 5 09:03:48 PDT 2026
Author: anjenner
Date: 2026-05-05T17:03:43+01:00
New Revision: 6f5570caa3a32df7e60c3c8ff3a69e41a4cd4466
URL: https://github.com/llvm/llvm-project/commit/6f5570caa3a32df7e60c3c8ff3a69e41a4cd4466
DIFF: https://github.com/llvm/llvm-project/commit/6f5570caa3a32df7e60c3c8ff3a69e41a4cd4466.diff
LOG: [AMDGPU][NFC] Autogenerate check lines for llvm.amdgcn.rsq.clamp.ll and llvm.amdgcn.rsq.ll (#195867)
Added:
Modified:
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.clamp.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.clamp.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.clamp.ll
index e879fb2c399f0..0b0cf45b02f3e 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.clamp.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.clamp.ll
@@ -1,44 +1,81 @@
-; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=VI -check-prefix=FUNC %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=VI %s
declare float @llvm.amdgcn.rsq.clamp.f32(float) #1
declare double @llvm.amdgcn.rsq.clamp.f64(double) #1
-; FUNC-LABEL: {{^}}rsq_clamp_f32:
-; SI: v_rsq_clamp_f32_e32
-
-; VI: s_load_dword [[SRC:s[0-9]+]]
-; VI-DAG: v_rsq_f32_e32 [[RSQ:v[0-9]+]], [[SRC]]
-; VI-DAG: v_min_f32_e32 [[MIN:v[0-9]+]], 0x7f7fffff, [[RSQ]]
-; VI: v_max_f32_e32 [[RESULT:v[0-9]+]], 0xff7fffff, [[MIN]]
-; VI: buffer_store_dword [[RESULT]]
define amdgpu_kernel void @rsq_clamp_f32(ptr addrspace(1) %out, float %src) #0 {
+; SI-LABEL: rsq_clamp_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dword s6, s[4:5], 0xb
+; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_rsq_clamp_f32_e32 v0, s6
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: rsq_clamp_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dword s0, s[4:5], 0x2c
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_rsq_f32_e32 v0, s0
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-NEXT: v_min_f32_e32 v0, 0x7f7fffff, v0
+; VI-NEXT: v_max_f32_e32 v2, 0xff7fffff, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_endpgm
%rsq_clamp = call float @llvm.amdgcn.rsq.clamp.f32(float %src)
store float %rsq_clamp, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}rsq_clamp_f64:
-; SI: v_rsq_clamp_f64_e32
-
-; TODO: this constant should be folded:
-; VI-DAG: s_mov_b32 [[NEG1:s[0-9]+]], -1
-; VI-DAG: s_mov_b32 s[[LOW1:[0-9]+]], [[NEG1]]
-; VI-DAG: s_mov_b32 s[[HIGH1:[0-9]+]], 0x7fefffff
-; VI-DAG: s_mov_b32 s[[HIGH2:[0-9]+]], 0xffefffff
-; VI-DAG: v_rsq_f64_e32 [[RSQ:v\[[0-9]+:[0-9]+\]]], s[{{[0-9]+:[0-9]+}}
-; VI-DAG: v_min_f64 v[0:1], [[RSQ]], s[[[LOW1]]:[[HIGH1]]]
-; VI-DAG: v_max_f64 v[0:1], v[0:1], s[[[LOW1]]:[[HIGH2]]]
define amdgpu_kernel void @rsq_clamp_f64(ptr addrspace(1) %out, double %src) #0 {
+; SI-LABEL: rsq_clamp_f64:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_mov_b32 s4, s0
+; SI-NEXT: s_mov_b32 s5, s1
+; SI-NEXT: v_rsq_clamp_f64_e32 v[0:1], s[2:3]
+; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: rsq_clamp_f64:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_rsq_f64_e32 v[0:1], s[2:3]
+; VI-NEXT: s_mov_b32 s3, 0x7fefffff
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: v_mov_b32_e32 v2, s0
+; VI-NEXT: v_mov_b32_e32 v3, s1
+; VI-NEXT: v_min_f64 v[0:1], v[0:1], s[2:3]
+; VI-NEXT: s_mov_b32 s3, 0xffefffff
+; VI-NEXT: v_max_f64 v[0:1], v[0:1], s[2:3]
+; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; VI-NEXT: s_endpgm
%rsq_clamp = call double @llvm.amdgcn.rsq.clamp.f64(double %src)
store double %rsq_clamp, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}rsq_clamp_undef_f32:
-; SI-NOT: v_rsq_clamp_f32
define amdgpu_kernel void @rsq_clamp_undef_f32(ptr addrspace(1) %out) #0 {
+; SI-LABEL: rsq_clamp_undef_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: rsq_clamp_undef_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_endpgm
%rsq_clamp = call float @llvm.amdgcn.rsq.clamp.f32(float poison)
store float %rsq_clamp, ptr addrspace(1) %out
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.ll
index f99fe71ac6a4d..1224953d15268 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.ll
@@ -1,62 +1,174 @@
-; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=VI %s
declare float @llvm.amdgcn.rsq.f32(float) #0
declare double @llvm.amdgcn.rsq.f64(double) #0
-; FUNC-LABEL: {{^}}rsq_f32:
-; SI: v_rsq_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}
define amdgpu_kernel void @rsq_f32(ptr addrspace(1) %out, float %src) #1 {
+; SI-LABEL: rsq_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dword s6, s[4:5], 0xb
+; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: v_rsq_f32_e32 v0, s6
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: rsq_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_rsq_f32_e32 v2, s2
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_endpgm
%rsq = call float @llvm.amdgcn.rsq.f32(float %src) #0
store float %rsq, ptr addrspace(1) %out, align 4
ret void
}
; TODO: Really these should be constant folded
-; FUNC-LABEL: {{^}}rsq_f32_constant_4.0
-; SI: v_rsq_f32_e32 {{v[0-9]+}}, 4.0
define amdgpu_kernel void @rsq_f32_constant_4.0(ptr addrspace(1) %out) #1 {
+; SI-LABEL: rsq_f32_constant_4.0:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: v_rsq_f32_e32 v0, 4.0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: rsq_f32_constant_4.0:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-NEXT: v_rsq_f32_e32 v2, 4.0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_endpgm
%rsq = call float @llvm.amdgcn.rsq.f32(float 4.0) #0
store float %rsq, ptr addrspace(1) %out, align 4
ret void
}
-; FUNC-LABEL: {{^}}rsq_f32_constant_100.0
-; SI: v_rsq_f32_e32 {{v[0-9]+}}, 0x42c80000
define amdgpu_kernel void @rsq_f32_constant_100.0(ptr addrspace(1) %out) #1 {
+; SI-LABEL: rsq_f32_constant_100.0:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: v_rsq_f32_e32 v0, 0x42c80000
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: rsq_f32_constant_100.0:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-NEXT: v_rsq_f32_e32 v2, 0x42c80000
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: flat_store_dword v[0:1], v2
+; VI-NEXT: s_endpgm
%rsq = call float @llvm.amdgcn.rsq.f32(float 100.0) #0
store float %rsq, ptr addrspace(1) %out, align 4
ret void
}
-; FUNC-LABEL: {{^}}rsq_f64:
-; SI: v_rsq_f64_e32 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
define amdgpu_kernel void @rsq_f64(ptr addrspace(1) %out, double %src) #1 {
+; SI-LABEL: rsq_f64:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_mov_b32 s4, s0
+; SI-NEXT: s_mov_b32 s5, s1
+; SI-NEXT: v_rsq_f64_e32 v[0:1], s[2:3]
+; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: rsq_f64:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_rsq_f64_e32 v[0:1], s[2:3]
+; VI-NEXT: v_mov_b32_e32 v2, s0
+; VI-NEXT: v_mov_b32_e32 v3, s1
+; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; VI-NEXT: s_endpgm
%rsq = call double @llvm.amdgcn.rsq.f64(double %src) #0
store double %rsq, ptr addrspace(1) %out, align 4
ret void
}
; TODO: Really these should be constant folded
-; FUNC-LABEL: {{^}}rsq_f64_constant_4.0
-; SI: v_rsq_f64_e32 {{v\[[0-9]+:[0-9]+\]}}, 4.0
define amdgpu_kernel void @rsq_f64_constant_4.0(ptr addrspace(1) %out) #1 {
+; SI-LABEL: rsq_f64_constant_4.0:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: v_rsq_f64_e32 v[0:1], 4.0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: rsq_f64_constant_4.0:
+; VI: ; %bb.0:
+; VI-NEXT: v_rsq_f64_e32 v[0:1], 4.0
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v3, s1
+; VI-NEXT: v_mov_b32_e32 v2, s0
+; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; VI-NEXT: s_endpgm
%rsq = call double @llvm.amdgcn.rsq.f64(double 4.0) #0
store double %rsq, ptr addrspace(1) %out, align 4
ret void
}
-; FUNC-LABEL: {{^}}rsq_f64_constant_100.0
-; SI: v_rsq_f64_e32 {{v\[[0-9]+:[0-9]+\]}}, 0x40590000
define amdgpu_kernel void @rsq_f64_constant_100.0(ptr addrspace(1) %out) #1 {
+; SI-LABEL: rsq_f64_constant_100.0:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: v_rsq_f64_e32 v[0:1], 0x40590000
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: rsq_f64_constant_100.0:
+; VI: ; %bb.0:
+; VI-NEXT: v_rsq_f64_e32 v[0:1], 0x40590000
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v3, s1
+; VI-NEXT: v_mov_b32_e32 v2, s0
+; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; VI-NEXT: s_endpgm
%rsq = call double @llvm.amdgcn.rsq.f64(double 100.0) #0
store double %rsq, ptr addrspace(1) %out, align 4
ret void
}
-; FUNC-LABEL: {{^}}rsq_undef_f32:
-; SI-NOT: v_rsq_f32
define amdgpu_kernel void @rsq_undef_f32(ptr addrspace(1) %out) #1 {
+; SI-LABEL: rsq_undef_f32:
+; SI: ; %bb.0:
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: rsq_undef_f32:
+; VI: ; %bb.0:
+; VI-NEXT: s_endpgm
%rsq = call float @llvm.amdgcn.rsq.f32(float poison)
store float %rsq, ptr addrspace(1) %out, align 4
ret void
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