[llvm] [AArch64][llvm] Redefine some insns as an alias of `SYS` (PR #187004)

[Kerry McLaughlin via llvm-commits]

================
@@ -919,18 +919,56 @@ bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
   bool OptionalReg = false;
   std::string Ins;
   std::string Name;
+  StringRef RegSep = ", ";
 
   if (CnVal == 7) {
     switch (CmVal) {
-    default:
-      return false;
+    default: return false;
+    // MLBI aliases
+    case 0: {
+      const AArch64MLBI::MLBI *MLBI =
+          AArch64MLBI::lookupMLBIByEncoding(Encoding);
+      if (!MLBI || !MLBI->haveFeatures(STI.getFeatureBits()))
+        return false;
+
+      NeedsReg = MLBI->NeedsReg;
+      Ins = "mlbi\t";
+      Name = std::string(MLBI->Name);
+    } break;
     // Maybe IC, maybe Prediction Restriction
     case 1:
       switch (Op1Val) {
       default: return false;
       case 0: goto Search_IC;
       case 3: goto Search_PRCTX;
       }
+    // BRB aliases.
+    case 2: {
+      if (Op1Val == 1) {
+        if (!(STI.hasFeature(AArch64::FeatureAll) ||
+              STI.hasFeature(AArch64::FeatureBRBE)))
+          return false;
+
+        NeedsReg = false;
+        if (Op2Val == 4) {
+          Ins = "brb\t";
+          Name = "iall";
+        } else if (Op2Val == 5) {
+          Ins = "brb\t";
+          Name = "inj";
+        } else {
+          return false;
+        }
+      } else if (Op1Val == 3) {
+        if (Op2Val != 7 || !(STI.hasFeature(AArch64::FeatureAll) ||
+                             STI.hasFeature(AArch64::FeatureITE)))
+          return false;
+
+        return false;
----------------
kmclaughlin-arm wrote:

I'm not sure what the `Op1Val == 3` case is for, it looks like it's always returning false?

https://github.com/llvm/llvm-project/pull/187004