[llvm] [CodeGen] Precompute untyped getMinimalPhysRegClass (PR #193438)

[Cullen Rhodes via llvm-commits]

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@@ -1718,6 +1722,38 @@ void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, raw_ostream &MainOS,
     }
   }
 
+  if (!RegisterClasses.empty()) {
+    assert(RegisterClasses.size() < UINT16_MAX &&
+           "Too many minimal register classes");
+
+    OS << "\n// Register to minimal register class mapping\n\n";
+    OS << "const TargetRegisterClass *" << ClassName
+       << "::getDefaultMinimalPhysRegClass(MCRegister Reg)" << " const {\n";
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c-rhodes wrote:

getMinimalPhysRegClass takes a value type but this only support the common MVT::Other case. From a compile-time perspective i dont expect supporting other VTs will give any benefit on AArch64, not sure about other platforms.

https://github.com/llvm/llvm-project/pull/193438