[llvm] [AArch64][ISel] Use v2i64 [S|U][MIN|MAX] reductions for fixed-width SVE (PR #195806)
Harry Ramsey via llvm-commits
llvm-commits at lists.llvm.org
Tue May 5 01:54:53 PDT 2026
https://github.com/Harry-Ramsey updated https://github.com/llvm/llvm-project/pull/195806
>From 2a421616612c197f8a0f93c88bd647fb7f3af1fb Mon Sep 17 00:00:00 2001
From: Harry Ramsey <harry.ramsey at arm.com>
Date: Thu, 30 Apr 2026 13:24:04 +0000
Subject: [PATCH 1/2] [AArch64][ISel] Use v2i64 [S|U][MIN|MAX] reductions for
fixed-width SVE
This commit enables SVE reductions for [S|U][MIN|MAX] on v2i64 data
types where no equivalent NEON instruction exists.
---
.../Target/AArch64/AArch64ISelLowering.cpp | 26 ++++++++++++++-----
1 file changed, 19 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index f5082b779d1db..8ddb28f080d8d 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1935,13 +1935,13 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
setOperationAction(ISD::MUL, MVT::v1i64, Custom);
setOperationAction(ISD::MUL, MVT::v2i64, Custom);
+ // NEON doesn't support 128-bit [s|u][min|max] operations.
+ // With SVE we can try lowering these to predicated operations (e.g. smaxv).
// With SVE2 we can try lowering these to pairwise operations (e.g. smaxp).
- if (Subtarget->hasSVE2() || Subtarget->isStreamingSVEAvailable()) {
- setOperationAction(ISD::VECREDUCE_SMAX, MVT::v2i64, Custom);
- setOperationAction(ISD::VECREDUCE_SMIN, MVT::v2i64, Custom);
- setOperationAction(ISD::VECREDUCE_UMAX, MVT::v2i64, Custom);
- setOperationAction(ISD::VECREDUCE_UMIN, MVT::v2i64, Custom);
- }
+ setOperationAction(ISD::VECREDUCE_SMAX, MVT::v2i64, Custom);
+ setOperationAction(ISD::VECREDUCE_SMIN, MVT::v2i64, Custom);
+ setOperationAction(ISD::VECREDUCE_UMAX, MVT::v2i64, Custom);
+ setOperationAction(ISD::VECREDUCE_UMIN, MVT::v2i64, Custom);
// NOTE: Currently this has to happen after computeRegisterProperties rather
// than the preferred option of combining it with the addRegisterClass call.
@@ -32150,14 +32150,26 @@ bool AArch64TargetLowering::shouldLowerReductionToSVE(
bool UseSVE = useSVEForFixedLengthVectorVT(
SrcVT, OverrideNEON && Subtarget->useSVEForFixedLengthVectors());
+ bool IsI64MinMaxReduction =
+ SrcVT == MVT::v2i64 && (RdxOp.getOpcode() == ISD::VECREDUCE_SMIN ||
+ RdxOp.getOpcode() == ISD::VECREDUCE_SMAX ||
+ RdxOp.getOpcode() == ISD::VECREDUCE_UMIN ||
+ RdxOp.getOpcode() == ISD::VECREDUCE_UMAX);
+
// Always lower v2i64 vectors to pairwise SVE2 operations when possible as
// NEON does not natively support reductions on v2i64. Lower v2i32 to pairwise
// SVE2 operations when UseSVE is true, as the pairwise ops are likely to be
// cheaper than a full reduction.
- if (Subtarget->hasSVE2() || Subtarget->isStreamingSVEAvailable())
+ //
+ // If SVE2 is not supported, we can lower certain operations to predicated SVE
+ // operations.
+ if (Subtarget->hasSVE2() || Subtarget->isStreamingSVEAvailable()) {
if (SrcVT == MVT::v2i64 || (UseSVE && SrcVT == MVT::v2i32))
if ((PairwiseOpIID = getPairwiseOpForReduction(RdxOp.getOpcode())))
UseSVE = true;
+ } else if (Subtarget->hasSVE() && IsI64MinMaxReduction) {
+ UseSVE = true;
+ }
return UseSVE;
}
>From af3277b561c470b43b43c20d4a42e1a59faa8cfb Mon Sep 17 00:00:00 2001
From: Harry Ramsey <harry.ramsey at arm.com>
Date: Tue, 5 May 2026 08:54:22 +0000
Subject: [PATCH 2/2] fixup! [AArch64][ISel] Use v2i64 [S|U][MIN|MAX]
reductions for fixed-width SVE
---
llvm/test/CodeGen/AArch64/v2i64-min-max.ll | 42 +++++++++++++++++++++-
1 file changed, 41 insertions(+), 1 deletion(-)
diff --git a/llvm/test/CodeGen/AArch64/v2i64-min-max.ll b/llvm/test/CodeGen/AArch64/v2i64-min-max.ll
index 88c5e98cbdbe5..2c861e94d4ac1 100644
--- a/llvm/test/CodeGen/AArch64/v2i64-min-max.ll
+++ b/llvm/test/CodeGen/AArch64/v2i64-min-max.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64 -mattr=+sve2 | FileCheck %s -check-prefixes=CHECK-SVE2
-; RUN: llc < %s -mtriple=aarch64 -mattr=+sve | FileCheck %s -check-prefixes=CHECK
+; RUN: llc < %s -mtriple=aarch64 -mattr=+sve | FileCheck %s -check-prefixes=CHECK-SVE
; RUN: llc < %s -mtriple=aarch64 | FileCheck %s -check-prefixes=CHECK
define i64 @smax(<2 x i64> %0) {
@@ -12,6 +12,14 @@ define i64 @smax(<2 x i64> %0) {
; CHECK-SVE2-NEXT: fmov x0, d0
; CHECK-SVE2-NEXT: ret
;
+; CHECK-SVE-LABEL: smax:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.d, vl2
+; CHECK-SVE-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-SVE-NEXT: smaxv d0, p0, z0.d
+; CHECK-SVE-NEXT: fmov x0, d0
+; CHECK-SVE-NEXT: ret
+;
; CHECK-LABEL: smax:
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, v0.d[1]
@@ -34,6 +42,14 @@ define i64 @umax(<2 x i64> %0) {
; CHECK-SVE2-NEXT: fmov x0, d0
; CHECK-SVE2-NEXT: ret
;
+; CHECK-SVE-LABEL: umax:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.d, vl2
+; CHECK-SVE-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-SVE-NEXT: umaxv d0, p0, z0.d
+; CHECK-SVE-NEXT: fmov x0, d0
+; CHECK-SVE-NEXT: ret
+;
; CHECK-LABEL: umax:
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, v0.d[1]
@@ -56,6 +72,14 @@ define i64 @smin(<2 x i64> %0) {
; CHECK-SVE2-NEXT: fmov x0, d0
; CHECK-SVE2-NEXT: ret
;
+; CHECK-SVE-LABEL: smin:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.d, vl2
+; CHECK-SVE-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-SVE-NEXT: sminv d0, p0, z0.d
+; CHECK-SVE-NEXT: fmov x0, d0
+; CHECK-SVE-NEXT: ret
+;
; CHECK-LABEL: smin:
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, v0.d[1]
@@ -78,6 +102,14 @@ define i64 @umin(<2 x i64> %0) {
; CHECK-SVE2-NEXT: fmov x0, d0
; CHECK-SVE2-NEXT: ret
;
+; CHECK-SVE-LABEL: umin:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: ptrue p0.d, vl2
+; CHECK-SVE-NEXT: // kill: def $q0 killed $q0 def $z0
+; CHECK-SVE-NEXT: uminv d0, p0, z0.d
+; CHECK-SVE-NEXT: fmov x0, d0
+; CHECK-SVE-NEXT: ret
+;
; CHECK-LABEL: umin:
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, v0.d[1]
@@ -100,6 +132,14 @@ define i64 @umin_different_vectors(<2 x i64> %0, <2 x i64> %1) {
; CHECK-SVE2-NEXT: csel x0, x9, x8, lo
; CHECK-SVE2-NEXT: ret
;
+; CHECK-SVE-LABEL: umin_different_vectors:
+; CHECK-SVE: // %bb.0:
+; CHECK-SVE-NEXT: mov x8, v1.d[1]
+; CHECK-SVE-NEXT: fmov x9, d0
+; CHECK-SVE-NEXT: cmp x9, x8
+; CHECK-SVE-NEXT: csel x0, x9, x8, lo
+; CHECK-SVE-NEXT: ret
+;
; CHECK-LABEL: umin_different_vectors:
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, v1.d[1]
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