[llvm] [AArch64][GlobalISel] Add gisel test coverage for addp-shuffles.ll. NFC (PR #195803)
David Green via llvm-commits
llvm-commits at lists.llvm.org
Tue May 5 00:05:59 PDT 2026
https://github.com/davemgreen created https://github.com/llvm/llvm-project/pull/195803
None
>From 25064955065bff881ca66c31c8cb4e8e7d300030 Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Tue, 5 May 2026 08:05:48 +0100
Subject: [PATCH] [AArch64][GlobalISel] Add gisel test coverage for
addp-shuffles.ll. NFC
---
llvm/test/CodeGen/AArch64/addp-shuffle.ll | 557 +++++++++++++++++-----
1 file changed, 445 insertions(+), 112 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/addp-shuffle.ll b/llvm/test/CodeGen/AArch64/addp-shuffle.ll
index 1f313e7ca1e7e..e71d23921785c 100644
--- a/llvm/test/CodeGen/AArch64/addp-shuffle.ll
+++ b/llvm/test/CodeGen/AArch64/addp-shuffle.ll
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-NOFP16
-; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-NOFP16,CHECK-NOFP16-SD
+; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16,CHECK-FP16-SD
+; RUN: llc < %s -mtriple=aarch64 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-NOFP16,CHECK-NOFP16-GI
+; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-FP16,CHECK-FP16-GI
define <4 x i32> @deinterleave_shuffle_v8i32(<8 x i32> %a) {
; CHECK-LABEL: deinterleave_shuffle_v8i32:
@@ -25,11 +27,31 @@ define <4 x i32> @deinterleave_shuffle_v8i32_c(<8 x i32> %a) {
}
define <2 x i32> @deinterleave_shuffle_v4i32(<4 x i32> %a) {
-; CHECK-LABEL: deinterleave_shuffle_v4i32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: addp v0.4s, v0.4s, v0.4s
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT: ret
+; CHECK-NOFP16-SD-LABEL: deinterleave_shuffle_v4i32:
+; CHECK-NOFP16-SD: // %bb.0:
+; CHECK-NOFP16-SD-NEXT: addp v0.4s, v0.4s, v0.4s
+; CHECK-NOFP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NOFP16-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: deinterleave_shuffle_v4i32:
+; CHECK-FP16-SD: // %bb.0:
+; CHECK-FP16-SD-NEXT: addp v0.4s, v0.4s, v0.4s
+; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-NOFP16-GI-LABEL: deinterleave_shuffle_v4i32:
+; CHECK-NOFP16-GI: // %bb.0:
+; CHECK-NOFP16-GI-NEXT: uzp1 v1.4s, v0.4s, v0.4s
+; CHECK-NOFP16-GI-NEXT: uzp2 v0.4s, v0.4s, v0.4s
+; CHECK-NOFP16-GI-NEXT: add v0.2s, v1.2s, v0.2s
+; CHECK-NOFP16-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: deinterleave_shuffle_v4i32:
+; CHECK-FP16-GI: // %bb.0:
+; CHECK-FP16-GI-NEXT: uzp1 v1.4s, v0.4s, v0.4s
+; CHECK-FP16-GI-NEXT: uzp2 v0.4s, v0.4s, v0.4s
+; CHECK-FP16-GI-NEXT: add v0.2s, v1.2s, v0.2s
+; CHECK-FP16-GI-NEXT: ret
%r0 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 0, i32 2>
%r1 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 1, i32 3>
%o = add <2 x i32> %r0, %r1
@@ -48,11 +70,31 @@ define <8 x i16> @deinterleave_shuffle_v16i16(<16 x i16> %a) {
}
define <4 x i16> @deinterleave_shuffle_v8i16(<8 x i16> %a) {
-; CHECK-LABEL: deinterleave_shuffle_v8i16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: addp v0.8h, v0.8h, v0.8h
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT: ret
+; CHECK-NOFP16-SD-LABEL: deinterleave_shuffle_v8i16:
+; CHECK-NOFP16-SD: // %bb.0:
+; CHECK-NOFP16-SD-NEXT: addp v0.8h, v0.8h, v0.8h
+; CHECK-NOFP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NOFP16-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: deinterleave_shuffle_v8i16:
+; CHECK-FP16-SD: // %bb.0:
+; CHECK-FP16-SD-NEXT: addp v0.8h, v0.8h, v0.8h
+; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-NOFP16-GI-LABEL: deinterleave_shuffle_v8i16:
+; CHECK-NOFP16-GI: // %bb.0:
+; CHECK-NOFP16-GI-NEXT: uzp1 v1.8h, v0.8h, v0.8h
+; CHECK-NOFP16-GI-NEXT: uzp2 v0.8h, v0.8h, v0.8h
+; CHECK-NOFP16-GI-NEXT: add v0.4h, v1.4h, v0.4h
+; CHECK-NOFP16-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: deinterleave_shuffle_v8i16:
+; CHECK-FP16-GI: // %bb.0:
+; CHECK-FP16-GI-NEXT: uzp1 v1.8h, v0.8h, v0.8h
+; CHECK-FP16-GI-NEXT: uzp2 v0.8h, v0.8h, v0.8h
+; CHECK-FP16-GI-NEXT: add v0.4h, v1.4h, v0.4h
+; CHECK-FP16-GI-NEXT: ret
%r0 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%r1 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%o = add <4 x i16> %r0, %r1
@@ -71,11 +113,31 @@ define <16 x i8> @deinterleave_shuffle_v32i8(<32 x i8> %a) {
}
define <8 x i8> @deinterleave_shuffle_v16i8(<16 x i8> %a) {
-; CHECK-LABEL: deinterleave_shuffle_v16i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: addp v0.16b, v0.16b, v0.16b
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT: ret
+; CHECK-NOFP16-SD-LABEL: deinterleave_shuffle_v16i8:
+; CHECK-NOFP16-SD: // %bb.0:
+; CHECK-NOFP16-SD-NEXT: addp v0.16b, v0.16b, v0.16b
+; CHECK-NOFP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NOFP16-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: deinterleave_shuffle_v16i8:
+; CHECK-FP16-SD: // %bb.0:
+; CHECK-FP16-SD-NEXT: addp v0.16b, v0.16b, v0.16b
+; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-NOFP16-GI-LABEL: deinterleave_shuffle_v16i8:
+; CHECK-NOFP16-GI: // %bb.0:
+; CHECK-NOFP16-GI-NEXT: uzp1 v1.16b, v0.16b, v0.16b
+; CHECK-NOFP16-GI-NEXT: uzp2 v0.16b, v0.16b, v0.16b
+; CHECK-NOFP16-GI-NEXT: add v0.8b, v1.8b, v0.8b
+; CHECK-NOFP16-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: deinterleave_shuffle_v16i8:
+; CHECK-FP16-GI: // %bb.0:
+; CHECK-FP16-GI-NEXT: uzp1 v1.16b, v0.16b, v0.16b
+; CHECK-FP16-GI-NEXT: uzp2 v0.16b, v0.16b, v0.16b
+; CHECK-FP16-GI-NEXT: add v0.8b, v1.8b, v0.8b
+; CHECK-FP16-GI-NEXT: ret
%r0 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%r1 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%o = add <8 x i8> %r0, %r1
@@ -83,12 +145,31 @@ define <8 x i8> @deinterleave_shuffle_v16i8(<16 x i8> %a) {
}
define <4 x i64> @deinterleave_shuffle_v8i64(<8 x i64> %a) {
-; CHECK-LABEL: deinterleave_shuffle_v8i64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: addp v2.2d, v2.2d, v3.2d
-; CHECK-NEXT: addp v0.2d, v0.2d, v1.2d
-; CHECK-NEXT: mov v1.16b, v2.16b
-; CHECK-NEXT: ret
+; CHECK-NOFP16-SD-LABEL: deinterleave_shuffle_v8i64:
+; CHECK-NOFP16-SD: // %bb.0:
+; CHECK-NOFP16-SD-NEXT: addp v2.2d, v2.2d, v3.2d
+; CHECK-NOFP16-SD-NEXT: addp v0.2d, v0.2d, v1.2d
+; CHECK-NOFP16-SD-NEXT: mov v1.16b, v2.16b
+; CHECK-NOFP16-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: deinterleave_shuffle_v8i64:
+; CHECK-FP16-SD: // %bb.0:
+; CHECK-FP16-SD-NEXT: addp v2.2d, v2.2d, v3.2d
+; CHECK-FP16-SD-NEXT: addp v0.2d, v0.2d, v1.2d
+; CHECK-FP16-SD-NEXT: mov v1.16b, v2.16b
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-NOFP16-GI-LABEL: deinterleave_shuffle_v8i64:
+; CHECK-NOFP16-GI: // %bb.0:
+; CHECK-NOFP16-GI-NEXT: addp v0.2d, v0.2d, v1.2d
+; CHECK-NOFP16-GI-NEXT: addp v1.2d, v2.2d, v3.2d
+; CHECK-NOFP16-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: deinterleave_shuffle_v8i64:
+; CHECK-FP16-GI: // %bb.0:
+; CHECK-FP16-GI-NEXT: addp v0.2d, v0.2d, v1.2d
+; CHECK-FP16-GI-NEXT: addp v1.2d, v2.2d, v3.2d
+; CHECK-FP16-GI-NEXT: ret
%r0 = shufflevector <8 x i64> %a, <8 x i64> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%r1 = shufflevector <8 x i64> %a, <8 x i64> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%o = add <4 x i64> %r0, %r1
@@ -118,24 +199,38 @@ define <4 x float> @deinterleave_shuffle_v8f32_c(<8 x float> %a) {
}
define <8 x half> @deinterleave_shuffle_v16f16(<16 x half> %a) {
-; CHECK-NOFP16-LABEL: deinterleave_shuffle_v16f16:
-; CHECK-NOFP16: // %bb.0:
-; CHECK-NOFP16-NEXT: uzp1 v2.8h, v0.8h, v1.8h
-; CHECK-NOFP16-NEXT: uzp2 v0.8h, v0.8h, v1.8h
-; CHECK-NOFP16-NEXT: fcvtl v1.4s, v0.4h
-; CHECK-NOFP16-NEXT: fcvtl v3.4s, v2.4h
-; CHECK-NOFP16-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-NOFP16-NEXT: fcvtl2 v2.4s, v2.8h
-; CHECK-NOFP16-NEXT: fadd v1.4s, v3.4s, v1.4s
-; CHECK-NOFP16-NEXT: fadd v2.4s, v2.4s, v0.4s
-; CHECK-NOFP16-NEXT: fcvtn v0.4h, v1.4s
-; CHECK-NOFP16-NEXT: fcvtn2 v0.8h, v2.4s
-; CHECK-NOFP16-NEXT: ret
+; CHECK-NOFP16-SD-LABEL: deinterleave_shuffle_v16f16:
+; CHECK-NOFP16-SD: // %bb.0:
+; CHECK-NOFP16-SD-NEXT: uzp1 v2.8h, v0.8h, v1.8h
+; CHECK-NOFP16-SD-NEXT: uzp2 v0.8h, v0.8h, v1.8h
+; CHECK-NOFP16-SD-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-NOFP16-SD-NEXT: fcvtl v3.4s, v2.4h
+; CHECK-NOFP16-SD-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-NOFP16-SD-NEXT: fcvtl2 v2.4s, v2.8h
+; CHECK-NOFP16-SD-NEXT: fadd v1.4s, v3.4s, v1.4s
+; CHECK-NOFP16-SD-NEXT: fadd v2.4s, v2.4s, v0.4s
+; CHECK-NOFP16-SD-NEXT: fcvtn v0.4h, v1.4s
+; CHECK-NOFP16-SD-NEXT: fcvtn2 v0.8h, v2.4s
+; CHECK-NOFP16-SD-NEXT: ret
;
; CHECK-FP16-LABEL: deinterleave_shuffle_v16f16:
; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: faddp v0.8h, v0.8h, v1.8h
; CHECK-FP16-NEXT: ret
+;
+; CHECK-NOFP16-GI-LABEL: deinterleave_shuffle_v16f16:
+; CHECK-NOFP16-GI: // %bb.0:
+; CHECK-NOFP16-GI-NEXT: uzp1 v2.8h, v0.8h, v1.8h
+; CHECK-NOFP16-GI-NEXT: uzp2 v0.8h, v0.8h, v1.8h
+; CHECK-NOFP16-GI-NEXT: fcvtl v1.4s, v2.4h
+; CHECK-NOFP16-GI-NEXT: fcvtl v3.4s, v0.4h
+; CHECK-NOFP16-GI-NEXT: fcvtl2 v2.4s, v2.8h
+; CHECK-NOFP16-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-NOFP16-GI-NEXT: fadd v1.4s, v1.4s, v3.4s
+; CHECK-NOFP16-GI-NEXT: fadd v2.4s, v2.4s, v0.4s
+; CHECK-NOFP16-GI-NEXT: fcvtn v0.4h, v1.4s
+; CHECK-NOFP16-GI-NEXT: fcvtn2 v0.8h, v2.4s
+; CHECK-NOFP16-GI-NEXT: ret
%r0 = shufflevector <16 x half> %a, <16 x half> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%r1 = shufflevector <16 x half> %a, <16 x half> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%o = fadd <8 x half> %r0, %r1
@@ -143,12 +238,31 @@ define <8 x half> @deinterleave_shuffle_v16f16(<16 x half> %a) {
}
define <4 x double> @deinterleave_shuffle_v8f64(<8 x double> %a) {
-; CHECK-LABEL: deinterleave_shuffle_v8f64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: faddp v2.2d, v2.2d, v3.2d
-; CHECK-NEXT: faddp v0.2d, v0.2d, v1.2d
-; CHECK-NEXT: mov v1.16b, v2.16b
-; CHECK-NEXT: ret
+; CHECK-NOFP16-SD-LABEL: deinterleave_shuffle_v8f64:
+; CHECK-NOFP16-SD: // %bb.0:
+; CHECK-NOFP16-SD-NEXT: faddp v2.2d, v2.2d, v3.2d
+; CHECK-NOFP16-SD-NEXT: faddp v0.2d, v0.2d, v1.2d
+; CHECK-NOFP16-SD-NEXT: mov v1.16b, v2.16b
+; CHECK-NOFP16-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: deinterleave_shuffle_v8f64:
+; CHECK-FP16-SD: // %bb.0:
+; CHECK-FP16-SD-NEXT: faddp v2.2d, v2.2d, v3.2d
+; CHECK-FP16-SD-NEXT: faddp v0.2d, v0.2d, v1.2d
+; CHECK-FP16-SD-NEXT: mov v1.16b, v2.16b
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-NOFP16-GI-LABEL: deinterleave_shuffle_v8f64:
+; CHECK-NOFP16-GI: // %bb.0:
+; CHECK-NOFP16-GI-NEXT: faddp v0.2d, v0.2d, v1.2d
+; CHECK-NOFP16-GI-NEXT: faddp v1.2d, v2.2d, v3.2d
+; CHECK-NOFP16-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: deinterleave_shuffle_v8f64:
+; CHECK-FP16-GI: // %bb.0:
+; CHECK-FP16-GI-NEXT: faddp v0.2d, v0.2d, v1.2d
+; CHECK-FP16-GI-NEXT: faddp v1.2d, v2.2d, v3.2d
+; CHECK-FP16-GI-NEXT: ret
%r0 = shufflevector <8 x double> %a, <8 x double> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%r1 = shufflevector <8 x double> %a, <8 x double> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%o = fadd <4 x double> %r0, %r1
@@ -156,19 +270,61 @@ define <4 x double> @deinterleave_shuffle_v8f64(<8 x double> %a) {
}
define <4 x i32> @udot(<4 x i32> %z, <16 x i8> %a, <16 x i8> %b) {
-; CHECK-LABEL: udot:
-; CHECK: // %bb.0:
-; CHECK-NEXT: umull v3.8h, v1.8b, v2.8b
-; CHECK-NEXT: umull2 v1.8h, v1.16b, v2.16b
-; CHECK-NEXT: ushll2 v2.4s, v3.8h, #0
-; CHECK-NEXT: ushll v3.4s, v3.4h, #0
-; CHECK-NEXT: ushll2 v4.4s, v1.8h, #0
-; CHECK-NEXT: ushll v1.4s, v1.4h, #0
-; CHECK-NEXT: addp v2.4s, v3.4s, v2.4s
-; CHECK-NEXT: addp v1.4s, v1.4s, v4.4s
-; CHECK-NEXT: addp v1.4s, v2.4s, v1.4s
-; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
-; CHECK-NEXT: ret
+; CHECK-NOFP16-SD-LABEL: udot:
+; CHECK-NOFP16-SD: // %bb.0:
+; CHECK-NOFP16-SD-NEXT: umull v3.8h, v1.8b, v2.8b
+; CHECK-NOFP16-SD-NEXT: umull2 v1.8h, v1.16b, v2.16b
+; CHECK-NOFP16-SD-NEXT: ushll2 v2.4s, v3.8h, #0
+; CHECK-NOFP16-SD-NEXT: ushll v3.4s, v3.4h, #0
+; CHECK-NOFP16-SD-NEXT: ushll2 v4.4s, v1.8h, #0
+; CHECK-NOFP16-SD-NEXT: ushll v1.4s, v1.4h, #0
+; CHECK-NOFP16-SD-NEXT: addp v2.4s, v3.4s, v2.4s
+; CHECK-NOFP16-SD-NEXT: addp v1.4s, v1.4s, v4.4s
+; CHECK-NOFP16-SD-NEXT: addp v1.4s, v2.4s, v1.4s
+; CHECK-NOFP16-SD-NEXT: add v0.4s, v0.4s, v1.4s
+; CHECK-NOFP16-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: udot:
+; CHECK-FP16-SD: // %bb.0:
+; CHECK-FP16-SD-NEXT: umull v3.8h, v1.8b, v2.8b
+; CHECK-FP16-SD-NEXT: umull2 v1.8h, v1.16b, v2.16b
+; CHECK-FP16-SD-NEXT: ushll2 v2.4s, v3.8h, #0
+; CHECK-FP16-SD-NEXT: ushll v3.4s, v3.4h, #0
+; CHECK-FP16-SD-NEXT: ushll2 v4.4s, v1.8h, #0
+; CHECK-FP16-SD-NEXT: ushll v1.4s, v1.4h, #0
+; CHECK-FP16-SD-NEXT: addp v2.4s, v3.4s, v2.4s
+; CHECK-FP16-SD-NEXT: addp v1.4s, v1.4s, v4.4s
+; CHECK-FP16-SD-NEXT: addp v1.4s, v2.4s, v1.4s
+; CHECK-FP16-SD-NEXT: add v0.4s, v0.4s, v1.4s
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-NOFP16-GI-LABEL: udot:
+; CHECK-NOFP16-GI: // %bb.0:
+; CHECK-NOFP16-GI-NEXT: umull v3.8h, v1.8b, v2.8b
+; CHECK-NOFP16-GI-NEXT: umull2 v1.8h, v1.16b, v2.16b
+; CHECK-NOFP16-GI-NEXT: ushll v2.4s, v3.4h, #0
+; CHECK-NOFP16-GI-NEXT: ushll2 v3.4s, v3.8h, #0
+; CHECK-NOFP16-GI-NEXT: ushll v4.4s, v1.4h, #0
+; CHECK-NOFP16-GI-NEXT: ushll2 v1.4s, v1.8h, #0
+; CHECK-NOFP16-GI-NEXT: addp v2.4s, v2.4s, v3.4s
+; CHECK-NOFP16-GI-NEXT: addp v1.4s, v4.4s, v1.4s
+; CHECK-NOFP16-GI-NEXT: addp v1.4s, v2.4s, v1.4s
+; CHECK-NOFP16-GI-NEXT: add v0.4s, v0.4s, v1.4s
+; CHECK-NOFP16-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: udot:
+; CHECK-FP16-GI: // %bb.0:
+; CHECK-FP16-GI-NEXT: umull v3.8h, v1.8b, v2.8b
+; CHECK-FP16-GI-NEXT: umull2 v1.8h, v1.16b, v2.16b
+; CHECK-FP16-GI-NEXT: ushll v2.4s, v3.4h, #0
+; CHECK-FP16-GI-NEXT: ushll2 v3.4s, v3.8h, #0
+; CHECK-FP16-GI-NEXT: ushll v4.4s, v1.4h, #0
+; CHECK-FP16-GI-NEXT: ushll2 v1.4s, v1.8h, #0
+; CHECK-FP16-GI-NEXT: addp v2.4s, v2.4s, v3.4s
+; CHECK-FP16-GI-NEXT: addp v1.4s, v4.4s, v1.4s
+; CHECK-FP16-GI-NEXT: addp v1.4s, v2.4s, v1.4s
+; CHECK-FP16-GI-NEXT: add v0.4s, v0.4s, v1.4s
+; CHECK-FP16-GI-NEXT: ret
%za = zext <16 x i8> %a to <16 x i32>
%zb = zext <16 x i8> %b to <16 x i32>
%m = mul <16 x i32> %za, %zb
@@ -183,19 +339,61 @@ define <4 x i32> @udot(<4 x i32> %z, <16 x i8> %a, <16 x i8> %b) {
}
define <4 x i32> @sdot(<4 x i32> %z, <16 x i8> %a, <16 x i8> %b) {
-; CHECK-LABEL: sdot:
-; CHECK: // %bb.0:
-; CHECK-NEXT: smull v3.8h, v1.8b, v2.8b
-; CHECK-NEXT: smull2 v1.8h, v1.16b, v2.16b
-; CHECK-NEXT: sshll2 v2.4s, v3.8h, #0
-; CHECK-NEXT: sshll v3.4s, v3.4h, #0
-; CHECK-NEXT: sshll2 v4.4s, v1.8h, #0
-; CHECK-NEXT: sshll v1.4s, v1.4h, #0
-; CHECK-NEXT: addp v2.4s, v3.4s, v2.4s
-; CHECK-NEXT: addp v1.4s, v1.4s, v4.4s
-; CHECK-NEXT: addp v1.4s, v2.4s, v1.4s
-; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
-; CHECK-NEXT: ret
+; CHECK-NOFP16-SD-LABEL: sdot:
+; CHECK-NOFP16-SD: // %bb.0:
+; CHECK-NOFP16-SD-NEXT: smull v3.8h, v1.8b, v2.8b
+; CHECK-NOFP16-SD-NEXT: smull2 v1.8h, v1.16b, v2.16b
+; CHECK-NOFP16-SD-NEXT: sshll2 v2.4s, v3.8h, #0
+; CHECK-NOFP16-SD-NEXT: sshll v3.4s, v3.4h, #0
+; CHECK-NOFP16-SD-NEXT: sshll2 v4.4s, v1.8h, #0
+; CHECK-NOFP16-SD-NEXT: sshll v1.4s, v1.4h, #0
+; CHECK-NOFP16-SD-NEXT: addp v2.4s, v3.4s, v2.4s
+; CHECK-NOFP16-SD-NEXT: addp v1.4s, v1.4s, v4.4s
+; CHECK-NOFP16-SD-NEXT: addp v1.4s, v2.4s, v1.4s
+; CHECK-NOFP16-SD-NEXT: add v0.4s, v0.4s, v1.4s
+; CHECK-NOFP16-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: sdot:
+; CHECK-FP16-SD: // %bb.0:
+; CHECK-FP16-SD-NEXT: smull v3.8h, v1.8b, v2.8b
+; CHECK-FP16-SD-NEXT: smull2 v1.8h, v1.16b, v2.16b
+; CHECK-FP16-SD-NEXT: sshll2 v2.4s, v3.8h, #0
+; CHECK-FP16-SD-NEXT: sshll v3.4s, v3.4h, #0
+; CHECK-FP16-SD-NEXT: sshll2 v4.4s, v1.8h, #0
+; CHECK-FP16-SD-NEXT: sshll v1.4s, v1.4h, #0
+; CHECK-FP16-SD-NEXT: addp v2.4s, v3.4s, v2.4s
+; CHECK-FP16-SD-NEXT: addp v1.4s, v1.4s, v4.4s
+; CHECK-FP16-SD-NEXT: addp v1.4s, v2.4s, v1.4s
+; CHECK-FP16-SD-NEXT: add v0.4s, v0.4s, v1.4s
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-NOFP16-GI-LABEL: sdot:
+; CHECK-NOFP16-GI: // %bb.0:
+; CHECK-NOFP16-GI-NEXT: smull v3.8h, v1.8b, v2.8b
+; CHECK-NOFP16-GI-NEXT: smull2 v1.8h, v1.16b, v2.16b
+; CHECK-NOFP16-GI-NEXT: sshll v2.4s, v3.4h, #0
+; CHECK-NOFP16-GI-NEXT: sshll2 v3.4s, v3.8h, #0
+; CHECK-NOFP16-GI-NEXT: sshll v4.4s, v1.4h, #0
+; CHECK-NOFP16-GI-NEXT: sshll2 v1.4s, v1.8h, #0
+; CHECK-NOFP16-GI-NEXT: addp v2.4s, v2.4s, v3.4s
+; CHECK-NOFP16-GI-NEXT: addp v1.4s, v4.4s, v1.4s
+; CHECK-NOFP16-GI-NEXT: addp v1.4s, v2.4s, v1.4s
+; CHECK-NOFP16-GI-NEXT: add v0.4s, v0.4s, v1.4s
+; CHECK-NOFP16-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: sdot:
+; CHECK-FP16-GI: // %bb.0:
+; CHECK-FP16-GI-NEXT: smull v3.8h, v1.8b, v2.8b
+; CHECK-FP16-GI-NEXT: smull2 v1.8h, v1.16b, v2.16b
+; CHECK-FP16-GI-NEXT: sshll v2.4s, v3.4h, #0
+; CHECK-FP16-GI-NEXT: sshll2 v3.4s, v3.8h, #0
+; CHECK-FP16-GI-NEXT: sshll v4.4s, v1.4h, #0
+; CHECK-FP16-GI-NEXT: sshll2 v1.4s, v1.8h, #0
+; CHECK-FP16-GI-NEXT: addp v2.4s, v2.4s, v3.4s
+; CHECK-FP16-GI-NEXT: addp v1.4s, v4.4s, v1.4s
+; CHECK-FP16-GI-NEXT: addp v1.4s, v2.4s, v1.4s
+; CHECK-FP16-GI-NEXT: add v0.4s, v0.4s, v1.4s
+; CHECK-FP16-GI-NEXT: ret
%za = sext <16 x i8> %a to <16 x i32>
%zb = sext <16 x i8> %b to <16 x i32>
%m = mul <16 x i32> %za, %zb
@@ -294,24 +492,38 @@ start:
}
define <8 x half> @manual_faddp_v8f16(<8 x half> %a, <8 x half> %b) {
-; CHECK-NOFP16-LABEL: manual_faddp_v8f16:
-; CHECK-NOFP16: // %bb.0: // %start
-; CHECK-NOFP16-NEXT: uzp1 v2.8h, v0.8h, v1.8h
-; CHECK-NOFP16-NEXT: uzp2 v0.8h, v0.8h, v1.8h
-; CHECK-NOFP16-NEXT: fcvtl v1.4s, v0.4h
-; CHECK-NOFP16-NEXT: fcvtl v3.4s, v2.4h
-; CHECK-NOFP16-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-NOFP16-NEXT: fcvtl2 v2.4s, v2.8h
-; CHECK-NOFP16-NEXT: fadd v1.4s, v3.4s, v1.4s
-; CHECK-NOFP16-NEXT: fadd v2.4s, v2.4s, v0.4s
-; CHECK-NOFP16-NEXT: fcvtn v0.4h, v1.4s
-; CHECK-NOFP16-NEXT: fcvtn2 v0.8h, v2.4s
-; CHECK-NOFP16-NEXT: ret
+; CHECK-NOFP16-SD-LABEL: manual_faddp_v8f16:
+; CHECK-NOFP16-SD: // %bb.0: // %start
+; CHECK-NOFP16-SD-NEXT: uzp1 v2.8h, v0.8h, v1.8h
+; CHECK-NOFP16-SD-NEXT: uzp2 v0.8h, v0.8h, v1.8h
+; CHECK-NOFP16-SD-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-NOFP16-SD-NEXT: fcvtl v3.4s, v2.4h
+; CHECK-NOFP16-SD-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-NOFP16-SD-NEXT: fcvtl2 v2.4s, v2.8h
+; CHECK-NOFP16-SD-NEXT: fadd v1.4s, v3.4s, v1.4s
+; CHECK-NOFP16-SD-NEXT: fadd v2.4s, v2.4s, v0.4s
+; CHECK-NOFP16-SD-NEXT: fcvtn v0.4h, v1.4s
+; CHECK-NOFP16-SD-NEXT: fcvtn2 v0.8h, v2.4s
+; CHECK-NOFP16-SD-NEXT: ret
;
; CHECK-FP16-LABEL: manual_faddp_v8f16:
; CHECK-FP16: // %bb.0: // %start
; CHECK-FP16-NEXT: faddp v0.8h, v0.8h, v1.8h
; CHECK-FP16-NEXT: ret
+;
+; CHECK-NOFP16-GI-LABEL: manual_faddp_v8f16:
+; CHECK-NOFP16-GI: // %bb.0: // %start
+; CHECK-NOFP16-GI-NEXT: uzp1 v2.8h, v0.8h, v1.8h
+; CHECK-NOFP16-GI-NEXT: uzp2 v0.8h, v0.8h, v1.8h
+; CHECK-NOFP16-GI-NEXT: fcvtl v1.4s, v2.4h
+; CHECK-NOFP16-GI-NEXT: fcvtl v3.4s, v0.4h
+; CHECK-NOFP16-GI-NEXT: fcvtl2 v2.4s, v2.8h
+; CHECK-NOFP16-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-NOFP16-GI-NEXT: fadd v1.4s, v1.4s, v3.4s
+; CHECK-NOFP16-GI-NEXT: fadd v2.4s, v2.4s, v0.4s
+; CHECK-NOFP16-GI-NEXT: fcvtn v0.4h, v1.4s
+; CHECK-NOFP16-GI-NEXT: fcvtn2 v0.8h, v2.4s
+; CHECK-NOFP16-GI-NEXT: ret
start:
%0 = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%1 = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
@@ -332,11 +544,31 @@ start:
}
define i64 @addp_2xi64(<2 x i64> %a) {
-; CHECK-LABEL: addp_2xi64:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: addp d0, v0.2d
-; CHECK-NEXT: fmov x0, d0
-; CHECK-NEXT: ret
+; CHECK-NOFP16-SD-LABEL: addp_2xi64:
+; CHECK-NOFP16-SD: // %bb.0: // %entry
+; CHECK-NOFP16-SD-NEXT: addp d0, v0.2d
+; CHECK-NOFP16-SD-NEXT: fmov x0, d0
+; CHECK-NOFP16-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: addp_2xi64:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: addp d0, v0.2d
+; CHECK-FP16-SD-NEXT: fmov x0, d0
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-NOFP16-GI-LABEL: addp_2xi64:
+; CHECK-NOFP16-GI: // %bb.0: // %entry
+; CHECK-NOFP16-GI-NEXT: dup v1.2d, v0.d[1]
+; CHECK-NOFP16-GI-NEXT: add v0.2d, v0.2d, v1.2d
+; CHECK-NOFP16-GI-NEXT: fmov x0, d0
+; CHECK-NOFP16-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: addp_2xi64:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: dup v1.2d, v0.d[1]
+; CHECK-FP16-GI-NEXT: add v0.2d, v0.2d, v1.2d
+; CHECK-FP16-GI-NEXT: fmov x0, d0
+; CHECK-FP16-GI-NEXT: ret
entry:
%shift = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> <i32 1, i32 undef>
%0 = add <2 x i64> %a, %shift
@@ -345,11 +577,31 @@ entry:
}
define i64 @addp_2xi64_commute(<2 x i64> %a) {
-; CHECK-LABEL: addp_2xi64_commute:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: addp d0, v0.2d
-; CHECK-NEXT: fmov x0, d0
-; CHECK-NEXT: ret
+; CHECK-NOFP16-SD-LABEL: addp_2xi64_commute:
+; CHECK-NOFP16-SD: // %bb.0: // %entry
+; CHECK-NOFP16-SD-NEXT: addp d0, v0.2d
+; CHECK-NOFP16-SD-NEXT: fmov x0, d0
+; CHECK-NOFP16-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: addp_2xi64_commute:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: addp d0, v0.2d
+; CHECK-FP16-SD-NEXT: fmov x0, d0
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-NOFP16-GI-LABEL: addp_2xi64_commute:
+; CHECK-NOFP16-GI: // %bb.0: // %entry
+; CHECK-NOFP16-GI-NEXT: dup v1.2d, v0.d[1]
+; CHECK-NOFP16-GI-NEXT: add v0.2d, v1.2d, v0.2d
+; CHECK-NOFP16-GI-NEXT: fmov x0, d0
+; CHECK-NOFP16-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: addp_2xi64_commute:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: dup v1.2d, v0.d[1]
+; CHECK-FP16-GI-NEXT: add v0.2d, v1.2d, v0.2d
+; CHECK-FP16-GI-NEXT: fmov x0, d0
+; CHECK-FP16-GI-NEXT: ret
entry:
%shift = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> <i32 1, i32 undef>
%0 = add <2 x i64> %shift, %a
@@ -381,11 +633,31 @@ define <4 x i32> @or_deinterleave_shuffle_v8i32_c(<8 x i32> %a) {
}
define <2 x i32> @or_deinterleave_shuffle_v4i32(<4 x i32> %a) {
-; CHECK-LABEL: or_deinterleave_shuffle_v4i32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: addp v0.4s, v0.4s, v0.4s
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT: ret
+; CHECK-NOFP16-SD-LABEL: or_deinterleave_shuffle_v4i32:
+; CHECK-NOFP16-SD: // %bb.0:
+; CHECK-NOFP16-SD-NEXT: addp v0.4s, v0.4s, v0.4s
+; CHECK-NOFP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NOFP16-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: or_deinterleave_shuffle_v4i32:
+; CHECK-FP16-SD: // %bb.0:
+; CHECK-FP16-SD-NEXT: addp v0.4s, v0.4s, v0.4s
+; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-NOFP16-GI-LABEL: or_deinterleave_shuffle_v4i32:
+; CHECK-NOFP16-GI: // %bb.0:
+; CHECK-NOFP16-GI-NEXT: uzp1 v1.4s, v0.4s, v0.4s
+; CHECK-NOFP16-GI-NEXT: uzp2 v0.4s, v0.4s, v0.4s
+; CHECK-NOFP16-GI-NEXT: orr v0.8b, v1.8b, v0.8b
+; CHECK-NOFP16-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: or_deinterleave_shuffle_v4i32:
+; CHECK-FP16-GI: // %bb.0:
+; CHECK-FP16-GI-NEXT: uzp1 v1.4s, v0.4s, v0.4s
+; CHECK-FP16-GI-NEXT: uzp2 v0.4s, v0.4s, v0.4s
+; CHECK-FP16-GI-NEXT: orr v0.8b, v1.8b, v0.8b
+; CHECK-FP16-GI-NEXT: ret
%r0 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 0, i32 2>
%r1 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 1, i32 3>
%o = or disjoint <2 x i32> %r0, %r1
@@ -404,11 +676,31 @@ define <8 x i16> @or_deinterleave_shuffle_v16i16(<16 x i16> %a) {
}
define <4 x i16> @or_deinterleave_shuffle_v8i16(<8 x i16> %a) {
-; CHECK-LABEL: or_deinterleave_shuffle_v8i16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: addp v0.8h, v0.8h, v0.8h
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT: ret
+; CHECK-NOFP16-SD-LABEL: or_deinterleave_shuffle_v8i16:
+; CHECK-NOFP16-SD: // %bb.0:
+; CHECK-NOFP16-SD-NEXT: addp v0.8h, v0.8h, v0.8h
+; CHECK-NOFP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NOFP16-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: or_deinterleave_shuffle_v8i16:
+; CHECK-FP16-SD: // %bb.0:
+; CHECK-FP16-SD-NEXT: addp v0.8h, v0.8h, v0.8h
+; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-NOFP16-GI-LABEL: or_deinterleave_shuffle_v8i16:
+; CHECK-NOFP16-GI: // %bb.0:
+; CHECK-NOFP16-GI-NEXT: uzp1 v1.8h, v0.8h, v0.8h
+; CHECK-NOFP16-GI-NEXT: uzp2 v0.8h, v0.8h, v0.8h
+; CHECK-NOFP16-GI-NEXT: orr v0.8b, v1.8b, v0.8b
+; CHECK-NOFP16-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: or_deinterleave_shuffle_v8i16:
+; CHECK-FP16-GI: // %bb.0:
+; CHECK-FP16-GI-NEXT: uzp1 v1.8h, v0.8h, v0.8h
+; CHECK-FP16-GI-NEXT: uzp2 v0.8h, v0.8h, v0.8h
+; CHECK-FP16-GI-NEXT: orr v0.8b, v1.8b, v0.8b
+; CHECK-FP16-GI-NEXT: ret
%r0 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%r1 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%o = or disjoint <4 x i16> %r0, %r1
@@ -427,11 +719,31 @@ define <16 x i8> @or_deinterleave_shuffle_v32i8(<32 x i8> %a) {
}
define <8 x i8> @or_deinterleave_shuffle_v16i8(<16 x i8> %a) {
-; CHECK-LABEL: or_deinterleave_shuffle_v16i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: addp v0.16b, v0.16b, v0.16b
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT: ret
+; CHECK-NOFP16-SD-LABEL: or_deinterleave_shuffle_v16i8:
+; CHECK-NOFP16-SD: // %bb.0:
+; CHECK-NOFP16-SD-NEXT: addp v0.16b, v0.16b, v0.16b
+; CHECK-NOFP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NOFP16-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: or_deinterleave_shuffle_v16i8:
+; CHECK-FP16-SD: // %bb.0:
+; CHECK-FP16-SD-NEXT: addp v0.16b, v0.16b, v0.16b
+; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-NOFP16-GI-LABEL: or_deinterleave_shuffle_v16i8:
+; CHECK-NOFP16-GI: // %bb.0:
+; CHECK-NOFP16-GI-NEXT: uzp1 v1.16b, v0.16b, v0.16b
+; CHECK-NOFP16-GI-NEXT: uzp2 v0.16b, v0.16b, v0.16b
+; CHECK-NOFP16-GI-NEXT: orr v0.8b, v1.8b, v0.8b
+; CHECK-NOFP16-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: or_deinterleave_shuffle_v16i8:
+; CHECK-FP16-GI: // %bb.0:
+; CHECK-FP16-GI-NEXT: uzp1 v1.16b, v0.16b, v0.16b
+; CHECK-FP16-GI-NEXT: uzp2 v0.16b, v0.16b, v0.16b
+; CHECK-FP16-GI-NEXT: orr v0.8b, v1.8b, v0.8b
+; CHECK-FP16-GI-NEXT: ret
%r0 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%r1 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%o = or disjoint <8 x i8> %r0, %r1
@@ -439,12 +751,31 @@ define <8 x i8> @or_deinterleave_shuffle_v16i8(<16 x i8> %a) {
}
define <4 x i64> @or_deinterleave_shuffle_v8i64(<8 x i64> %a) {
-; CHECK-LABEL: or_deinterleave_shuffle_v8i64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: addp v2.2d, v2.2d, v3.2d
-; CHECK-NEXT: addp v0.2d, v0.2d, v1.2d
-; CHECK-NEXT: mov v1.16b, v2.16b
-; CHECK-NEXT: ret
+; CHECK-NOFP16-SD-LABEL: or_deinterleave_shuffle_v8i64:
+; CHECK-NOFP16-SD: // %bb.0:
+; CHECK-NOFP16-SD-NEXT: addp v2.2d, v2.2d, v3.2d
+; CHECK-NOFP16-SD-NEXT: addp v0.2d, v0.2d, v1.2d
+; CHECK-NOFP16-SD-NEXT: mov v1.16b, v2.16b
+; CHECK-NOFP16-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: or_deinterleave_shuffle_v8i64:
+; CHECK-FP16-SD: // %bb.0:
+; CHECK-FP16-SD-NEXT: addp v2.2d, v2.2d, v3.2d
+; CHECK-FP16-SD-NEXT: addp v0.2d, v0.2d, v1.2d
+; CHECK-FP16-SD-NEXT: mov v1.16b, v2.16b
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-NOFP16-GI-LABEL: or_deinterleave_shuffle_v8i64:
+; CHECK-NOFP16-GI: // %bb.0:
+; CHECK-NOFP16-GI-NEXT: addp v0.2d, v0.2d, v1.2d
+; CHECK-NOFP16-GI-NEXT: addp v1.2d, v2.2d, v3.2d
+; CHECK-NOFP16-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: or_deinterleave_shuffle_v8i64:
+; CHECK-FP16-GI: // %bb.0:
+; CHECK-FP16-GI-NEXT: addp v0.2d, v0.2d, v1.2d
+; CHECK-FP16-GI-NEXT: addp v1.2d, v2.2d, v3.2d
+; CHECK-FP16-GI-NEXT: ret
%r0 = shufflevector <8 x i64> %a, <8 x i64> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%r1 = shufflevector <8 x i64> %a, <8 x i64> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%o = or disjoint <4 x i64> %r0, %r1
@@ -629,3 +960,5 @@ define <4 x i32> @xtn_uzp2_v4i32_or(<4 x i32> %x) {
ret <4 x i32> %r
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK-NOFP16: {{.*}}
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