[llvm] [WIP] AMDGPU: VGPR bank conflict avoidance hints (PR #192140)

[Reem Elkhouly via llvm-commits]

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@@ -3853,6 +3858,104 @@ const int *SIRegisterInfo::getRegUnitPressureSets(MCRegUnit RegUnit) const {
   return AMDGPUGenRegisterInfo::getRegUnitPressureSets(RegUnit);
 }
 
+unsigned SIRegisterInfo::getVGPRBankIndex(MCRegister Reg) const {
+  return getHWRegIndex(Reg) % 4;
+}
+
+bool SIRegisterInfo::canHave3VGPROperands(const MachineInstr &MI) const {
+  if (!SIInstrInfo::isVALU(MI))
+    return false;
+
+  const MCInstrDesc &Desc = MI.getDesc();
+  const SIInstrInfo *TII = ST.getInstrInfo();
+  unsigned NumVGPRSrcs = 0;
+
+  // Count explicit source operands whose register class can hold VGPRs.
+  // Skip defs (operands 0..NumDefs-1); only inspect use slots.
+  for (unsigned i = Desc.getNumDefs(), e = Desc.getNumOperands(); i < e; ++i) {
+    const TargetRegisterClass *OpRC = TII->getRegClass(Desc, i);
+    if (OpRC && hasVGPRs(OpRC)) {
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amd-relkhoul wrote:

That's a fair point. However, I don't think it's wrong to include these instructions. Even if one operand turns out to be an SGPR or constant at runtime, the remaining two VGPR operands can still land on the same bank and cause a conflict. 
The focus on 3-operand instructions because they have the highest conflict potential and to limit compile-time overhead, but 2-way conflicts within those same instructions still worth resolution.

https://github.com/llvm/llvm-project/pull/192140