[llvm] [AMDGPU] Support Wave Reduction for i16 types - 1 (PR #194808)

[Matt Arsenault via llvm-commits]

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@@ -6673,6 +6728,34 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
   const DebugLoc &DL = MI.getDebugLoc();
 
   switch (MI.getOpcode()) {
+  case AMDGPU::WAVE_REDUCE_UMIN_PSEUDO_U16:
+    return lowerWaveReduce(MI, *BB, *getSubtarget(),
+                           ST.getGeneration() == AMDGPUSubtarget::GFX10
+                               ? AMDGPU::V_MIN_U16_opsel_e64
+                           : ST.hasTrue16BitInsts()
+                               ? AMDGPU::V_MIN_U16_fake16_e64
+                               : AMDGPU::V_MIN_U16_e64);
+  case AMDGPU::WAVE_REDUCE_MIN_PSEUDO_I16:
+    return lowerWaveReduce(MI, *BB, *getSubtarget(),
+                           ST.getGeneration() == AMDGPUSubtarget::GFX10
+                               ? AMDGPU::V_MIN_I16_opsel_e64
+                           : ST.hasTrue16BitInsts()
+                               ? AMDGPU::V_MIN_I16_fake16_e64
+                               : AMDGPU::V_MIN_I16_e64);
+  case AMDGPU::WAVE_REDUCE_UMAX_PSEUDO_U16:
+    return lowerWaveReduce(MI, *BB, *getSubtarget(),
+                           ST.getGeneration() == AMDGPUSubtarget::GFX10
+                               ? AMDGPU::V_MAX_U16_opsel_e64
+                           : ST.hasTrue16BitInsts()
+                               ? AMDGPU::V_MAX_U16_fake16_e64
+                               : AMDGPU::V_MAX_U16_e64);
+  case AMDGPU::WAVE_REDUCE_MAX_PSEUDO_I16:
+    return lowerWaveReduce(MI, *BB, *getSubtarget(),
+                           ST.getGeneration() == AMDGPUSubtarget::GFX10
+                               ? AMDGPU::V_MAX_I16_opsel_e64
+                           : ST.hasTrue16BitInsts()
+                               ? AMDGPU::V_MAX_I16_fake16_e64
+                               : AMDGPU::V_MAX_I16_e64);
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arsenm wrote:

Should this be using the scalar instructions too? It's slightly more complicated than the simple bit ops since you have to perform the extension into the high bits in the prolog (I suppose we could just always promote these to i32?)

https://github.com/llvm/llvm-project/pull/194808