[llvm] [AMDGPU][True16] relax d16-write-vgpr32 condition (PR #194477)

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git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp --diff_from_common_commit
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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
index ddc853391..6f930a6e4 100644
--- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
@@ -1634,7 +1634,8 @@ AMDGPU::Waitcnt WaitcntBrackets::determineAsyncWait(unsigned N) {
 //
 // Replace VGPR16 to VGPR32 for wait check if:
 // 1. MI is a VALU16, and there is a wait event on the other half
-// 2. MI is a LdSt, and there is a wait event on the other half from different order group
+// 2. MI is a LdSt, and there is a wait event on the other half from different
+// order group
 MCPhysReg WaitcntBrackets::determineVGPR16Dependency(const MachineInstr &MI,
                                                      AMDGPU::InstCounterType T,
                                                      MCPhysReg Reg) const {

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https://github.com/llvm/llvm-project/pull/194477