[llvm] [VPlan] Add SCEV support for abs intrinsic (PR #195678)

[Madhur Amilkanthwar via llvm-commits]

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@@ -33,6 +34,45 @@ namespace {
   } while (0)
 
 using VPInstructionTest = VPlanTestBase;
+using VPlanSCEVTest = VPlanTestIRBase;
+
+TEST_F(VPlanSCEVTest, GetSCEVExprForVPValueAbs) {
+  const char *ModuleString =
+      "define void @f(i32 %x) {\n"
+      "entry:\n"
+      "  br label %loop\n"
+      "loop:\n"
+      "  %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]\n"
+      "  %iv.next = add nuw nsw i32 %iv, 1\n"
+      "  %exit = icmp eq i32 %iv.next, 4\n"
+      "  br i1 %exit, label %exit.block, label %loop\n"
+      "exit.block:\n"
+      "  ret void\n"
+      "}\n";
+
+  Module &M = parseModule(ModuleString);
+  Function *F = M.getFunction("f");
+  BasicBlock *LoopHeader = F->getEntryBlock().getSingleSuccessor();
+  doAnalysis(*F);
+
+  Loop *L = LI->getLoopFor(LoopHeader);
+  PredicatedScalarEvolution PSE(*SE, *L);
+  VPlan Plan(LoopHeader);
+  Argument *X = F->getArg(0);
+  VPValue *Op = Plan.getOrAddLiveIn(X);
+  VPValue *IsIntMinPoison = Plan.getOrAddLiveIn(ConstantInt::getTrue(*Ctx));
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madhur13490 wrote:

Done

https://github.com/llvm/llvm-project/pull/195678