[llvm] [AMDGPU][True16] relax d16-write-vgpr32 condition (PR #194477)

[Matt Arsenault via llvm-commits]

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@@ -1629,13 +1629,52 @@ AMDGPU::Waitcnt WaitcntBrackets::determineAsyncWait(unsigned N) {
   return Wait;
 }
 
+MCPhysReg WaitcntBrackets::determineVGPR16Dependency(const MachineInstr &MI,
+                                                     AMDGPU::InstCounterType T,
+                                                     MCPhysReg Reg) const {
+  const TargetRegisterClass *RC = Context->TRI.getPhysRegBaseClass(Reg);
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arsenm wrote:

Isn't the base class always the 32-bit class? 

https://github.com/llvm/llvm-project/pull/194477