[llvm] [AMDGPU][True16] relax d16-write-vgpr32 condition (PR #194477)

Matt Arsenault via llvm-commits llvm-commits at lists.llvm.org
Mon May 4 09:14:13 PDT 2026


================
@@ -1629,13 +1629,52 @@ AMDGPU::Waitcnt WaitcntBrackets::determineAsyncWait(unsigned N) {
   return Wait;
 }
 
+MCPhysReg WaitcntBrackets::determineVGPR16Dependency(const MachineInstr &MI,
+                                                     AMDGPU::InstCounterType T,
+                                                     MCPhysReg Reg) const {
+  const TargetRegisterClass *RC = Context->TRI.getPhysRegBaseClass(Reg);
+  unsigned Size = Context->TRI.getRegSizeInBits(*RC);
+
+  if (!(Size == 16) || !Context->ST.hasD16Writes32BitVgpr())
----------------
arsenm wrote:

```suggestion
  if (Size != 16 || !Context->ST.hasD16Writes32BitVgpr())
```

https://github.com/llvm/llvm-project/pull/194477


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