[llvm] [AMDGPU][True16] relax d16-write-vgpr32 condition (PR #194477)
Guo Chen via llvm-commits
llvm-commits at lists.llvm.org
Mon May 4 08:55:41 PDT 2026
https://github.com/broxigarchen updated https://github.com/llvm/llvm-project/pull/194477
>From 3809f3a4bc506a2e6c718075676329715ee65b0f Mon Sep 17 00:00:00 2001
From: guochen2 <guochen2 at amd.com>
Date: Mon, 27 Apr 2026 12:56:23 -0400
Subject: [PATCH] relax d16-write-vgpr32 war condition
---
llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp | 82 ++++++++---
.../branch-relaxation-inst-size-gfx11.ll | 4 +-
llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll | 1 -
llvm/test/CodeGen/AMDGPU/d16-write-vgpr32.ll | 139 ++++++++++++++++++
llvm/test/CodeGen/AMDGPU/function-args.ll | 30 ++--
5 files changed, 224 insertions(+), 32 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/d16-write-vgpr32.ll
diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
index f00b99075b022..7beb29cf502a8 100644
--- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
@@ -802,7 +802,11 @@ class WaitcntBrackets {
AMDGPU::Waitcnt &UpdateWait) const;
void determineWaitForPhysReg(AMDGPU::InstCounterType T, MCPhysReg Reg,
- AMDGPU::Waitcnt &Wait) const;
+ AMDGPU::Waitcnt &Wait,
+ const MachineInstr &MI) const;
+ MCPhysReg determineVGPR16Dependency(const MachineInstr &MI,
+ AMDGPU::InstCounterType T,
+ MCPhysReg Reg) const;
void determineWaitForLDSDMA(AMDGPU::InstCounterType T, VMEMID TID,
AMDGPU::Waitcnt &Wait) const;
AMDGPU::Waitcnt determineAsyncWait(unsigned N);
@@ -920,10 +924,6 @@ class WaitcntBrackets {
assert(Reg != AMDGPU::SCC && "Shouldn't be used on SCC");
if (!Context->TRI.isInAllocatableClass(Reg))
return {{}, {}};
- const TargetRegisterClass *RC = Context->TRI.getPhysRegBaseClass(Reg);
- unsigned Size = Context->TRI.getRegSizeInBits(*RC);
- if (Size == 16 && Context->ST.hasD16Writes32BitVgpr())
- Reg = Context->TRI.get32BitRegister(Reg);
return Context->TRI.regunits(Reg);
}
@@ -1629,13 +1629,52 @@ AMDGPU::Waitcnt WaitcntBrackets::determineAsyncWait(unsigned N) {
return Wait;
}
+MCPhysReg WaitcntBrackets::determineVGPR16Dependency(const MachineInstr &MI,
+ AMDGPU::InstCounterType T,
+ MCPhysReg Reg) const {
+ const TargetRegisterClass *RC = Context->TRI.getPhysRegBaseClass(Reg);
+ unsigned Size = Context->TRI.getRegSizeInBits(*RC);
+
+ if (!(Size == 16) || !Context->ST.hasD16Writes32BitVgpr())
+ return Reg;
+
+ // With D16Writes32BitVgpr, D16 Inst might clobber the whole vgpr32
+ // check dependency on the other half
+ Register Reg32 = Context->TRI.get32BitRegister(Reg);
+ Register OtherHalf = Context->TRI.getSubReg(
+ Reg32,
+ AMDGPU::isHi16Reg(Reg, Context->TRI) ? AMDGPU::lo16 : AMDGPU::hi16);
+
+ AMDGPU::Waitcnt Wait;
+ for (MCRegUnit RU : regunits(OtherHalf))
+ determineWaitForScore(T, getVMemScore(toVMEMID(RU), T), Wait);
+
+ // no wait on otherhalf
+ if (!Wait.hasWait())
+ return Reg;
+
+ if (Context->TII.isVALU(MI))
+ return Reg32;
+
+ // if hi/lo16 mixed events
+ WaitEventSet MIEvents = Context->getEventsFor(MI);
+ WaitEventSet OtherHalfEvents = Context->getWaitEvents(T);
+ WaitEventSet Events = MIEvents & OtherHalfEvents;
+ if (Events.twoOrMore())
+ return Reg32;
+ return Reg;
+}
+
void WaitcntBrackets::determineWaitForPhysReg(AMDGPU::InstCounterType T,
MCPhysReg Reg,
- AMDGPU::Waitcnt &Wait) const {
+ AMDGPU::Waitcnt &Wait,
+ const MachineInstr &MI) const {
if (Reg == AMDGPU::SCC) {
determineWaitForScore(T, SCCScore, Wait);
} else {
bool IsVGPR = Context->TRI.isVectorRegister(Context->MRI, Reg);
+ if (IsVGPR)
+ Reg = determineVGPR16Dependency(MI, T, Reg);
for (MCRegUnit RU : regunits(Reg))
determineWaitForScore(
T, IsVGPR ? getVMemScore(toVMEMID(RU), T) : getSGPRScore(RU, T),
@@ -2562,12 +2601,12 @@ bool SIInsertWaitcnts::generateWaitcntInstBefore(
const MachineOperand &CallAddrOp = TII.getCalleeOperand(MI);
if (CallAddrOp.isReg()) {
ScoreBrackets.determineWaitForPhysReg(
- SmemAccessCounter, CallAddrOp.getReg().asMCReg(), Wait);
+ SmemAccessCounter, CallAddrOp.getReg().asMCReg(), Wait, MI);
if (const auto *RtnAddrOp =
TII.getNamedOperand(MI, AMDGPU::OpName::dst)) {
ScoreBrackets.determineWaitForPhysReg(
- SmemAccessCounter, RtnAddrOp->getReg().asMCReg(), Wait);
+ SmemAccessCounter, RtnAddrOp->getReg().asMCReg(), Wait, MI);
}
}
} else if (Opc == AMDGPU::S_BARRIER_WAIT) {
@@ -2650,9 +2689,10 @@ bool SIInsertWaitcnts::generateWaitcntInstBefore(
if (Op.isImplicit() && MI.mayLoadOrStore())
continue;
- ScoreBrackets.determineWaitForPhysReg(AMDGPU::VA_VDST, Reg, Wait);
+ ScoreBrackets.determineWaitForPhysReg(AMDGPU::VA_VDST, Reg, Wait, MI);
if (Op.isDef())
- ScoreBrackets.determineWaitForPhysReg(AMDGPU::VM_VSRC, Reg, Wait);
+ ScoreBrackets.determineWaitForPhysReg(AMDGPU::VM_VSRC, Reg, Wait,
+ MI);
// RAW always needs an s_waitcnt. WAW needs an s_waitcnt unless the
// previous write and this write are the same type of VMEM
// instruction, in which case they are (in some architectures)
@@ -2663,25 +2703,29 @@ bool SIInsertWaitcnts::generateWaitcntInstBefore(
ScoreBrackets.hasOtherPendingVmemTypes(Reg, getVmemType(MI)) ||
ScoreBrackets.hasPointSamplePendingVmemTypes(MI, Reg) ||
!ST.hasVmemWriteVgprInOrder()) {
- ScoreBrackets.determineWaitForPhysReg(AMDGPU::LOAD_CNT, Reg, Wait);
- ScoreBrackets.determineWaitForPhysReg(AMDGPU::SAMPLE_CNT, Reg,
- Wait);
- ScoreBrackets.determineWaitForPhysReg(AMDGPU::BVH_CNT, Reg, Wait);
+ ScoreBrackets.determineWaitForPhysReg(AMDGPU::LOAD_CNT, Reg, Wait,
+ MI);
+ ScoreBrackets.determineWaitForPhysReg(AMDGPU::SAMPLE_CNT, Reg, Wait,
+ MI);
+ ScoreBrackets.determineWaitForPhysReg(AMDGPU::BVH_CNT, Reg, Wait,
+ MI);
ScoreBrackets.clearVgprVmemTypes(Reg);
}
if (Op.isDef() || ScoreBrackets.hasPendingEvent(EXP_LDS_ACCESS)) {
- ScoreBrackets.determineWaitForPhysReg(AMDGPU::EXP_CNT, Reg, Wait);
+ ScoreBrackets.determineWaitForPhysReg(AMDGPU::EXP_CNT, Reg, Wait,
+ MI);
}
- ScoreBrackets.determineWaitForPhysReg(AMDGPU::DS_CNT, Reg, Wait);
+ ScoreBrackets.determineWaitForPhysReg(AMDGPU::DS_CNT, Reg, Wait, MI);
} else if (Op.getReg() == AMDGPU::SCC) {
- ScoreBrackets.determineWaitForPhysReg(AMDGPU::KM_CNT, Reg, Wait);
+ ScoreBrackets.determineWaitForPhysReg(AMDGPU::KM_CNT, Reg, Wait, MI);
} else {
- ScoreBrackets.determineWaitForPhysReg(SmemAccessCounter, Reg, Wait);
+ ScoreBrackets.determineWaitForPhysReg(SmemAccessCounter, Reg, Wait,
+ MI);
}
if (ST.hasWaitXcnt() && Op.isDef())
- ScoreBrackets.determineWaitForPhysReg(AMDGPU::X_CNT, Reg, Wait);
+ ScoreBrackets.determineWaitForPhysReg(AMDGPU::X_CNT, Reg, Wait, MI);
}
}
}
diff --git a/llvm/test/CodeGen/AMDGPU/branch-relaxation-inst-size-gfx11.ll b/llvm/test/CodeGen/AMDGPU/branch-relaxation-inst-size-gfx11.ll
index 6bebc8f5d0d18..dd389375b0d77 100644
--- a/llvm/test/CodeGen/AMDGPU/branch-relaxation-inst-size-gfx11.ll
+++ b/llvm/test/CodeGen/AMDGPU/branch-relaxation-inst-size-gfx11.ll
@@ -23,9 +23,9 @@ define amdgpu_kernel void @long_forward_branch_gfx11plus(ptr addrspace(1) %in, p
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: global_load_d16_b16 v0, v1, s[0:1]
; GFX11-NEXT: global_load_d16_hi_b16 v0, v1, s[0:1] offset:2
-; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_waitcnt vmcnt(1)
; GFX11-NEXT: global_store_b16 v1, v0, s[2:3]
+; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: global_store_d16_hi_b16 v1, v0, s[2:3] offset:2
; GFX11-NEXT: .LBB0_2: ; %bb3
; GFX11-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll b/llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
index 76f84756dc3c1..062f682bf52ad 100644
--- a/llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
+++ b/llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
@@ -1093,7 +1093,6 @@ define <2 x i16> @chain_hi_to_lo_group_may_alias_store(ptr addrspace(3) %ptr, pt
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, 0x7b
; GFX11-TRUE16-NEXT: ds_load_u16_d16_hi v2, v0
-; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: ds_store_b16 v1, v2
; GFX11-TRUE16-NEXT: ds_load_u16_d16 v2, v0 offset:2
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/d16-write-vgpr32.ll b/llvm/test/CodeGen/AMDGPU/d16-write-vgpr32.ll
new file mode 100644
index 0000000000000..6e8443138ab22
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/d16-write-vgpr32.ll
@@ -0,0 +1,139 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc %s -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s
+; RUN: llc %s -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12 %s
+
+; wait 0 bewteen load_d16_hi16 and or(v0.l,v0.l)
+define amdgpu_kernel void @d16_load_and_valu(ptr %a, ptr %b) {
+; GFX11-LABEL: d16_load_and_valu:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s0
+; GFX11-NEXT: v_dual_mov_b32 v4, s3 :: v_dual_mov_b32 v3, s2
+; GFX11-NEXT: flat_load_d16_b16 v0, v[1:2]
+; GFX11-NEXT: flat_load_d16_hi_b16 v0, v[3:4]
+; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_or_b16 v0.l, v0.l, 1
+; GFX11-NEXT: v_or_b16 v0.h, v0.h, 1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_add_nc_u16 v0.l, v0.l, 10
+; GFX11-NEXT: flat_store_b16 v[1:2], v0
+; GFX11-NEXT: flat_store_d16_hi_b16 v[3:4], v0
+; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: d16_load_and_valu:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s0
+; GFX12-NEXT: v_dual_mov_b32 v4, s3 :: v_dual_mov_b32 v3, s2
+; GFX12-NEXT: flat_load_d16_b16 v0, v[1:2]
+; GFX12-NEXT: flat_load_d16_hi_b16 v0, v[3:4]
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: v_or_b16 v0.l, v0.l, 1
+; GFX12-NEXT: v_or_b16 v0.h, v0.h, 1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-NEXT: v_add_nc_u16 v0.l, v0.l, 10
+; GFX12-NEXT: flat_store_b16 v[1:2], v0
+; GFX12-NEXT: flat_store_d16_hi_b16 v[3:4], v0
+; GFX12-NEXT: s_endpgm
+ %1 = load i16, ptr %a, align 2
+ %2 = or i16 %1, 1
+ %3 = load i16, ptr %b, align 2
+ %4 = add i16 %2, 10
+ %5 = or i16 %3, 1
+ store i16 %4, ptr %a, align 2
+ store i16 %5, ptr %b, align 2
+ ret void
+}
+
+; no wait bewteen load_d16 and load_d16_hi from same order group
+define amdgpu_kernel void @d16_load_same_order_group(ptr %a, ptr %b) {
+; GFX11-LABEL: d16_load_same_order_group:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_dual_mov_b32 v0, 16 :: v_dual_mov_b32 v1, 0
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-NEXT: flat_load_b32 v0, v[0:1]
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshlrev_b64 v[0:1], 1, v[0:1]
+; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, s2, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, s3, v1, vcc_lo
+; GFX11-NEXT: flat_load_d16_b16 v0, v[2:3]
+; GFX11-NEXT: flat_load_d16_hi_b16 v0, v[4:5]
+; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-NEXT: flat_store_b16 v[2:3], v0
+; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: d16_load_same_order_group:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: v_dual_mov_b32 v0, 16 :: v_dual_mov_b32 v1, 0
+; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX12-NEXT: flat_load_b32 v0, v[0:1]
+; GFX12-NEXT: v_mov_b32_e32 v1, 0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-NEXT: v_lshlrev_b64_e32 v[0:1], 1, v[0:1]
+; GFX12-NEXT: v_add_co_u32 v4, vcc_lo, s2, v0
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_add_co_ci_u32_e64 v5, null, s3, v1, vcc_lo
+; GFX12-NEXT: flat_load_d16_b16 v0, v[2:3]
+; GFX12-NEXT: flat_load_d16_hi_b16 v0, v[4:5]
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX12-NEXT: flat_store_b16 v[2:3], v0
+; GFX12-NEXT: s_endpgm
+ %1 = load i32, ptr inttoptr (i64 16 to ptr), align 4
+ %2 = load i16, ptr %a, align 2
+ %3 = zext i32 %1 to i64
+ %4 = getelementptr i16, ptr %b, i64 %3
+ %5 = load i16, ptr %4, align 2
+ %6 = or i16 %2, %5
+ store i16 %6, ptr %a, align 2
+ ret void
+}
+
+; wait bewteen load_d16 and load_d16_hi from two order group
+define amdgpu_kernel void @d16_two_order_group(ptr addrspace(3) %a, ptr %b) {
+; GFX11-LABEL: d16_two_order_group:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x2c
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s0
+; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x24
+; GFX11-NEXT: flat_load_d16_b16 v0, v[1:2]
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_mov_b32_e32 v3, s0
+; GFX11-NEXT: ds_load_u16_d16_hi v0, v3
+; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_or_b16 v0.l, v0.h, v0.l
+; GFX11-NEXT: flat_store_b16 v[1:2], v0
+; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: d16_two_order_group:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_load_b64 s[0:1], s[4:5], 0x2c
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s0
+; GFX12-NEXT: s_load_b32 s0, s[4:5], 0x24
+; GFX12-NEXT: flat_load_d16_b16 v0, v[1:2]
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_mov_b32_e32 v3, s0
+; GFX12-NEXT: ds_load_u16_d16_hi v0, v3
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: v_or_b16 v0.l, v0.h, v0.l
+; GFX12-NEXT: flat_store_b16 v[1:2], v0
+; GFX12-NEXT: s_endpgm
+ %1 = load i16, ptr addrspace(3) %a, align 2
+ %2 = load i16, ptr %b, align 2
+ %3 = or i16 %1, %2
+ store i16 %3, ptr %b, align 2
+ ret void
+}
diff --git a/llvm/test/CodeGen/AMDGPU/function-args.ll b/llvm/test/CodeGen/AMDGPU/function-args.ll
index 3928a44595761..07dcad993ffe2 100644
--- a/llvm/test/CodeGen/AMDGPU/function-args.ll
+++ b/llvm/test/CodeGen/AMDGPU/function-args.ll
@@ -2680,14 +2680,16 @@ define void @void_func_v32i32_i1_i8_i16_bf16(<32 x i32> %arg0, i1 %arg1, i8 %arg
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: buffer_store_b8 v16, off, s[0:3], 0 dlc
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(2)
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
; GFX11-TRUE16-NEXT: buffer_store_b8 v32, off, s[0:3], 0 dlc
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(2)
; GFX11-TRUE16-NEXT: buffer_store_d16_hi_b16 v32, off, s[0:3], 0 dlc
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: buffer_store_b16 v33, off, s[0:3], 0 dlc
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: buffer_store_d16_hi_b16 v33, off, s[0:3], 0 dlc
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -4166,44 +4168,52 @@ define void @void_func_v32i32_v16i8(<32 x i32> %arg0, <16 x i8> %arg1) #0 {
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: buffer_store_b128 v[0:3], off, s[0:3], 0 dlc
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(14)
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(15)
; GFX11-TRUE16-NEXT: buffer_store_b8 v32, off, s[0:3], 0 dlc
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(14)
; GFX11-TRUE16-NEXT: buffer_store_d16_hi_b8 v32, off, s[0:3], 0 dlc
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(12)
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(13)
; GFX11-TRUE16-NEXT: buffer_store_b8 v33, off, s[0:3], 0 dlc
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(12)
; GFX11-TRUE16-NEXT: buffer_store_d16_hi_b8 v33, off, s[0:3], 0 dlc
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(10)
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(11)
; GFX11-TRUE16-NEXT: buffer_store_b8 v34, off, s[0:3], 0 dlc
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(10)
; GFX11-TRUE16-NEXT: buffer_store_d16_hi_b8 v34, off, s[0:3], 0 dlc
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(8)
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(9)
; GFX11-TRUE16-NEXT: buffer_store_b8 v35, off, s[0:3], 0 dlc
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(8)
; GFX11-TRUE16-NEXT: buffer_store_d16_hi_b8 v35, off, s[0:3], 0 dlc
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(6)
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
; GFX11-TRUE16-NEXT: buffer_store_b8 v36, off, s[0:3], 0 dlc
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(6)
; GFX11-TRUE16-NEXT: buffer_store_d16_hi_b8 v36, off, s[0:3], 0 dlc
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(4)
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(5)
; GFX11-TRUE16-NEXT: buffer_store_b8 v37, off, s[0:3], 0 dlc
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(4)
; GFX11-TRUE16-NEXT: buffer_store_d16_hi_b8 v37, off, s[0:3], 0 dlc
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(2)
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
; GFX11-TRUE16-NEXT: buffer_store_b8 v38, off, s[0:3], 0 dlc
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(2)
; GFX11-TRUE16-NEXT: buffer_store_d16_hi_b8 v38, off, s[0:3], 0 dlc
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: buffer_store_b8 v39, off, s[0:3], 0 dlc
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: buffer_store_d16_hi_b8 v39, off, s[0:3], 0 dlc
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
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