[llvm] [AMDGPU] Support Wave Reduction for i16 types - 1 (PR #194808)

[via llvm-commits]

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@@ -6114,12 +6153,42 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
           IsWave32 ? AMDGPU::S_FF1_I32_B32 : AMDGPU::S_FF1_I32_B64;
       BuildMI(*ComputeLoop, I, DL, TII->get(SFFOpc), FF1Reg)
           .addReg(ActiveBitsReg);
-      if (is32BitOpc) {
+      if (is32BitOpc || is16BitOpc) {
         BuildMI(*ComputeLoop, I, DL, TII->get(AMDGPU::V_READLANE_B32),
                 LaneValueReg)
             .addReg(SrcReg)
             .addReg(FF1Reg);
-        if (isFPOp) {
+        if (is16BitOpc) {
+          Register LaneValVgpr = MRI.createVirtualRegister(SrcRegClass);
+          Register VgprResultReg = MRI.createVirtualRegister(SrcRegClass);
+          bool hasSrc0Modifier = AMDGPU::getNamedOperandIdx(
+                                     Opc, AMDGPU::OpName::src0_modifiers) != -1;
+          bool hasSrc1Modifier = AMDGPU::getNamedOperandIdx(
+                                     Opc, AMDGPU::OpName::src1_modifiers) != -1;
+          bool hasClamp =
+              AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp) != -1;
+          bool hasOpSel =
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easyonaadit wrote:

I tried to inline them and get rid of the variable, but this is more readable.

https://github.com/llvm/llvm-project/pull/194808