[llvm] [RISCV] Add zero-store merging (PR #192662)

[Djordje Todorovic via llvm-commits]

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@@ -479,6 +537,46 @@ bool RISCVLoadStoreOpt::tryConvertToXqcilsmLdStPair(
   return true;
 }
 
+// Merge adjacent zero stores into a wider store.
+bool RISCVLoadStoreOpt::tryToMergeZeroStInst(
+    MachineBasicBlock::iterator &MBBI) {
+  assert(isPromotableZeroStoreInst(*MBBI) && "Expected narrow zero store.");
+  MachineInstr &MI = *MBBI;
+  MachineBasicBlock::iterator E = MI.getParent()->end();
+
+  // Don't merge volatile stores
+  if (MI.hasOrderedMemoryRef())
+    return false;
+
+  // Don't optimize frame setup/destroy instructions (stack spills)
+  if (MI.getFlag(MachineInstr::FrameSetup) ||
+      MI.getFlag(MachineInstr::FrameDestroy))
+    return false;
+
+  // Skip if there is no wider store on this target (e.g. SW on RV32).
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djtodoro wrote:

Done, thanks!

https://github.com/llvm/llvm-project/pull/192662