[llvm] 37f16ad - [MIPS] Remove InstrItinClass definitions and MipsSchedule.td (#188010)
via llvm-commits
llvm-commits at lists.llvm.org
Mon May 4 03:34:58 PDT 2026
Author: Djordje Todorovic
Date: 2026-05-04T12:34:53+02:00
New Revision: 37f16ad243850e19e1763f46fa732bcbf10673dd
URL: https://github.com/llvm/llvm-project/commit/37f16ad243850e19e1763f46fa732bcbf10673dd
DIFF: https://github.com/llvm/llvm-project/commit/37f16ad243850e19e1763f46fa732bcbf10673dd.diff
LOG: [MIPS] Remove InstrItinClass definitions and MipsSchedule.td (#188010)
Align Mips Targets with the rest of Architectures.
---------
Co-authored-by: Uros Stajic <uros.stajic at htecgroup.com>
Added:
Modified:
llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
llvm/lib/Target/Mips/MicroMipsDSPInstrFormats.td
llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td
llvm/lib/Target/Mips/MicroMipsInstrFPU.td
llvm/lib/Target/Mips/MicroMipsInstrFormats.td
llvm/lib/Target/Mips/MicroMipsInstrInfo.td
llvm/lib/Target/Mips/Mips.td
llvm/lib/Target/Mips/Mips16InstrFormats.td
llvm/lib/Target/Mips/Mips16InstrInfo.td
llvm/lib/Target/Mips/Mips32r6InstrFormats.td
llvm/lib/Target/Mips/Mips32r6InstrInfo.td
llvm/lib/Target/Mips/Mips64InstrInfo.td
llvm/lib/Target/Mips/Mips64r6InstrInfo.td
llvm/lib/Target/Mips/MipsCondMov.td
llvm/lib/Target/Mips/MipsDSPInstrFormats.td
llvm/lib/Target/Mips/MipsDSPInstrInfo.td
llvm/lib/Target/Mips/MipsEVAInstrFormats.td
llvm/lib/Target/Mips/MipsEVAInstrInfo.td
llvm/lib/Target/Mips/MipsInstrFPU.td
llvm/lib/Target/Mips/MipsInstrFormats.td
llvm/lib/Target/Mips/MipsInstrInfo.td
llvm/lib/Target/Mips/MipsMSAInstrFormats.td
llvm/lib/Target/Mips/MipsMSAInstrInfo.td
llvm/lib/Target/Mips/MipsMTInstrFormats.td
llvm/lib/Target/Mips/MipsMTInstrInfo.td
llvm/lib/Target/Mips/MipsSubtarget.cpp
llvm/lib/Target/Mips/MipsSubtarget.h
Removed:
llvm/lib/Target/Mips/MipsSchedule.td
################################################################################
diff --git a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
index e33a2305a536b..5487254c14ab3 100644
--- a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
+++ b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
@@ -280,7 +280,6 @@ class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
dag OutOperandList = (outs);
string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
list<Register> Defs = [AT];
- InstrItinClass Itinerary = II_BCCZC;
}
class BEQZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"beqzalc", brtarget_mm,
@@ -328,7 +327,6 @@ class CMP_CBR_2R_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
dag OutOperandList = (outs);
string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
list<Register> Defs = [AT];
- InstrItinClass Itinerary = II_BCCC;
}
class BGEC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bgec", brtarget_lsl2_mm,
@@ -344,35 +342,34 @@ class BEQC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"beqc", brtarget_lsl2_mm,
class BNEC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bnec", brtarget_lsl2_mm,
GPR32Opnd>;
-class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd, 1, II_ADD>;
+class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd, 1>;
class ADDIU_MMR6_DESC
- : ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16, add>;
-class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU>;
-class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>;
-class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd, 1, II_MUH, mulhs>;
-class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd, 1, II_MULU>;
-class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd, 1, II_MUHU, mulhu>;
-
-class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd, InstrItinClass Itin>
+ : ArithLogicI<"addiu", simm16, GPR32Opnd, immSExt16, add>;
+class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd, 1>;
+class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd, 1, mul>;
+class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd, 1, mulhs>;
+class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd, 1>;
+class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd, 1, mulhu>;
+
+class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd>
: BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
dag InOperandList = (ins opnd:$offset);
dag OutOperandList = (outs);
string AsmString = !strconcat(instr_asm, "\t$offset");
bit isBarrier = 1;
- InstrItinClass Itinerary = Itin;
}
-class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26_mm, II_BALC> {
+class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26_mm> {
bit isCall = 1;
list<Register> Defs = [RA];
}
-class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26_mm, II_BC> {
+class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26_mm> {
list<dag> Pattern = [(br bb:$offset)];
}
class BC16_MMR6_DESC : MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
!strconcat("bc16", "\t$offset"), [],
- II_BC, FrmI>,
+ FrmI>,
MMR6Arch<"bc16"> {
let isBranch = 1;
let isTerminator = 1;
@@ -393,8 +390,8 @@ class BEQZC_BNEZC_MM16R6_DESC_BASE<string instr_asm>
class BEQZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"beqzc16">;
class BNEZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"bnezc16">;
-class SUB_MMR6_DESC : ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>;
-class SUBU_MMR6_DESC : ArithLogicR<"subu", GPR32Opnd, 0,II_SUBU>;
+class SUB_MMR6_DESC : ArithLogicR<"sub", GPR32Opnd, 0>;
+class SUBU_MMR6_DESC : ArithLogicR<"subu", GPR32Opnd, 0>;
class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
: MMR6Arch<instr_asm> {
@@ -402,63 +399,57 @@ class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
dag InOperandList = (ins GPROpnd:$rt);
string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
list<dag> Pattern = [];
- InstrItinClass Itinerary = II_BITSWAP;
}
class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>;
class BRK_MMR6_DESC : BRK_FT<"break">;
-class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd,
- InstrItinClass Itin>
+class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd>
: MMR6Arch<instr_asm> {
dag OutOperandList = (outs);
dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
list<dag> Pattern = [];
string DecoderMethod = "DecodeCacheOpMM";
- InstrItinClass Itinerary = Itin;
}
-class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, II_CACHE>;
-class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, II_PREF>;
+class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12>;
+class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12>;
class LB_LBU_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd,
- RegisterOperand GPROpnd, InstrItinClass Itin>
+ RegisterOperand GPROpnd>
: MMR6Arch<instr_asm> {
dag OutOperandList = (outs GPROpnd:$rt);
dag InOperandList = (ins MemOpnd:$addr);
string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
string DecoderMethod = "DecodeLoadByte15";
bit mayLoad = 1;
- InstrItinClass Itinerary = Itin;
}
-class LB_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lb", mem_mm_16, GPR32Opnd, II_LB>;
-class LBU_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lbu", mem_mm_16, GPR32Opnd,
- II_LBU>;
+class LB_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lb", mem_mm_16, GPR32Opnd>;
+class LBU_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lbu", mem_mm_16, GPR32Opnd>;
-class CLO_CLZ_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- InstrItinClass Itin> : MMR6Arch<instr_asm> {
+class CLO_CLZ_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
+ : MMR6Arch<instr_asm> {
dag OutOperandList = (outs GPROpnd:$rt);
dag InOperandList = (ins GPROpnd:$rs);
string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
- InstrItinClass Itinerary = Itin;
}
-class CLO_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clo", GPR32Opnd, II_CLO>;
-class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd, II_CLZ>;
+class CLO_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clo", GPR32Opnd>;
+class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd>;
-class EHB_MMR6_DESC : Barrier<"ehb", II_EHB>;
-class EI_MMR6_DESC : DEI_FT<"ei", GPR32Opnd, II_EI>;
-class DI_MMR6_DESC : DEI_FT<"di", GPR32Opnd, II_DI>;
+class EHB_MMR6_DESC : Barrier<"ehb">;
+class EI_MMR6_DESC : DEI_FT<"ei", GPR32Opnd>;
+class DI_MMR6_DESC : DEI_FT<"di", GPR32Opnd>;
-class ERET_MMR6_DESC : ER_FT<"eret", II_ERET>;
-class DERET_MMR6_DESC : ER_FT<"deret", II_DERET>;
-class ERETNC_MMR6_DESC : ER_FT<"eretnc", II_ERETNC>;
+class ERET_MMR6_DESC : ER_FT<"eret">;
+class DERET_MMR6_DESC : ER_FT<"deret">;
+class ERETNC_MMR6_DESC : ER_FT<"eretnc">;
class JALRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
: MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
- [(MipsJmpLink RO:$rs)], II_JALR, FrmR>,
+ [(MipsJmpLink RO:$rs)], FrmR>,
MMR6Arch<opstr> {
let isCall = 1;
let hasDelaySlot = 0;
@@ -468,32 +459,30 @@ class JALRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
class JALRC16_MMR6_DESC : JALRC16_MMR6_DESC_BASE<"jalr", GPR32Opnd>;
class JMP_MMR6_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
- RegisterOperand GPROpnd,
- InstrItinClass Itin>
+ RegisterOperand GPROpnd>
: MMR6Arch<opstr> {
dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
string AsmString = !strconcat(opstr, "\t$rt, $offset");
list<dag> Pattern = [];
bit isTerminator = 1;
bit hasDelaySlot = 0;
- InstrItinClass Itinerary = Itin;
}
class JIALC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
- GPR32Opnd, II_JIALC> {
+ GPR32Opnd> {
bit isCall = 1;
list<Register> Defs = [RA];
}
class JIC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
- GPR32Opnd, II_JIC> {
+ GPR32Opnd> {
bit isBarrier = 1;
list<Register> Defs = [AT];
}
class JRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
: MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
- [], II_JR, FrmR>,
+ [], FrmR>,
MMR6Arch<opstr> {
let hasDelaySlot = 0;
let isBranch = 1;
@@ -503,7 +492,7 @@ class JRC16_MMR6_DESC : JRC16_MMR6_DESC_BASE<"jrc16", GPR32Opnd>;
class JRCADDIUSP_MMR6_DESC
: MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jrcaddiusp\t$imm",
- [], II_JRADDIUSP, FrmR>,
+ [], FrmR>,
MMR6Arch<"jrcaddiusp"> {
let hasDelaySlot = 0;
let isTerminator = 1;
@@ -513,88 +502,77 @@ class JRCADDIUSP_MMR6_DESC
}
class ALIGN_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- Operand ImmOpnd, InstrItinClass Itin>
+ Operand ImmOpnd>
: MMR6Arch<instr_asm> {
dag OutOperandList = (outs GPROpnd:$rd);
dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
list<dag> Pattern = [];
- InstrItinClass Itinerary = Itin;
}
-class ALIGN_MMR6_DESC : ALIGN_MMR6_DESC_BASE<"align", GPR32Opnd, uimm2,
- II_ALIGN>;
+class ALIGN_MMR6_DESC : ALIGN_MMR6_DESC_BASE<"align", GPR32Opnd, uimm2>;
-class AUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- InstrItinClass Itin> : MMR6Arch<instr_asm> {
+class AUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
+ : MMR6Arch<instr_asm> {
dag OutOperandList = (outs GPROpnd:$rt);
dag InOperandList = (ins GPROpnd:$rs, uimm16:$imm);
string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
list<dag> Pattern = [];
- InstrItinClass Itinerary = Itin;
}
-class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd, II_AUI>;
+class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd>;
-class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- InstrItinClass Itin> : MMR6Arch<instr_asm> {
+class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
+ : MMR6Arch<instr_asm> {
dag OutOperandList = (outs GPROpnd:$rt);
dag InOperandList = (ins simm16:$imm);
string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
list<dag> Pattern = [];
- InstrItinClass Itinerary = Itin;
}
-class ALUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"aluipc", GPR32Opnd, II_ALUIPC>;
-class AUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"auipc", GPR32Opnd, II_AUIPC>;
+class ALUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"aluipc", GPR32Opnd>;
+class AUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"auipc", GPR32Opnd>;
class LSA_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- Operand ImmOpnd, InstrItinClass Itin>
+ Operand ImmOpnd>
: MMR6Arch<instr_asm> {
dag OutOperandList = (outs GPROpnd:$rd);
dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $rd, $imm2");
list<dag> Pattern = [];
- InstrItinClass Itinerary = Itin;
}
-class LSA_MMR6_DESC : LSA_MMR6_DESC_BASE<"lsa", GPR32Opnd, uimm2_plus1, II_LSA>;
+class LSA_MMR6_DESC : LSA_MMR6_DESC_BASE<"lsa", GPR32Opnd, uimm2_plus1>;
class PCREL_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- Operand ImmOpnd, InstrItinClass Itin>
+ Operand ImmOpnd>
: MMR6Arch<instr_asm> {
dag OutOperandList = (outs GPROpnd:$rt);
dag InOperandList = (ins ImmOpnd:$imm);
string AsmString = !strconcat(instr_asm, "\t$rt, $imm");
list<dag> Pattern = [];
- InstrItinClass Itinerary = Itin;
}
class ADDIUPC_MMR6_DESC : PCREL_MMR6_DESC_BASE<"addiupc", GPR32Opnd,
- simm19_lsl2, II_ADDIUPC>;
-class LWPC_MMR6_DESC: PCREL_MMR6_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2,
- II_LWPC>;
+ simm19_lsl2>;
+class LWPC_MMR6_DESC: PCREL_MMR6_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>;
-class SELEQNE_Z_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- InstrItinClass Itin> : MMR6Arch<instr_asm> {
+class SELEQNE_Z_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
+ : MMR6Arch<instr_asm> {
dag OutOperandList = (outs GPROpnd:$rd);
dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
list<dag> Pattern = [];
- InstrItinClass Itinerary = Itin;
}
-class SELEQZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"seleqz", GPR32Opnd,
- II_SELCCZ>;
-class SELNEZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"selnez", GPR32Opnd,
- II_SELCCZ>;
-class PAUSE_MMR6_DESC : Barrier<"pause", II_PAUSE>;
+class SELEQZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"seleqz", GPR32Opnd>;
+class SELNEZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"selnez", GPR32Opnd>;
+class PAUSE_MMR6_DESC : Barrier<"pause">;
class RDHWR_MMR6_DESC : MMR6Arch<"rdhwr">, MipsR6Inst {
dag OutOperandList = (outs GPR32Opnd:$rt);
dag InOperandList = (ins HWRegsOpnd:$rs, uimm3:$sel);
string AsmString = !strconcat("rdhwr", "\t$rt, $rs, $sel");
list<dag> Pattern = [];
- InstrItinClass Itinerary = II_RDHWR;
Format Form = FrmR;
}
@@ -602,11 +580,10 @@ class WAIT_MMR6_DESC : WaitMM<"wait">;
// FIXME: ssnop should not be defined for R6. Per MD000582 microMIPS32 6.03:
// Assemblers targeting specifically Release 6 should reject the SSNOP
// instruction with an error.
-class SSNOP_MMR6_DESC : Barrier<"ssnop", II_SSNOP>;
-class SLL_MMR6_DESC : shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>;
+class SSNOP_MMR6_DESC : Barrier<"ssnop">;
+class SLL_MMR6_DESC : shift_rotate_imm<"sll", uimm5, GPR32Opnd>;
class DIVMOD_MMR6_DESC_BASE<string opstr, RegisterOperand GPROpnd,
- InstrItinClass Itin,
SDPatternOperator OpNode=null_frag>
: MipsR6Inst {
dag OutOperandList = (outs GPROpnd:$rd);
@@ -617,32 +594,28 @@ class DIVMOD_MMR6_DESC_BASE<string opstr, RegisterOperand GPROpnd,
Format f = FrmR;
let isCommutable = 0;
let isReMaterializable = 1;
- InstrItinClass Itinerary = Itin;
// This instruction doesn't trap division by zero itself. We must insert
// teq instructions as well.
bit usesCustomInserter = 1;
}
-class DIV_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"div", GPR32Opnd, II_DIV, sdiv>;
-class DIVU_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"divu", GPR32Opnd, II_DIVU, udiv>;
-class MOD_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"mod", GPR32Opnd, II_MOD, srem>;
-class MODU_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"modu", GPR32Opnd, II_MODU, urem>;
-class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>;
-class ANDI_MMR6_DESC : ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI>;
+class DIV_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"div", GPR32Opnd, sdiv>;
+class DIVU_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"divu", GPR32Opnd, udiv>;
+class MOD_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"mod", GPR32Opnd, srem>;
+class MODU_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"modu", GPR32Opnd, urem>;
+class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd, 1, and>;
+class ANDI_MMR6_DESC : ArithLogicI<"andi", uimm16, GPR32Opnd>;
class NOR_MMR6_DESC : LogicNOR<"nor", GPR32Opnd>;
-class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>;
-class ORI_MMR6_DESC : ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
+class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd, 1, or>;
+class ORI_MMR6_DESC : ArithLogicI<"ori", uimm16, GPR32Opnd, immZExt16,
or> {
int AddedComplexity = 1;
}
-class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>;
-class XORI_MMR6_DESC : ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI,
+class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd, 1, xor>;
+class XORI_MMR6_DESC : ArithLogicI<"xori", uimm16, GPR32Opnd,
immZExt16, xor>;
-class SW_MMR6_DESC : Store<"sw", GPR32Opnd> {
- InstrItinClass Itinerary = II_SW;
-}
-class WRPGPR_WSBH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO,
- InstrItinClass Itin> {
+class SW_MMR6_DESC : Store<"sw", GPR32Opnd>;
+class WRPGPR_WSBH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO> {
dag InOperandList = (ins RO:$rs);
dag OutOperandList = (outs RO:$rt);
string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
@@ -650,112 +623,94 @@ class WRPGPR_WSBH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO,
Format f = FrmR;
string BaseOpcode = instr_asm;
bit hasSideEffects = 0;
- InstrItinClass Itinerary = Itin;
}
-class WRPGPR_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wrpgpr", GPR32Opnd,
- II_WRPGPR>;
-class WSBH_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wsbh", GPR32Opnd, II_WSBH>;
+class WRPGPR_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wrpgpr", GPR32Opnd>;
+class WSBH_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wsbh", GPR32Opnd>;
class MTC0_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
- RegisterOperand SrcRC, InstrItinClass Itin> {
+ RegisterOperand SrcRC> {
dag InOperandList = (ins SrcRC:$rt, uimm3:$sel);
dag OutOperandList = (outs DstRC:$rs);
string AsmString = !strconcat(opstr, "\t$rt, $rs, $sel");
list<dag> Pattern = [];
Format f = FrmFR;
string BaseOpcode = opstr;
- InstrItinClass Itinerary = Itin;
}
class MTC1_MMR6_DESC_BASE<
string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
- InstrItinClass Itin = NoItinerary, SDPatternOperator OpNode = null_frag>
+ SDPatternOperator OpNode = null_frag>
: MipsR6Inst {
dag InOperandList = (ins SrcRC:$rt);
dag OutOperandList = (outs DstRC:$fs);
string AsmString = !strconcat(opstr, "\t$rt, $fs");
list<dag> Pattern = [(set DstRC:$fs, (OpNode SrcRC:$rt))];
Format f = FrmFR;
- InstrItinClass Itinerary = Itin;
string BaseOpcode = opstr;
}
class MTC1_64_MMR6_DESC_BASE<
- string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
- InstrItinClass Itin = NoItinerary> : MipsR6Inst {
+ string opstr, RegisterOperand DstRC, RegisterOperand SrcRC>
+ : MipsR6Inst {
dag InOperandList = (ins DstRC:$fs_in, SrcRC:$rt);
dag OutOperandList = (outs DstRC:$fs);
string AsmString = !strconcat(opstr, "\t$rt, $fs");
list<dag> Pattern = [];
Format f = FrmFR;
- InstrItinClass Itinerary = Itin;
string BaseOpcode = opstr;
// $fs_in is part of a white lie to work around a widespread bug in the FPU
// implementation. See expandBuildPairF64 for details.
let Constraints = "$fs = $fs_in";
}
class MTC2_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
- RegisterOperand SrcRC, InstrItinClass Itin> {
+ RegisterOperand SrcRC> {
dag InOperandList = (ins SrcRC:$rt);
dag OutOperandList = (outs DstRC:$impl);
string AsmString = !strconcat(opstr, "\t$rt, $impl");
list<dag> Pattern = [];
Format f = FrmFR;
string BaseOpcode = opstr;
- InstrItinClass Itinerary = Itin;
}
-class MTC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mtc0", COP0Opnd, GPR32Opnd,
- II_MTC0>;
+class MTC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mtc0", COP0Opnd, GPR32Opnd>;
class MTC1_MMR6_DESC : MTC1_MMR6_DESC_BASE<"mtc1", FGR32Opnd, GPR32Opnd,
- II_MTC1, bitconvert>, HARDFLOAT;
-class MTC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mtc2", COP2Opnd, GPR32Opnd,
- II_MTC2>;
-class MTHC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mthc0", COP0Opnd, GPR32Opnd,
- II_MTHC0>;
-class MTHC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mthc2", COP2Opnd, GPR32Opnd,
- II_MTC2>;
+ bitconvert>, HARDFLOAT;
+class MTC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mtc2", COP2Opnd, GPR32Opnd>;
+class MTHC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mthc0", COP0Opnd, GPR32Opnd>;
+class MTHC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mthc2", COP2Opnd, GPR32Opnd>;
class MFC0_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
- RegisterOperand SrcRC, InstrItinClass Itin> {
+ RegisterOperand SrcRC> {
dag InOperandList = (ins SrcRC:$rs, uimm3:$sel);
dag OutOperandList = (outs DstRC:$rt);
string AsmString = !strconcat(opstr, "\t$rt, $rs, $sel");
list<dag> Pattern = [];
Format f = FrmFR;
string BaseOpcode = opstr;
- InstrItinClass Itinerary = Itin;
}
class MFC1_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
RegisterOperand SrcRC,
- InstrItinClass Itin = NoItinerary,
SDPatternOperator OpNode = null_frag> : MipsR6Inst {
dag InOperandList = (ins SrcRC:$fs);
dag OutOperandList = (outs DstRC:$rt);
string AsmString = !strconcat(opstr, "\t$rt, $fs");
list<dag> Pattern = [(set DstRC:$rt, (OpNode SrcRC:$fs))];
Format f = FrmFR;
- InstrItinClass Itinerary = Itin;
string BaseOpcode = opstr;
}
class MFC2_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
- RegisterOperand SrcRC, InstrItinClass Itin> {
+ RegisterOperand SrcRC> {
dag InOperandList = (ins SrcRC:$impl);
dag OutOperandList = (outs DstRC:$rt);
string AsmString = !strconcat(opstr, "\t$rt, $impl");
list<dag> Pattern = [];
Format f = FrmFR;
string BaseOpcode = opstr;
- InstrItinClass Itinerary = Itin;
}
-class MFC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfc0", GPR32Opnd, COP0Opnd,
- II_MFC0>;
+class MFC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfc0", GPR32Opnd, COP0Opnd>;
class MFC1_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfc1", GPR32Opnd, FGR32Opnd,
- II_MFC1, bitconvert>, HARDFLOAT;
-class MFC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfc2", GPR32Opnd, COP2Opnd,
- II_MFC2>;
-class MFHC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfhc0", GPR32Opnd, COP0Opnd,
- II_MFHC0>;
-class MFHC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfhc2", GPR32Opnd, COP2Opnd,
- II_MFC2>;
+ bitconvert>, HARDFLOAT;
+class MFC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfc2", GPR32Opnd, COP2Opnd>;
+class MFHC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfhc0", GPR32Opnd, COP0Opnd>;
+class MFHC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfhc2", GPR32Opnd, COP2Opnd>;
class LDC1_D64_MMR6_DESC : MipsR6Inst, HARDFLOAT, FGR_64 {
dag InOperandList = (ins mem_mm_16:$addr);
@@ -763,7 +718,6 @@ class LDC1_D64_MMR6_DESC : MipsR6Inst, HARDFLOAT, FGR_64 {
string AsmString = !strconcat("ldc1", "\t$ft, $addr");
list<dag> Pattern = [(set FGR64Opnd:$ft, (load addrimm16:$addr))];
Format f = FrmFI;
- InstrItinClass Itinerary = II_LDC1;
string BaseOpcode = "ldc1";
bit mayLoad = 1;
let DecoderMethod = "DecodeFMemMMR2";
@@ -775,342 +729,311 @@ class SDC1_D64_MMR6_DESC : MipsR6Inst, HARDFLOAT, FGR_64 {
string AsmString = !strconcat("sdc1", "\t$ft, $addr");
list<dag> Pattern = [(store FGR64Opnd:$ft, addrimm16:$addr)];
Format f = FrmFI;
- InstrItinClass Itinerary = II_SDC1;
string BaseOpcode = "sdc1";
bit mayStore = 1;
let DecoderMethod = "DecodeFMemMMR2";
}
-class LDC2_LWC2_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
+class LDC2_LWC2_MMR6_DESC_BASE<string opstr> {
dag OutOperandList = (outs COP2Opnd:$rt);
dag InOperandList = (ins mem_mm_11:$addr);
string AsmString = !strconcat(opstr, "\t$rt, $addr");
list<dag> Pattern = [(set COP2Opnd:$rt, (load addrimm11:$addr))];
Format f = FrmFI;
- InstrItinClass Itinerary = itin;
string BaseOpcode = opstr;
bit mayLoad = 1;
string DecoderMethod = "DecodeFMemCop2MMR6";
}
-class LDC2_MMR6_DESC : LDC2_LWC2_MMR6_DESC_BASE<"ldc2", II_LDC2>;
-class LWC2_MMR6_DESC : LDC2_LWC2_MMR6_DESC_BASE<"lwc2", II_LWC2>;
+class LDC2_MMR6_DESC : LDC2_LWC2_MMR6_DESC_BASE<"ldc2">;
+class LWC2_MMR6_DESC : LDC2_LWC2_MMR6_DESC_BASE<"lwc2">;
-class SDC2_SWC2_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
+class SDC2_SWC2_MMR6_DESC_BASE<string opstr> {
dag OutOperandList = (outs);
dag InOperandList = (ins COP2Opnd:$rt, mem_mm_11:$addr);
string AsmString = !strconcat(opstr, "\t$rt, $addr");
list<dag> Pattern = [(store COP2Opnd:$rt, addrimm11:$addr)];
Format f = FrmFI;
- InstrItinClass Itinerary = itin;
string BaseOpcode = opstr;
bit mayStore = 1;
string DecoderMethod = "DecodeFMemCop2MMR6";
}
-class SDC2_MMR6_DESC : SDC2_SWC2_MMR6_DESC_BASE<"sdc2", II_SDC2>;
-class SWC2_MMR6_DESC : SDC2_SWC2_MMR6_DESC_BASE<"swc2", II_SWC2>;
+class SDC2_MMR6_DESC : SDC2_SWC2_MMR6_DESC_BASE<"sdc2">;
+class SWC2_MMR6_DESC : SDC2_SWC2_MMR6_DESC_BASE<"swc2">;
class GINV_MMR6_DESC_BASE<string opstr,
- RegisterOperand SrcRC, InstrItinClass Itin> {
+ RegisterOperand SrcRC> {
dag InOperandList = (ins SrcRC:$rs, uimm2:$type);
dag OutOperandList = (outs);
string AsmString = !strconcat(opstr, "\t$rs, $type");
list<dag> Pattern = [];
Format f = FrmFR;
string BaseOpcode = opstr;
- InstrItinClass Itinerary = Itin;
}
-class GINVI_MMR6_DESC : GINV_MMR6_DESC_BASE<"ginvi", GPR32Opnd,
- II_GINVI> {
+class GINVI_MMR6_DESC : GINV_MMR6_DESC_BASE<"ginvi", GPR32Opnd> {
bits<2> type = 0b00;
dag InOperandList = (ins GPR32Opnd:$rs);
string AsmString = "ginvi\t$rs";
}
-class GINVT_MMR6_DESC : GINV_MMR6_DESC_BASE<"ginvt", GPR32Opnd,
- II_GINVT>;
+class GINVT_MMR6_DESC : GINV_MMR6_DESC_BASE<"ginvt", GPR32Opnd>;
-class SC_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
+class SC_MMR6_DESC_BASE<string opstr> {
dag OutOperandList = (outs GPR32Opnd:$dst);
dag InOperandList = (ins GPR32Opnd:$rt, mem_mm_9:$addr);
string AsmString = !strconcat(opstr, "\t$rt, $addr");
- InstrItinClass Itinerary = itin;
string BaseOpcode = opstr;
bit mayStore = 1;
string Constraints = "$rt = $dst";
string DecoderMethod = "DecodeMemMMImm9";
}
-class LL_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
+class LL_MMR6_DESC_BASE<string opstr> {
dag OutOperandList = (outs GPR32Opnd:$rt);
dag InOperandList = (ins mem_mm_9:$addr);
string AsmString = !strconcat(opstr, "\t$rt, $addr");
- InstrItinClass Itinerary = itin;
string BaseOpcode = opstr;
bit mayLoad = 1;
string DecoderMethod = "DecodeMemMMImm9";
}
-class SC_MMR6_DESC : SC_MMR6_DESC_BASE<"sc", II_SC>;
-class LL_MMR6_DESC : LL_MMR6_DESC_BASE<"ll", II_LL>;
+class SC_MMR6_DESC : SC_MMR6_DESC_BASE<"sc">;
+class LL_MMR6_DESC : LL_MMR6_DESC_BASE<"ll">;
/// Floating Point Instructions
class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC,
- InstrItinClass Itin, bit isComm,
+ bit isComm,
SDPatternOperator OpNode = null_frag> : HARDFLOAT {
dag OutOperandList = (outs RC:$fd);
dag InOperandList = (ins RC:$ft, RC:$fs);
string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
list<dag> Pattern = [(set RC:$fd, (OpNode RC:$fs, RC:$ft))];
- InstrItinClass Itinerary = Itin;
bit isCommutable = isComm;
}
class FADD_S_MMR6_DESC
- : FARITH_MMR6_DESC_BASE<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>;
+ : FARITH_MMR6_DESC_BASE<"add.s", FGR32Opnd, 1, fadd>;
class FSUB_S_MMR6_DESC
- : FARITH_MMR6_DESC_BASE<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>;
+ : FARITH_MMR6_DESC_BASE<"sub.s", FGR32Opnd, 0, fsub>;
class FMUL_S_MMR6_DESC
- : FARITH_MMR6_DESC_BASE<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>;
+ : FARITH_MMR6_DESC_BASE<"mul.s", FGR32Opnd, 1, fmul>;
class FDIV_S_MMR6_DESC
- : FARITH_MMR6_DESC_BASE<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>;
-class MADDF_S_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd,
- II_MADDF_S>, HARDFLOAT;
-class MADDF_D_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd,
- II_MADDF_D>, HARDFLOAT;
-class MSUBF_S_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd,
- II_MSUBF_S>, HARDFLOAT;
-class MSUBF_D_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd,
- II_MSUBF_D>, HARDFLOAT;
+ : FARITH_MMR6_DESC_BASE<"div.s", FGR32Opnd, 0, fdiv>;
+class MADDF_S_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>, HARDFLOAT;
+class MADDF_D_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>, HARDFLOAT;
+class MSUBF_S_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>, HARDFLOAT;
+class MSUBF_D_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>, HARDFLOAT;
class FMOV_FNEG_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
- RegisterOperand SrcRC, InstrItinClass Itin,
+ RegisterOperand SrcRC,
SDPatternOperator OpNode = null_frag>
: HARDFLOAT, NeverHasSideEffects {
dag OutOperandList = (outs DstRC:$ft);
dag InOperandList = (ins SrcRC:$fs);
string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
- InstrItinClass Itinerary = Itin;
Format Form = FrmFR;
}
class FMOV_S_MMR6_DESC
- : FMOV_FNEG_MMR6_DESC_BASE<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>;
+ : FMOV_FNEG_MMR6_DESC_BASE<"mov.s", FGR32Opnd, FGR32Opnd>;
class FMOV_D_MMR6_DESC
- : FMOV_FNEG_MMR6_DESC_BASE<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>;
+ : FMOV_FNEG_MMR6_DESC_BASE<"mov.d", FGR64Opnd, FGR64Opnd>;
class FNEG_S_MMR6_DESC
- : FMOV_FNEG_MMR6_DESC_BASE<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>;
+ : FMOV_FNEG_MMR6_DESC_BASE<"neg.s", FGR32Opnd, FGR32Opnd, fneg>;
-class MAX_S_MMR6_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd, II_MAX_S>,
+class MAX_S_MMR6_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>,
HARDFLOAT;
-class MAX_D_MMR6_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd, II_MAX_D>,
+class MAX_D_MMR6_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>,
HARDFLOAT;
-class MIN_S_MMR6_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd, II_MIN_S>,
+class MIN_S_MMR6_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>,
HARDFLOAT;
-class MIN_D_MMR6_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd, II_MIN_D>,
+class MIN_D_MMR6_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>,
HARDFLOAT;
-class MAXA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd, II_MAXA_S>,
+class MAXA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>,
HARDFLOAT;
-class MAXA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd, II_MAXA_D>,
+class MAXA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>,
HARDFLOAT;
-class MINA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd, II_MINA_S>,
+class MINA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>,
HARDFLOAT;
-class MINA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd, II_MINA_D>,
+class MINA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>,
HARDFLOAT;
class CVT_MMR6_DESC_BASE<
string instr_asm, RegisterOperand DstRC, RegisterOperand SrcRC,
- InstrItinClass Itin, SDPatternOperator OpNode = null_frag>
+ SDPatternOperator OpNode = null_frag>
: HARDFLOAT, NeverHasSideEffects {
dag OutOperandList = (outs DstRC:$ft);
dag InOperandList = (ins SrcRC:$fs);
string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
- InstrItinClass Itinerary = Itin;
Format Form = FrmFR;
}
-class CVT_L_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.s", FGR64Opnd, FGR32Opnd,
- II_CVT>;
-class CVT_L_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.d", FGR64Opnd, FGR64Opnd,
- II_CVT>;
-class CVT_W_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.s", FGR32Opnd, FGR32Opnd,
- II_CVT>;
-class CVT_D_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.l", FGR64Opnd, FGR64Opnd,
- II_CVT>, FGR_64;
-class CVT_S_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.w", FGR32Opnd, FGR32Opnd,
- II_CVT>;
-class CVT_S_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.l", FGR64Opnd, FGR32Opnd,
- II_CVT>, FGR_64;
+class CVT_L_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.s", FGR64Opnd, FGR32Opnd>;
+class CVT_L_D_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.l.d", FGR64Opnd, FGR64Opnd>;
+class CVT_W_S_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.w.s", FGR32Opnd, FGR32Opnd>;
+class CVT_D_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.d.l", FGR64Opnd, FGR64Opnd>,
+ FGR_64;
+class CVT_S_W_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.w", FGR32Opnd, FGR32Opnd>;
+class CVT_S_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.l", FGR64Opnd, FGR32Opnd>,
+ FGR_64;
multiclass CMP_CC_MMR6<bits<6> format, string Typestr,
RegisterOperand FGROpnd,
- RegisterOperand FGRCCOpnd,
- InstrItinClass Itin> {
+ RegisterOperand FGRCCOpnd> {
def CMP_AF_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.af.", Typestr), format, FIELD_CMP_COND_AF>,
- CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd, FGRCCOpnd, Itin>, HARDFLOAT,
+ CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd, FGRCCOpnd>, HARDFLOAT,
ISA_MICROMIPS32R6;
def CMP_UN_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.un.", Typestr), format, FIELD_CMP_COND_UN>,
- CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, FGRCCOpnd, Itin, setuo>, HARDFLOAT,
+ CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, FGRCCOpnd, setuo>, HARDFLOAT,
ISA_MICROMIPS32R6;
def CMP_EQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.eq.", Typestr), format, FIELD_CMP_COND_EQ>,
- CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, FGRCCOpnd, Itin, setoeq>, HARDFLOAT,
+ CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, FGRCCOpnd, setoeq>, HARDFLOAT,
ISA_MICROMIPS32R6;
def CMP_UEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.ueq.", Typestr), format, FIELD_CMP_COND_UEQ>,
- CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, FGRCCOpnd, Itin, setueq>, HARDFLOAT,
+ CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, FGRCCOpnd, setueq>, HARDFLOAT,
ISA_MICROMIPS32R6;
def CMP_LT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.lt.", Typestr), format, FIELD_CMP_COND_LT>,
- CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, FGRCCOpnd, Itin, setolt>, HARDFLOAT,
+ CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, FGRCCOpnd, setolt>, HARDFLOAT,
ISA_MICROMIPS32R6;
def CMP_ULT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.ult.", Typestr), format, FIELD_CMP_COND_ULT>,
- CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, FGRCCOpnd, Itin, setult>, HARDFLOAT,
+ CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, FGRCCOpnd, setult>, HARDFLOAT,
ISA_MICROMIPS32R6;
def CMP_LE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.le.", Typestr), format, FIELD_CMP_COND_LE>,
- CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, FGRCCOpnd, Itin, setole>, HARDFLOAT,
+ CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, FGRCCOpnd, setole>, HARDFLOAT,
ISA_MICROMIPS32R6;
def CMP_ULE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.ule.", Typestr), format, FIELD_CMP_COND_ULE>,
- CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, FGRCCOpnd, Itin, setule>, HARDFLOAT,
+ CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, FGRCCOpnd, setule>, HARDFLOAT,
ISA_MICROMIPS32R6;
let mayRaiseFPException = 1 in {
def CMP_SAF_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.saf.", Typestr), format, FIELD_CMP_COND_SAF>,
- CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd, FGRCCOpnd, Itin>, HARDFLOAT,
+ CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd, FGRCCOpnd>, HARDFLOAT,
ISA_MICROMIPS32R6;
def CMP_SUN_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.sun.", Typestr), format, FIELD_CMP_COND_SUN>,
- CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd, FGRCCOpnd, Itin>, HARDFLOAT,
+ CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd, FGRCCOpnd>, HARDFLOAT,
ISA_MICROMIPS32R6;
def CMP_SEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.seq.", Typestr), format, FIELD_CMP_COND_SEQ>,
- CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd, FGRCCOpnd, Itin>, HARDFLOAT,
+ CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd, FGRCCOpnd>, HARDFLOAT,
ISA_MICROMIPS32R6;
def CMP_SUEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.sueq.", Typestr), format, FIELD_CMP_COND_SUEQ>,
- CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd, FGRCCOpnd, Itin>, HARDFLOAT,
+ CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd, FGRCCOpnd>, HARDFLOAT,
ISA_MICROMIPS32R6;
def CMP_SLT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.slt.", Typestr), format, FIELD_CMP_COND_SLT>,
- CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd, FGRCCOpnd, Itin>, HARDFLOAT,
+ CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd, FGRCCOpnd>, HARDFLOAT,
ISA_MICROMIPS32R6;
def CMP_SULT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.sult.", Typestr), format, FIELD_CMP_COND_SULT>,
- CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd, FGRCCOpnd, Itin>, HARDFLOAT,
+ CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd, FGRCCOpnd>, HARDFLOAT,
ISA_MICROMIPS32R6;
def CMP_SLE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.sle.", Typestr), format, FIELD_CMP_COND_SLE>,
- CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd, FGRCCOpnd, Itin>, HARDFLOAT,
+ CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd, FGRCCOpnd>, HARDFLOAT,
ISA_MICROMIPS32R6;
def CMP_SULE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.sule.", Typestr), format, FIELD_CMP_COND_SULE>,
- CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd, FGRCCOpnd, Itin>, HARDFLOAT,
+ CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd, FGRCCOpnd>, HARDFLOAT,
ISA_MICROMIPS32R6;
}
}
class ABSS_FT_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
- RegisterOperand SrcRC, InstrItinClass Itin,
+ RegisterOperand SrcRC,
SDPatternOperator OpNode = null_frag>
: HARDFLOAT, NeverHasSideEffects {
dag OutOperandList = (outs DstRC:$ft);
dag InOperandList = (ins SrcRC:$fs);
string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
- InstrItinClass Itinerary = Itin;
Format Form = FrmFR;
list<Predicate> EncodingPredicates = [HasStdEnc];
}
class FLOOR_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.s", FGR64Opnd,
- FGR32Opnd, II_FLOOR>;
+ FGR32Opnd>;
class FLOOR_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.d", FGR64Opnd,
- FGR64Opnd, II_FLOOR>;
+ FGR64Opnd>;
class FLOOR_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.s", FGR32Opnd,
- FGR32Opnd, II_FLOOR>;
+ FGR32Opnd>;
class FLOOR_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.d", FGR32Opnd,
- AFGR64Opnd, II_FLOOR>;
+ AFGR64Opnd>;
class CEIL_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.s", FGR64Opnd,
- FGR32Opnd, II_CEIL>;
+ FGR32Opnd>;
class CEIL_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.d", FGR64Opnd,
- FGR64Opnd, II_CEIL>;
+ FGR64Opnd>;
class CEIL_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.s", FGR32Opnd,
- FGR32Opnd, II_CEIL>;
+ FGR32Opnd>;
class CEIL_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.d", FGR32Opnd,
- AFGR64Opnd, II_CEIL>;
+ AFGR64Opnd>;
class TRUNC_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.s", FGR64Opnd,
- FGR32Opnd, II_TRUNC>;
+ FGR32Opnd>;
class TRUNC_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.d", FGR64Opnd,
- FGR64Opnd, II_TRUNC>;
+ FGR64Opnd>;
class TRUNC_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.s", FGR32Opnd,
- FGR32Opnd, II_TRUNC>;
+ FGR32Opnd>;
class TRUNC_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.d", FGR32Opnd,
- FGR64Opnd, II_TRUNC>;
+ FGR64Opnd>;
class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd,
- II_SQRT_S, fsqrt>;
+ fsqrt>;
class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd,
- AFGR64Opnd, II_SQRT_D, fsqrt>;
+ AFGR64Opnd, fsqrt>;
class ROUND_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.s", FGR64Opnd,
- FGR32Opnd, II_ROUND>;
+ FGR32Opnd>;
class ROUND_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.d", FGR64Opnd,
- FGR64Opnd, II_ROUND>;
+ FGR64Opnd>;
class ROUND_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.s", FGR32Opnd,
- FGR32Opnd, II_ROUND>;
+ FGR32Opnd>;
class ROUND_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.d", FGR64Opnd,
- FGR64Opnd, II_ROUND>;
-
-class SEL_S_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd, FGR32CCOpnd, II_SEL_S>;
-class SEL_D_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd, FGR64CCOpnd, II_SEL_D>;
-
-class SELEQZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd,
- II_SELCCZ_S>;
-class SELEQZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd,
- II_SELCCZ_D>;
-class SELNEZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd,
- II_SELCCZ_S>;
-class SELNEZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd,
- II_SELCCZ_D>;
-class RINT_S_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd,
- II_RINT_S>;
-class RINT_D_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd,
- II_RINT_S>;
-class CLASS_S_MMR6_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd,
- II_CLASS_S>;
-class CLASS_D_MMR6_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd,
- II_CLASS_S>;
-
-class STORE_MMR6_DESC_BASE<string opstr, DAGOperand RO,
- InstrItinClass Itin>
+ FGR64Opnd>;
+
+class SEL_S_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd, FGR32CCOpnd>;
+class SEL_D_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd, FGR64CCOpnd>;
+
+class SELEQZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>;
+class SELEQZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>;
+class SELNEZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>;
+class SELNEZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>;
+class RINT_S_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>;
+class RINT_D_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>;
+class CLASS_S_MMR6_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>;
+class CLASS_D_MMR6_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>;
+
+class STORE_MMR6_DESC_BASE<string opstr, DAGOperand RO>
: Store<opstr, RO>, MMR6Arch<opstr> {
let DecoderMethod = "DecodeMemMMImm16";
- InstrItinClass Itinerary = Itin;
}
-class SB_MMR6_DESC : STORE_MMR6_DESC_BASE<"sb", GPR32Opnd, II_SB>;
+class SB_MMR6_DESC : STORE_MMR6_DESC_BASE<"sb", GPR32Opnd>;
-class SH_MMR6_DESC : STORE_MMR6_DESC_BASE<"sh", GPR32Opnd, II_SH>;
-class ADDU16_MMR6_DESC : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
+class SH_MMR6_DESC : STORE_MMR6_DESC_BASE<"sh", GPR32Opnd>;
+class ADDU16_MMR6_DESC : ArithRMM16<"addu16", GPRMM16Opnd, 1, add>,
MMR6Arch<"addu16"> {
int AddedComplexity = 1;
}
-class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd, II_AND>,
+class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd>,
MMR6Arch<"and16">;
-class ANDI16_MMR6_DESC : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>,
+class ANDI16_MMR6_DESC : AndImmMM16<"andi16", GPRMM16Opnd>,
MMR6Arch<"andi16">;
class NOT16_MMR6_DESC : NotMM16<"not16", GPRMM16Opnd>, MMR6Arch<"not16"> {
int AddedComplexity = 1;
}
-class OR16_MMR6_DESC : LogicRMM16<"or16", GPRMM16Opnd, II_OR>, MMR6Arch<"or16">;
-class SLL16_MMR6_DESC : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
+class OR16_MMR6_DESC : LogicRMM16<"or16", GPRMM16Opnd>, MMR6Arch<"or16">;
+class SLL16_MMR6_DESC : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd>,
MMR6Arch<"sll16">;
-class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
+class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd>,
MMR6Arch<"srl16">;
-class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16", II_BREAK>,
+class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16">,
MMR6Arch<"break16">;
class LI16_MMR6_DESC : LoadImmMM16<"li16", li16_imm, GPRMM16Opnd>,
MMR6Arch<"li16">, IsAsCheapAsAMove;
@@ -1118,13 +1041,13 @@ class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"move16">;
class MOVEP_MMR6_DESC : MovePMM16<"movep", GPRMM16OpndMovePPairFirst,
GPRMM16OpndMovePPairSecond, GPRMM16OpndMoveP>,
MMR6Arch<"movep">;
-class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16", II_SDBBP>,
+class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16">,
MMR6Arch<"sdbbp16">;
-class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
+class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, sub>,
MMR6Arch<"subu16"> {
int AddedComplexity = 1;
}
-class XOR16_MMR6_DESC : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR>,
+class XOR16_MMR6_DESC : LogicRMM16<"xor16", GPRMM16Opnd>,
MMR6Arch<"xor16">;
class LW_MMR6_DESC : MMR6Arch<"lw">, MipsR6Inst {
@@ -1135,7 +1058,6 @@ class LW_MMR6_DESC : MMR6Arch<"lw">, MipsR6Inst {
let canFoldAsLoad = 1;
let mayLoad = 1;
list<dag> Pattern = [(set GPR32Opnd:$rt, (load addrDefault:$addr))];
- InstrItinClass Itinerary = II_LW;
}
class LUI_MMR6_DESC : IsAsCheapAsAMove, MMR6Arch<"lui">, MipsR6Inst{
@@ -1145,7 +1067,6 @@ class LUI_MMR6_DESC : IsAsCheapAsAMove, MMR6Arch<"lui">, MipsR6Inst{
list<dag> Pattern = [];
bit hasSideEffects = 0;
bit isReMaterializable = 1;
- InstrItinClass Itinerary = II_LUI;
Format Form = FrmI;
}
@@ -1154,7 +1075,6 @@ class SYNC_MMR6_DESC : MMR6Arch<"sync">, MipsR6Inst {
dag InOperandList = (ins uimm5:$stype);
string AsmString = !strconcat("sync", "\t$stype");
list<dag> Pattern = [(MipsSync immZExt5:$stype)];
- InstrItinClass Itinerary = II_SYNC;
bit HasSideEffects = 1;
}
@@ -1166,7 +1086,6 @@ class RDPGPR_MMR6_DESC : MMR6Arch<"rdpgpr">, MipsR6Inst {
dag OutOperandList = (outs GPR32Opnd:$rt);
dag InOperandList = (ins GPR32Opnd:$rd);
string AsmString = !strconcat("rdpgpr", "\t$rt, $rd");
- InstrItinClass Itinerary = II_RDPGPR;
}
class SDBBP_MMR6_DESC : MipsR6Inst {
@@ -1174,7 +1093,6 @@ class SDBBP_MMR6_DESC : MipsR6Inst {
dag InOperandList = (ins uimm20:$code_);
string AsmString = !strconcat("sdbbp", "\t$code_");
list<dag> Pattern = [];
- InstrItinClass Itinerary = II_SDBBP;
}
class SIGRIE_MMR6_DESC : MipsR6Inst {
@@ -1182,13 +1100,12 @@ class SIGRIE_MMR6_DESC : MipsR6Inst {
dag InOperandList = (ins uimm16:$code_);
string AsmString = !strconcat("sigrie", "\t$code_");
list<dag> Pattern = [];
- InstrItinClass Itinerary = II_SIGRIE;
}
class LWM16_MMR6_DESC
: MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
!strconcat("lwm16", "\t$rt, $addr"), [],
- II_LWM, FrmI>,
+ FrmI>,
MMR6Arch<"lwm16"> {
let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
let mayLoad = 1;
@@ -1198,7 +1115,7 @@ class LWM16_MMR6_DESC
class SWM16_MMR6_DESC
: MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr),
!strconcat("swm16", "\t$rt, $addr"), [],
- II_SWM, FrmI>,
+ FrmI>,
MMR6Arch<"swm16"> {
let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
let mayStore = 1;
@@ -1206,24 +1123,24 @@ class SWM16_MMR6_DESC
}
class SB16_MMR6_DESC_BASE<string opstr, DAGOperand RTOpnd,
- InstrItinClass Itin, Operand MemOpnd>
+ Operand MemOpnd>
: MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
- !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI>,
+ !strconcat(opstr, "\t$rt, $addr"), [], FrmI>,
MMR6Arch<opstr> {
let DecoderMethod = "DecodeMemMMImm4";
let mayStore = 1;
}
class SB16_MMR6_DESC
- : SB16_MMR6_DESC_BASE<"sb16", GPRMM16OpndZero, II_SB, mem_mm_4>;
+ : SB16_MMR6_DESC_BASE<"sb16", GPRMM16OpndZero, mem_mm_4>;
class SH16_MMR6_DESC
- : SB16_MMR6_DESC_BASE<"sh16", GPRMM16OpndZero, II_SH, mem_mm_4_lsl1>;
+ : SB16_MMR6_DESC_BASE<"sh16", GPRMM16OpndZero, mem_mm_4_lsl1>;
class SW16_MMR6_DESC
- : SB16_MMR6_DESC_BASE<"sw16", GPRMM16OpndZero, II_SW, mem_mm_4_lsl2>;
+ : SB16_MMR6_DESC_BASE<"sw16", GPRMM16OpndZero, mem_mm_4_lsl2>;
class SWSP_MMR6_DESC
: MicroMipsInst16<(outs), (ins GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset),
- !strconcat("sw", "\t$rt, $offset"), [], II_SW, FrmI>,
+ !strconcat("sw", "\t$rt, $offset"), [], FrmI>,
MMR6Arch<"swsp"> {
let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
let mayStore = 1;
@@ -1234,34 +1151,31 @@ class JALRC_HB_MMR6_DESC {
dag InOperandList = (ins GPR32Opnd:$rs);
string AsmString = !strconcat("jalrc.hb", "\t$rt, $rs");
list<dag> Pattern = [];
- InstrItinClass Itinerary = II_JALR_HB;
Format Form = FrmJ;
bit isIndirectBranch = 1;
bit hasDelaySlot = 0;
}
-class TLBINV_MMR6_DESC_BASE<string opstr, InstrItinClass Itin> {
+class TLBINV_MMR6_DESC_BASE<string opstr> {
dag OutOperandList = (outs);
dag InOperandList = (ins);
string AsmString = opstr;
list<dag> Pattern = [];
- InstrItinClass Itinerary = Itin;
}
-class TLBINV_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinv", II_TLBINV>;
-class TLBINVF_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinvf", II_TLBINVF>;
+class TLBINV_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinv">;
+class TLBINVF_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinvf">;
-class DVPEVP_MMR6_DESC_BASE<string opstr, InstrItinClass Itin> {
+class DVPEVP_MMR6_DESC_BASE<string opstr> {
dag OutOperandList = (outs GPR32Opnd:$rs);
dag InOperandList = (ins);
string AsmString = !strconcat(opstr, "\t$rs");
list<dag> Pattern = [];
- InstrItinClass Itinerary = Itin;
bit hasUnModeledSideEffects = 1;
}
-class DVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"dvp", II_DVP>;
-class EVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"evp", II_EVP>;
+class DVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"dvp">;
+class EVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"evp">;
class BEQZC_MMR6_DESC
: CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21_mm, GPR32Opnd>,
@@ -1272,7 +1186,7 @@ class BNEZC_MMR6_DESC
class BRANCH_COP1_MMR6_DESC_BASE<string opstr> :
InstSE<(outs), (ins FGR64Opnd:$rt, brtarget_mm:$offset),
- !strconcat(opstr, "\t$rt, $offset"), [], II_BC1CCZ, FrmI>,
+ !strconcat(opstr, "\t$rt, $offset"), [], FrmI>,
HARDFLOAT, BRANCH_DESC_BASE {
list<Register> Defs = [AT];
}
@@ -1280,17 +1194,16 @@ class BRANCH_COP1_MMR6_DESC_BASE<string opstr> :
class BC1EQZC_MMR6_DESC : BRANCH_COP1_MMR6_DESC_BASE<"bc1eqzc">;
class BC1NEZC_MMR6_DESC : BRANCH_COP1_MMR6_DESC_BASE<"bc1nezc">;
-class BRANCH_COP2_MMR6_DESC_BASE<string opstr, InstrItinClass Itin>
+class BRANCH_COP2_MMR6_DESC_BASE<string opstr>
: BRANCH_DESC_BASE {
dag InOperandList = (ins COP2Opnd:$rt, brtarget_mm:$offset);
dag OutOperandList = (outs);
string AsmString = !strconcat(opstr, "\t$rt, $offset");
list<Register> Defs = [AT];
- InstrItinClass Itinerary = Itin;
}
-class BC2EQZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2eqzc", II_BC2CCZ>;
-class BC2NEZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2nezc", II_BC2CCZ>;
+class BC2EQZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2eqzc">;
+class BC2NEZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2nezc">;
class EXT_MMR6_DESC {
dag OutOperandList = (outs GPR32Opnd:$rt);
@@ -1298,7 +1211,6 @@ class EXT_MMR6_DESC {
string AsmString = !strconcat("ext", "\t$rt, $rs, $pos, $size");
list<dag> Pattern = [(set GPR32Opnd:$rt, (MipsExt GPR32Opnd:$rs, imm:$pos,
imm:$size))];
- InstrItinClass Itinerary = II_EXT;
Format Form = FrmR;
string BaseOpcode = "ext";
}
@@ -1310,7 +1222,6 @@ class INS_MMR6_DESC {
string AsmString = !strconcat("ins", "\t$rt, $rs, $pos, $size");
list<dag> Pattern = [(set GPR32Opnd:$rt, (MipsIns GPR32Opnd:$rs, imm:$pos,
imm:$size, GPR32Opnd:$src))];
- InstrItinClass Itinerary = II_INS;
Format Form = FrmR;
string BaseOpcode = "ins";
string Constraints = "$src = $rt";
@@ -1321,7 +1232,6 @@ class JALRC_MMR6_DESC {
dag InOperandList = (ins GPR32Opnd:$rs);
string AsmString = !strconcat("jalrc", "\t$rt, $rs");
list<dag> Pattern = [];
- InstrItinClass Itinerary = II_JALRC;
bit isCall = 1;
bit hasDelaySlot = 0;
list<Register> Defs = [RA];
@@ -1334,7 +1244,6 @@ class BOVC_BNVC_MMR6_DESC_BASE<string instr_asm, Operand opnd,
dag OutOperandList = (outs);
string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $offset");
list<Register> Defs = [AT];
- InstrItinClass Itinerary = II_BCCC;
}
class BOVC_MMR6_DESC : BOVC_BNVC_MMR6_DESC_BASE<"bovc", brtargetr6, GPR32Opnd>;
@@ -1514,8 +1423,8 @@ let mayRaiseFPException = 1 in {
}
}
-defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd, FGR32CCOpnd, II_CMP_CC_S>;
-defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd, FGR64CCOpnd, II_CMP_CC_D>;
+defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd, FGR32CCOpnd>;
+defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd, FGR64CCOpnd>;
let mayRaiseFPException = 1 in {
def FLOOR_L_S_MMR6 : StdMMR6Rel, FLOOR_L_S_MMR6_ENC, FLOOR_L_S_MMR6_DESC,
ISA_MICROMIPS32R6;
@@ -1808,7 +1717,7 @@ let AddedComplexity = 41 in {
let isCall=1, hasDelaySlot=0, isCTI=1, Defs = [RA] in {
class JumpLinkMMR6<Instruction JumpInst, DAGOperand Opnd> :
- PseudoSE<(outs), (ins calltarget:$target), [], II_JAL>,
+ PseudoSE<(outs), (ins calltarget:$target), []>,
PseudoInstExpansion<(JumpInst Opnd:$target)>;
}
diff --git a/llvm/lib/Target/Mips/MicroMipsDSPInstrFormats.td b/llvm/lib/Target/Mips/MicroMipsDSPInstrFormats.td
index 26b6cf8994ca0..029ab2472f900 100644
--- a/llvm/lib/Target/Mips/MicroMipsDSPInstrFormats.td
+++ b/llvm/lib/Target/Mips/MicroMipsDSPInstrFormats.td
@@ -7,7 +7,7 @@
//===----------------------------------------------------------------------===//
class MMDSPInst<string opstr = "">
- : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
+ : MipsInst<(outs), (ins), "", [], FrmOther> {
let ASEPredicate = [HasDSP];
let EncodingPredicates = [InMicroMips];
string BaseOpcode = opstr;
diff --git a/llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td
index f7d0105f4d7d2..cb0def7a6d5e4 100644
--- a/llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td
+++ b/llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td
@@ -177,121 +177,116 @@ class CMPU_LE_QB_MM_ENC : POOL32A_2R2B0_FMT<"cmpu.le.qb", 0b1011000101>;
// Instruction desc.
class ABSQ_S_PH_MM_R2_DESC_BASE<string opstr, SDPatternOperator OpNode,
- InstrItinClass itin, RegisterOperand ROD,
+ RegisterOperand ROD,
RegisterOperand ROS = ROD> {
dag OutOperandList = (outs ROD:$rt);
dag InOperandList = (ins ROS:$rs);
string AsmString = !strconcat(opstr, "\t$rt, $rs");
list<dag> Pattern = [(set ROD:$rt, (OpNode ROS:$rs))];
- InstrItinClass Itinerary = itin;
}
class ABSQ_S_PH_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
- "absq_s.ph", int_mips_absq_s_ph, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag20]>;
+ "absq_s.ph", int_mips_absq_s_ph, DSPROpnd>, Defs<[DSPOutFlag20]>;
class ABSQ_S_W_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
- "absq_s.w", int_mips_absq_s_w, NoItinerary, GPR32Opnd>, Defs<[DSPOutFlag20]>;
+ "absq_s.w", int_mips_absq_s_w, GPR32Opnd>, Defs<[DSPOutFlag20]>;
class ABSQ_S_QB_MMR2_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
- "absq_s.qb", int_mips_absq_s_qb, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag20]>;
+ "absq_s.qb", int_mips_absq_s_qb, DSPROpnd>, Defs<[DSPOutFlag20]>;
class PRECEQ_W_PHL_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
- "preceq.w.phl", int_mips_preceq_w_phl, NoItinerary, GPR32Opnd, DSPROpnd>;
+ "preceq.w.phl", int_mips_preceq_w_phl, GPR32Opnd, DSPROpnd>;
class PRECEQ_W_PHR_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
- "preceq.w.phr", int_mips_preceq_w_phr, NoItinerary, GPR32Opnd, DSPROpnd>;
+ "preceq.w.phr", int_mips_preceq_w_phr, GPR32Opnd, DSPROpnd>;
class PRECEQU_PH_QBL_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
- "precequ.ph.qbl", int_mips_precequ_ph_qbl, NoItinerary, DSPROpnd>;
+ "precequ.ph.qbl", int_mips_precequ_ph_qbl, DSPROpnd>;
class PRECEQU_PH_QBLA_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
- "precequ.ph.qbla", int_mips_precequ_ph_qbla, NoItinerary, DSPROpnd>;
+ "precequ.ph.qbla", int_mips_precequ_ph_qbla, DSPROpnd>;
class PRECEQU_PH_QBR_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
- "precequ.ph.qbr", int_mips_precequ_ph_qbr, NoItinerary, DSPROpnd>;
+ "precequ.ph.qbr", int_mips_precequ_ph_qbr, DSPROpnd>;
class PRECEQU_PH_QBRA_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
- "precequ.ph.qbra", int_mips_precequ_ph_qbra, NoItinerary, DSPROpnd>;
+ "precequ.ph.qbra", int_mips_precequ_ph_qbra, DSPROpnd>;
class PRECEU_PH_QBL_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
- "preceu.ph.qbl", int_mips_preceu_ph_qbl, NoItinerary, DSPROpnd>;
+ "preceu.ph.qbl", int_mips_preceu_ph_qbl, DSPROpnd>;
class PRECEU_PH_QBLA_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
- "preceu.ph.qbla", int_mips_preceu_ph_qbla, NoItinerary, DSPROpnd>;
+ "preceu.ph.qbla", int_mips_preceu_ph_qbla, DSPROpnd>;
class PRECEU_PH_QBR_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
- "preceu.ph.qbr", int_mips_preceu_ph_qbr, NoItinerary, DSPROpnd>;
+ "preceu.ph.qbr", int_mips_preceu_ph_qbr, DSPROpnd>;
class PRECEU_PH_QBRA_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
- "preceu.ph.qbra", int_mips_preceu_ph_qbra, NoItinerary, DSPROpnd>;
+ "preceu.ph.qbra", int_mips_preceu_ph_qbra, DSPROpnd>;
class SHLL_R2_MM_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
- SDPatternOperator ImmPat, InstrItinClass itin,
+ SDPatternOperator ImmPat,
RegisterOperand RO, Operand ImmOpnd> {
dag OutOperandList = (outs RO:$rt);
dag InOperandList = (ins RO:$rs, ImmOpnd:$sa);
string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
list<dag> Pattern = [(set RO:$rt, (OpNode RO:$rs, ImmPat:$sa))];
- InstrItinClass Itinerary = itin;
bit hasSideEffects = 1;
}
class SHLL_PH_MM_DESC : SHLL_R2_MM_DESC_BASE<
- "shll.ph", null_frag, immZExt4, NoItinerary, DSPROpnd, uimm4>,
+ "shll.ph", null_frag, immZExt4, DSPROpnd, uimm4>,
Defs<[DSPOutFlag22]>;
class SHLL_S_PH_MM_DESC : SHLL_R2_MM_DESC_BASE<
- "shll_s.ph", int_mips_shll_s_ph, immZExt4, NoItinerary, DSPROpnd, uimm4>,
+ "shll_s.ph", int_mips_shll_s_ph, immZExt4, DSPROpnd, uimm4>,
Defs<[DSPOutFlag22]>;
class SHLL_QB_MM_DESC : SHLL_R2_MM_DESC_BASE<
- "shll.qb", null_frag, immZExt3, NoItinerary, DSPROpnd, uimm3>,
+ "shll.qb", null_frag, immZExt3, DSPROpnd, uimm3>,
Defs<[DSPOutFlag22]>;
class SHLL_S_W_MM_DESC : SHLL_R2_MM_DESC_BASE<
- "shll_s.w", int_mips_shll_s_w, immZExt5, NoItinerary, GPR32Opnd, uimm5>,
+ "shll_s.w", int_mips_shll_s_w, immZExt5, GPR32Opnd, uimm5>,
Defs<[DSPOutFlag22]>;
class SHRA_QB_MMR2_DESC : SHLL_R2_MM_DESC_BASE<
- "shra.qb", null_frag, immZExt3, NoItinerary, DSPROpnd, uimm3>;
+ "shra.qb", null_frag, immZExt3, DSPROpnd, uimm3>;
class SHRA_R_QB_MMR2_DESC : SHLL_R2_MM_DESC_BASE<
- "shra_r.qb", int_mips_shra_r_qb, immZExt3, NoItinerary, DSPROpnd, uimm3>;
+ "shra_r.qb", int_mips_shra_r_qb, immZExt3, DSPROpnd, uimm3>;
class SHRA_PH_MM_DESC : SHLL_R2_MM_DESC_BASE<
- "shra.ph", null_frag, immZExt4, NoItinerary, DSPROpnd, uimm4>;
+ "shra.ph", null_frag, immZExt4, DSPROpnd, uimm4>;
class SHRA_R_PH_MM_DESC : SHLL_R2_MM_DESC_BASE<
- "shra_r.ph", int_mips_shra_r_ph, immZExt4, NoItinerary, DSPROpnd, uimm4>;
+ "shra_r.ph", int_mips_shra_r_ph, immZExt4, DSPROpnd, uimm4>;
class SHRA_R_W_MM_DESC : SHLL_R2_MM_DESC_BASE<
- "shra_r.w", int_mips_shra_r_w, immZExt5, NoItinerary, GPR32Opnd, uimm5>;
+ "shra_r.w", int_mips_shra_r_w, immZExt5, GPR32Opnd, uimm5>;
class SHRL_QB_MM_DESC : SHLL_R2_MM_DESC_BASE<
- "shrl.qb", null_frag, immZExt3, NoItinerary, DSPROpnd, uimm3>;
+ "shrl.qb", null_frag, immZExt3, DSPROpnd, uimm3>;
class SHRL_PH_MMR2_DESC : SHLL_R2_MM_DESC_BASE<
- "shrl.ph", null_frag, immZExt4, NoItinerary, DSPROpnd, uimm4>;
+ "shrl.ph", null_frag, immZExt4, DSPROpnd, uimm4>;
class SHLLV_R3_MM_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
- InstrItinClass itin, RegisterOperand RO> {
+ RegisterOperand RO> {
dag OutOperandList = (outs RO:$rd);
dag InOperandList = (ins RO:$rt, GPR32Opnd:$rs);
string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs");
list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))];
- InstrItinClass Itinerary = itin;
}
class SHLLV_PH_MM_DESC : SHLLV_R3_MM_DESC_BASE<
- "shllv.ph", int_mips_shll_ph, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag22]>;
+ "shllv.ph", int_mips_shll_ph, DSPROpnd>, Defs<[DSPOutFlag22]>;
class SHLLV_S_PH_MM_DESC : SHLLV_R3_MM_DESC_BASE<
- "shllv_s.ph", int_mips_shll_s_ph, NoItinerary, DSPROpnd>,
+ "shllv_s.ph", int_mips_shll_s_ph, DSPROpnd>,
Defs<[DSPOutFlag22]>;
class SHLLV_QB_MM_DESC : SHLLV_R3_MM_DESC_BASE<
- "shllv.qb", int_mips_shll_qb, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag22]>;
+ "shllv.qb", int_mips_shll_qb, DSPROpnd>, Defs<[DSPOutFlag22]>;
class SHLLV_S_W_MM_DESC : SHLLV_R3_MM_DESC_BASE<
- "shllv_s.w", int_mips_shll_s_w, NoItinerary, GPR32Opnd>, Defs<[DSPOutFlag22]>;
+ "shllv_s.w", int_mips_shll_s_w, GPR32Opnd>, Defs<[DSPOutFlag22]>;
class SHRAV_PH_MM_DESC : SHLLV_R3_MM_DESC_BASE<
- "shrav.ph", int_mips_shra_ph, NoItinerary, DSPROpnd>;
+ "shrav.ph", int_mips_shra_ph, DSPROpnd>;
class SHRAV_R_PH_MM_DESC : SHLLV_R3_MM_DESC_BASE<
- "shrav_r.ph", int_mips_shra_r_ph, NoItinerary, DSPROpnd>;
+ "shrav_r.ph", int_mips_shra_r_ph, DSPROpnd>;
class SHRAV_QB_MMR2_DESC : SHLLV_R3_MM_DESC_BASE<
- "shrav.qb", int_mips_shra_qb, NoItinerary, DSPROpnd>;
+ "shrav.qb", int_mips_shra_qb, DSPROpnd>;
class SHRAV_R_QB_MMR2_DESC : SHLLV_R3_MM_DESC_BASE<
- "shrav_r.qb", int_mips_shra_r_qb, NoItinerary, DSPROpnd>;
+ "shrav_r.qb", int_mips_shra_r_qb, DSPROpnd>;
class SHRAV_R_W_MM_DESC : SHLLV_R3_MM_DESC_BASE<
- "shrav_r.w", int_mips_shra_r_w, NoItinerary, GPR32Opnd>;
+ "shrav_r.w", int_mips_shra_r_w, GPR32Opnd>;
class SHRLV_PH_MMR2_DESC : SHLLV_R3_MM_DESC_BASE<
- "shrlv.ph", int_mips_shrl_ph, NoItinerary, DSPROpnd>;
+ "shrlv.ph", int_mips_shrl_ph, DSPROpnd>;
class SHRLV_QB_MM_DESC : SHLLV_R3_MM_DESC_BASE<
- "shrlv.qb", int_mips_shrl_qb, NoItinerary, DSPROpnd>;
+ "shrlv.qb", int_mips_shrl_qb, DSPROpnd>;
class EXT_MM_2R_DESC_BASE<string instr_asm> {
dag OutOperandList = (outs GPR32Opnd:$rt);
dag InOperandList = (ins ACC64DSPOpnd:$ac, GPR32Opnd:$rs);
string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $rs");
- InstrItinClass Itinerary = NoItinerary;
}
class EXT_MM_1R_DESC_BASE<string instr_asm> {
dag OutOperandList = (outs GPR32Opnd:$rt);
dag InOperandList = (ins ACC64DSPOpnd:$ac, uimm5:$imm);
string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $imm");
- InstrItinClass Itinerary = NoItinerary;
}
class EXTP_MM_DESC : EXT_MM_1R_DESC_BASE<"extp">,
@@ -322,26 +317,21 @@ class EXTRV_RS_W_MM_DESC : EXT_MM_2R_DESC_BASE<"extrv_rs.w">,
class EXTRV_S_H_MM_DESC : EXT_MM_2R_DESC_BASE<"extrv_s.h">,
Defs<[DSPOutFlag23]>;
-class MFHI_MM_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode,
- InstrItinClass itin> {
+class MFHI_MM_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode> {
dag OutOperandList = (outs GPR32Opnd:$rs);
dag InOperandList = (ins RO:$ac);
string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
list<dag> Pattern = [(set GPR32Opnd:$rs, (OpNode RO:$ac))];
- InstrItinClass Itinerary = itin;
}
-class MFHI_MM_DESC : MFHI_MM_DESC_BASE<"mfhi", ACC64DSPOpnd, MipsMFHI,
- NoItinerary>;
-class MFLO_MM_DESC : MFHI_MM_DESC_BASE<"mflo", ACC64DSPOpnd, MipsMFLO,
- NoItinerary>;
+class MFHI_MM_DESC : MFHI_MM_DESC_BASE<"mfhi", ACC64DSPOpnd, MipsMFHI>;
+class MFLO_MM_DESC : MFHI_MM_DESC_BASE<"mflo", ACC64DSPOpnd, MipsMFLO>;
class RADDU_W_QB_MM_DESC {
dag OutOperandList = (outs GPR32Opnd:$rt);
dag InOperandList = (ins DSPROpnd:$rs);
string AsmString = !strconcat("raddu.w.qb", "\t$rt, $rs");
list<dag> Pattern = [(set GPR32Opnd:$rt, (int_mips_raddu_w_qb DSPROpnd:$rs))];
- InstrItinClass Itinerary = NoItinerary;
string BaseOpcode = "raddu.w.qb";
}
@@ -350,7 +340,6 @@ class RDDSP_MM_DESC {
dag InOperandList = (ins uimm7:$mask);
string AsmString = !strconcat("rddsp", "\t$rt, $mask");
list<dag> Pattern = [(set GPR32Opnd:$rt, (int_mips_rddsp timmZExt7:$mask))];
- InstrItinClass Itinerary = NoItinerary;
}
class REPL_QB_MM_DESC {
@@ -358,14 +347,13 @@ class REPL_QB_MM_DESC {
dag InOperandList = (ins uimm8:$imm);
string AsmString = !strconcat("repl.qb", "\t$rt, $imm");
list<dag> Pattern = [(set DSPROpnd:$rt, (int_mips_repl_qb immZExt8:$imm))];
- InstrItinClass Itinerary = NoItinerary;
}
class REPLV_PH_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<"replv.ph", int_mips_repl_ph,
- NoItinerary, DSPROpnd,
+ DSPROpnd,
GPR32Opnd>;
class REPLV_QB_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<"replv.qb", int_mips_repl_qb,
- NoItinerary, DSPROpnd,
+ DSPROpnd,
GPR32Opnd>;
class WRDSP_MM_DESC {
@@ -373,14 +361,12 @@ class WRDSP_MM_DESC {
dag InOperandList = (ins GPR32Opnd:$rt, uimm7:$mask);
string AsmString = !strconcat("wrdsp", "\t$rt, $mask");
list<dag> Pattern = [(int_mips_wrdsp GPR32Opnd:$rt, timmZExt7:$mask)];
- InstrItinClass Itinerary = NoItinerary;
}
class BPOSGE32C_MMR3_DESC {
dag OutOperandList = (outs);
dag InOperandList = (ins brtarget1SImm16:$offset);
string AsmString = !strconcat("bposge32c", "\t$offset");
- InstrItinClass Itinerary = NoItinerary;
bit isBranch = 1;
bit isTerminator = 1;
bit hasDelaySlot = 0;
@@ -393,21 +379,19 @@ class BALIGN_MMR2_DESC {
list<dag> Pattern = [(set GPR32Opnd:$rt, (int_mips_balign GPR32Opnd:$src,
GPR32Opnd:$rs,
immZExt2:$bp))];
- InstrItinClass Itinerary = NoItinerary;
string Constraints = "$src = $rt";
}
class BITREV_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<"bitrev", int_mips_bitrev,
- NoItinerary, GPR32Opnd>;
+ GPR32Opnd>;
-class BPOSGE32_MM_DESC : BPOSGE32_DESC_BASE<"bposge32", brtarget_mm,
- NoItinerary>;
+class BPOSGE32_MM_DESC : BPOSGE32_DESC_BASE<"bposge32", brtarget_mm>;
let DecoderNamespace = "MicroMipsDSP", Arch = "mmdsp",
EncodingPredicates = [InMicroMips], ASEPredicate = [HasDSP] in {
- def LWDSP_MM : Load<"lw", DSPROpnd, null_frag, II_LW>, DspMMRel,
+ def LWDSP_MM : Load<"lw", DSPROpnd, null_frag>, DspMMRel,
LW_FM_MM<0x3f>;
- def SWDSP_MM : Store<"sw", DSPROpnd, null_frag, II_SW>, DspMMRel,
+ def SWDSP_MM : Store<"sw", DSPROpnd, null_frag>, DspMMRel,
LW_FM_MM<0x3e>;
}
// Instruction defs.
diff --git a/llvm/lib/Target/Mips/MicroMipsInstrFPU.td b/llvm/lib/Target/Mips/MicroMipsInstrFPU.td
index 62992e7b3bb28..0c4344dde095e 100644
--- a/llvm/lib/Target/Mips/MicroMipsInstrFPU.td
+++ b/llvm/lib/Target/Mips/MicroMipsInstrFPU.td
@@ -10,51 +10,51 @@
//
//===----------------------------------------------------------------------===//
-multiclass ADDS_MMM<string opstr, InstrItinClass Itin, bit IsComm,
+multiclass ADDS_MMM<string opstr, bit IsComm,
SDPatternOperator OpNode = null_frag> {
- def _D32_MM : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>,
+ def _D32_MM : MMRel, ADDS_FT<opstr, AFGR64Opnd, IsComm, OpNode>,
FGR_32 {
string DecoderNamespace = "MicroMips";
}
// FIXME: This needs to be part of the instruction mapping tables.
- def _D64_MM : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, FGR_64 {
+ def _D64_MM : ADDS_FT<opstr, FGR64Opnd, IsComm, OpNode>, FGR_64 {
string DecoderNamespace = "MicroMipsFP64";
}
}
let mayRaiseFPException = 1, Uses = [FCR31] in {
- def FADD_S_MM : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>,
+ def FADD_S_MM : MMRel, ADDS_FT<"add.s", FGR32Opnd, 1, fadd>,
ADDS_FM_MM<0, 0x30>, ISA_MICROMIPS;
- def FDIV_S_MM : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>,
+ def FDIV_S_MM : MMRel, ADDS_FT<"div.s", FGR32Opnd, 0, fdiv>,
ADDS_FM_MM<0, 0xf0>, ISA_MICROMIPS;
- def FMUL_S_MM : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>,
+ def FMUL_S_MM : MMRel, ADDS_FT<"mul.s", FGR32Opnd, 1, fmul>,
ADDS_FM_MM<0, 0xb0>, ISA_MICROMIPS;
- def FSUB_S_MM : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>,
+ def FSUB_S_MM : MMRel, ADDS_FT<"sub.s", FGR32Opnd, 0, fsub>,
ADDS_FM_MM<0, 0x70>, ISA_MICROMIPS;
- defm FADD : ADDS_MMM<"add.d", II_ADD_D, 1, fadd>,
+ defm FADD : ADDS_MMM<"add.d", 1, fadd>,
ADDS_FM_MM<1, 0x30>, ISA_MICROMIPS;
- defm FDIV : ADDS_MMM<"div.d", II_DIV_D, 0, fdiv>,
+ defm FDIV : ADDS_MMM<"div.d", 0, fdiv>,
ADDS_FM_MM<1, 0xf0>, ISA_MICROMIPS;
- defm FMUL : ADDS_MMM<"mul.d", II_MUL_D, 1, fmul>,
+ defm FMUL : ADDS_MMM<"mul.d", 1, fmul>,
ADDS_FM_MM<1, 0xb0>, ISA_MICROMIPS;
- defm FSUB : ADDS_MMM<"sub.d", II_SUB_D, 0, fsub>,
+ defm FSUB : ADDS_MMM<"sub.d", 0, fsub>,
ADDS_FM_MM<1, 0x70>, ISA_MICROMIPS;
}
let DecoderNamespace = "MicroMips" in {
- def LWXC1_MM : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>,
+ def LWXC1_MM : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, load>,
LWXC1_FM_MM<0x48>, ISA_MICROMIPS32_NOT_MIPS32R6;
- def SWXC1_MM : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>,
+ def SWXC1_MM : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, store>,
SWXC1_FM_MM<0x88>, ISA_MICROMIPS32_NOT_MIPS32R6;
- def LUXC1_MM : MMRel, LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>,
+ def LUXC1_MM : MMRel, LWXC1_FT<"luxc1", FGR64Opnd>,
LWXC1_FM_MM<0x148>, FGR_64, ISA_MICROMIPS32_NOT_MIPS32R6;
- def SUXC1_MM : MMRel, SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>,
+ def SUXC1_MM : MMRel, SWXC1_FT<"suxc1", FGR64Opnd>,
SWXC1_FM_MM<0x188>, FGR_64, ISA_MICROMIPS32_NOT_MIPS32R6;
}
let isCodeGenOnly = 1 in {
-def FCMP_S32_MM : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>,
+def FCMP_S32_MM : MMRel, CEQS_FT<"s", FGR32, MipsFPCmp>,
CEQS_FM_MM<0>, ISA_MICROMIPS32_NOT_MIPS32R6 {
// FIXME: This is a required to work around the fact that these instructions
// only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the
@@ -62,7 +62,7 @@ def FCMP_S32_MM : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>,
bits<3> fcc = 0;
}
-def FCMP_D32_MM : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>,
+def FCMP_D32_MM : MMRel, CEQS_FT<"d", AFGR64, MipsFPCmp>,
CEQS_FM_MM<1>, ISA_MICROMIPS32_NOT_MIPS32R6 {
// FIXME: This is a required to work around the fact that these instructions
// only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the
@@ -73,335 +73,328 @@ def FCMP_D32_MM : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>,
}
let DecoderNamespace = "MicroMips" in {
- def BC1F_MM : MMRel, BC1F_FT<"bc1f", brtarget_mm, II_BC1F, MIPS_BRANCH_F>,
+ def BC1F_MM : MMRel, BC1F_FT<"bc1f", brtarget_mm, MIPS_BRANCH_F>,
BC1F_FM_MM<0x1c>, ISA_MICROMIPS32_NOT_MIPS32R6;
- def BC1T_MM : MMRel, BC1F_FT<"bc1t", brtarget_mm, II_BC1T, MIPS_BRANCH_T>,
+ def BC1T_MM : MMRel, BC1F_FT<"bc1t", brtarget_mm, MIPS_BRANCH_T>,
BC1F_FM_MM<0x1d>, ISA_MICROMIPS32_NOT_MIPS32R6;
let mayRaiseFPException = 1, Uses = [FCR31] in
- def CVT_W_S_MM : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
+ def CVT_W_S_MM : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd>,
ROUND_W_FM_MM<0, 0x24>, ISA_MICROMIPS;
}
let DecoderNamespace = "MicroMips", mayRaiseFPException = 1 in {
def ROUND_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd,
- FGR32Opnd, II_ROUND>,
+ FGR32Opnd>,
ROUND_W_FM_MM<0, 0xec>, ISA_MICROMIPS;
- def CEIL_W_MM : MMRel, ABSS_FT<"ceil.w.d", FGR32Opnd, AFGR64Opnd, II_CEIL>,
+ def CEIL_W_MM : MMRel, ABSS_FT<"ceil.w.d", FGR32Opnd, AFGR64Opnd>,
ROUND_W_FM_MM<1, 0x6c>, ISA_MICROMIPS, FGR_32;
- def FLOOR_W_MM : MMRel, ABSS_FT<"floor.w.d", FGR32Opnd, AFGR64Opnd, II_FLOOR>,
+ def FLOOR_W_MM : MMRel, ABSS_FT<"floor.w.d", FGR32Opnd, AFGR64Opnd>,
ROUND_W_FM_MM<1, 0x2c>, ISA_MICROMIPS, FGR_32;
def ROUND_W_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.d", FGR32Opnd,
- AFGR64Opnd, II_ROUND>,
+ AFGR64Opnd>,
ROUND_W_FM_MM<1, 0xec>, ISA_MICROMIPS, FGR_32;
- def TRUNC_W_MM : MMRel, ABSS_FT<"trunc.w.d", FGR32Opnd, AFGR64Opnd, II_TRUNC>,
+ def TRUNC_W_MM : MMRel, ABSS_FT<"trunc.w.d", FGR32Opnd, AFGR64Opnd>,
ROUND_W_FM_MM<1, 0xac>, ISA_MICROMIPS, FGR_32;
let Uses = [FCR31] in {
- def CVT_L_S_MM : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
+ def CVT_L_S_MM : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd>,
ROUND_W_FM_MM<0, 0x4>, ISA_MICROMIPS, FGR_64;
- def CVT_L_D64_MM : MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
+ def CVT_L_D64_MM : MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd>,
ROUND_W_FM_MM<1, 0x4>, ISA_MICROMIPS, FGR_64;
- def CVT_W_D32_MM : MMRel, ABSS_FT<"cvt.w.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
+ def CVT_W_D32_MM : MMRel, ABSS_FT<"cvt.w.d", FGR32Opnd, AFGR64Opnd>,
ROUND_W_FM_MM<1, 0x24>, ISA_MICROMIPS, FGR_32;
}
}
let DecoderNamespace = "MicroMipsFP64", mayRaiseFPException = 1, Uses = [FCR31] in {
- def CVT_W_D64_MM : ABSS_FT<"cvt.w.d", FGR32Opnd, FGR64Opnd, II_CVT>,
+ def CVT_W_D64_MM : ABSS_FT<"cvt.w.d", FGR32Opnd, FGR64Opnd>,
ROUND_W_FM_MM<1, 0x24>, ISA_MICROMIPS, FGR_64;
}
-multiclass ABSS_MMM<string opstr, InstrItinClass Itin,
+multiclass ABSS_MMM<string opstr,
SDPatternOperator OpNode = null_frag> {
- def _D32_MM : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
+ def _D32_MM : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, OpNode>,
ISA_MICROMIPS, FGR_32 {
string DecoderNamespace = "MicroMips";
}
- def _D64_MM : StdMMR6Rel, ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>,
+ def _D64_MM : StdMMR6Rel, ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, OpNode>,
ISA_MICROMIPS, FGR_64 {
string DecoderNamespace = "MicroMipsFP64";
}
}
let mayRaiseFPException = 1, Uses = [FCR31] in
-defm FSQRT : ABSS_MMM<"sqrt.d", II_SQRT_D, fsqrt>, ROUND_W_FM_MM<1, 0x28>;
-defm FABS : ABSS_MMM<"abs.d", II_SQRT_D, fabs>, ABS_FM_MM<1, 0xd>;
+defm FSQRT : ABSS_MMM<"sqrt.d", fsqrt>, ROUND_W_FM_MM<1, 0x28>;
+defm FABS : ABSS_MMM<"abs.d", fabs>, ABS_FM_MM<1, 0xd>;
let DecoderNamespace = "MicroMips" in {
- def FABS_S_MM : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS>,
+ def FABS_S_MM : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, fabs>,
ABS_FM_MM<0, 0xd>, ISA_MICROMIPS;
}
def : Pat<(ABSS_FT_PatFrag<fabs> FGR32Opnd:$fs), (FABS_S_MM FGR32Opnd:$fs)>;
-def FMOV_S_MM : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,
+def FMOV_S_MM : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd>,
ABS_FM_MM<0, 0x1>, ISA_MICROMIPS {
let isMoveReg = 1;
}
-def FNEG_S_MM : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>,
+def FNEG_S_MM : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, fneg>,
ABS_FM_MM<0, 0x2d>, ISA_MICROMIPS;
let DecoderNamespace = "MicroMips", mayRaiseFPException = 1, Uses = [FCR31] in {
- def CVT_D32_S_MM : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>,
+ def CVT_D32_S_MM : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd>,
ABS_FM_MM<0, 0x4d>, ISA_MICROMIPS, FGR_32;
- def CVT_D32_W_MM : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>,
+ def CVT_D32_W_MM : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd>,
ABS_FM_MM<1, 0x4d>, ISA_MICROMIPS, FGR_32;
}
let DecoderNamespace = "MicroMipsFP64", mayRaiseFPException = 1, Uses = [FCR31] in {
- def CVT_D64_S_MM : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>,
+ def CVT_D64_S_MM : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd>,
ABS_FM_MM<0, 0x4d>, ISA_MICROMIPS, FGR_64;
- def CVT_D64_W_MM : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>,
+ def CVT_D64_W_MM : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd>,
ABS_FM_MM<1, 0x4d>, ISA_MICROMIPS, FGR_64;
- def CVT_S_D64_MM : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>,
+ def CVT_S_D64_MM : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd>,
ABS_FM_MM<0, 0x6d>, ISA_MICROMIPS, FGR_64;
}
let DecoderNamespace = "MicroMips", mayRaiseFPException = 1, Uses = [FCR31] in {
- def CVT_S_D32_MM : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
+ def CVT_S_D32_MM : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd>,
ABS_FM_MM<0, 0x6d>, ISA_MICROMIPS, FGR_32;
- def CVT_S_W_MM : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
+ def CVT_S_W_MM : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd>,
ABS_FM_MM<1, 0x6d>, ISA_MICROMIPS;
}
-defm FNEG : ABSS_MMM<"neg.d", II_NEG, fneg>, ABS_FM_MM<1, 0x2d>;
-defm FMOV : ABSS_MMM<"mov.d", II_MOV_D>, ABS_FM_MM<1, 0x1>;
+defm FNEG : ABSS_MMM<"neg.d", fneg>, ABS_FM_MM<1, 0x2d>;
+defm FMOV : ABSS_MMM<"mov.d">, ABS_FM_MM<1, 0x1>;
let DecoderNamespace = "MicroMips" in {
- def MOVZ_I_S_MM : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd,
- II_MOVZ_S>, CMov_I_F_FM_MM<0x78, 0>,
+ def MOVZ_I_S_MM : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd>,
+ CMov_I_F_FM_MM<0x78, 0>,
ISA_MICROMIPS32_NOT_MIPS32R6;
- def MOVN_I_S_MM : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd,
- II_MOVN_S>, CMov_I_F_FM_MM<0x38, 0>,
+ def MOVN_I_S_MM : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd>,
+ CMov_I_F_FM_MM<0x38, 0>,
ISA_MICROMIPS32_NOT_MIPS32R6;
- def MOVZ_I_D32_MM : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd,
- II_MOVZ_D>, CMov_I_F_FM_MM<0x78, 1>,
+ def MOVZ_I_D32_MM : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd>,
+ CMov_I_F_FM_MM<0x78, 1>,
ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
- def MOVN_I_D32_MM : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd,
- II_MOVN_D>, CMov_I_F_FM_MM<0x38, 1>,
+ def MOVN_I_D32_MM : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd>,
+ CMov_I_F_FM_MM<0x38, 1>,
ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
- def MOVT_S_MM : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S,
+ def MOVT_S_MM : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd,
MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 0>,
ISA_MICROMIPS32_NOT_MIPS32R6;
- def MOVF_S_MM : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S,
+ def MOVF_S_MM : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd,
MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 0>,
ISA_MICROMIPS32_NOT_MIPS32R6;
- def MOVT_D32_MM : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D,
- MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 1>,
- ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
- def MOVF_D32_MM : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D,
+ def MOVT_D32_MM : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd,
+ MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 1>,
+ ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
+ def MOVF_D32_MM : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd,
MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 1>,
ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd,
- II_MFC1, bitconvert>, MFC1_FM_MM<0x80>,
+ bitconvert>, MFC1_FM_MM<0x80>,
ISA_MICROMIPS;
def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd,
- II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>,
+ bitconvert>, MFC1_FM_MM<0xa0>,
ISA_MICROMIPS;
let mayRaiseFPException = 1, Uses = [FCR31] in {
- def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S>,
+ def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd>,
MADDS_FM_MM<0x1>, ISA_MICROMIPS32_NOT_MIPS32R6, MADD4;
- def MSUB_S_MM : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S>,
+ def MSUB_S_MM : MMRel, MADDS_FT<"msub.s", FGR32Opnd>,
MADDS_FM_MM<0x21>, ISA_MICROMIPS32_NOT_MIPS32R6, MADD4;
- def MADD_D32_MM : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D>,
+ def MADD_D32_MM : MMRel, MADDS_FT<"madd.d", AFGR64Opnd>,
MADDS_FM_MM<0x9>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32,
MADD4;
- def MSUB_D32_MM : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D>,
+ def MSUB_D32_MM : MMRel, MADDS_FT<"msub.d", AFGR64Opnd>,
MADDS_FM_MM<0x29>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32,
MADD4;
let AdditionalPredicates = [HasMadd4] in {
- def NMADD_S_MM : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S>,
+ def NMADD_S_MM : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd>,
MADDS_FM_MM<0x2>, ISA_MICROMIPS32_NOT_MIPS32R6;
- def NMSUB_S_MM : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S>,
+ def NMSUB_S_MM : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd>,
MADDS_FM_MM<0x22>, ISA_MICROMIPS32_NOT_MIPS32R6;
- def NMADD_D32_MM : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D>,
+ def NMADD_D32_MM : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd>,
MADDS_FM_MM<0xa>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
- def NMSUB_D32_MM : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D>,
+ def NMSUB_D32_MM : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd>,
MADDS_FM_MM<0x2a>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
}
}
let mayRaiseFPException = 1 in {
- def FLOOR_W_S_MM : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd,
- II_FLOOR>, ROUND_W_FM_MM<0, 0x2c>,
+ def FLOOR_W_S_MM : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd>,
+ ROUND_W_FM_MM<0, 0x2c>,
ISA_MICROMIPS;
def TRUNC_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd,
- FGR32Opnd, II_TRUNC>,
+ FGR32Opnd>,
ROUND_W_FM_MM<0, 0xac>, ISA_MICROMIPS;
- def CEIL_W_S_MM : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>,
+ def CEIL_W_S_MM : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd>,
ROUND_W_FM_MM<0, 0x6c>, ISA_MICROMIPS;
let Uses = [FCR31] in
- def FSQRT_S_MM : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S,
- fsqrt>, ROUND_W_FM_MM<0, 0x28>, ISA_MICROMIPS;
+ def FSQRT_S_MM : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd,
+ fsqrt>, ROUND_W_FM_MM<0, 0x28>, ISA_MICROMIPS;
}
def MTHC1_D32_MM : MMRel,
- MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
+ MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd>,
MFC1_FM_MM<0xe0>, ISA_MICROMIPS, FGR_32;
- def MFHC1_D32_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
+ def MFHC1_D32_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd>,
MFC1_FM_MM<0xc0>, ISA_MICROMIPS, FGR_32;
}
let DecoderNamespace = "MicroMipsFP64" in {
- def MTHC1_D64_MM : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>,
+ def MTHC1_D64_MM : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd>,
MFC1_FM_MM<0xe0>, ISA_MICROMIPS, FGR_64;
- def MFHC1_D64_MM : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>,
+ def MFHC1_D64_MM : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd>,
MFC1_FM_MM<0xc0>, ISA_MICROMIPS, FGR_64;
- def MTC1_D64_MM : MTC1_FT<"mtc1", FGR64Opnd, GPR32Opnd, II_MTC1>,
+ def MTC1_D64_MM : MTC1_FT<"mtc1", FGR64Opnd, GPR32Opnd>,
MFC1_FM_MM<0xa0>, ISA_MICROMIPS, FGR_64;
}
let DecoderNamespace = "MicroMips" in {
- def CFC1_MM : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>,
+ def CFC1_MM : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd>,
MFC1_FM_MM<0x40>, ISA_MICROMIPS;
- def CTC1_MM : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>,
+ def CTC1_MM : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd>,
MFC1_FM_MM<0x60>, ISA_MICROMIPS;
let mayRaiseFPException = 1, Uses = [FCR31] in {
- def RECIP_S_MM : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd,
- II_RECIP_S>,
+ def RECIP_S_MM : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd>,
ROUND_W_FM_MM<0b0, 0b01001000>, ISA_MICROMIPS;
- def RECIP_D32_MM : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd,
- II_RECIP_D>,
+ def RECIP_D32_MM : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd>,
ROUND_W_FM_MM<0b1, 0b01001000>, ISA_MICROMIPS, FGR_32 {
let BaseOpcode = "RECIP_D32";
}
let DecoderNamespace = "MicroMipsFP64" in
- def RECIP_D64_MM : MMRel, ABSS_FT<"recip.d", FGR64Opnd, FGR64Opnd,
- II_RECIP_D>,
+ def RECIP_D64_MM : MMRel, ABSS_FT<"recip.d", FGR64Opnd, FGR64Opnd>,
ROUND_W_FM_MM<0b1, 0b01001000>, ISA_MICROMIPS, FGR_64;
- def RSQRT_S_MM : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd,
- II_RECIP_S>,
+ def RSQRT_S_MM : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd>,
ROUND_W_FM_MM<0b0, 0b00001000>, ISA_MICROMIPS;
- def RSQRT_D32_MM : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd,
- II_RECIP_D>,
+ def RSQRT_D32_MM : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd>,
ROUND_W_FM_MM<0b1, 0b00001000>, ISA_MICROMIPS, FGR_32 {
let BaseOpcode = "RSQRT_D32";
}
let DecoderNamespace = "MicroMipsFP64" in
- def RSQRT_D64_MM : MMRel, ABSS_FT<"rsqrt.d", FGR64Opnd, FGR64Opnd,
- II_RECIP_D>,
+ def RSQRT_D64_MM : MMRel, ABSS_FT<"rsqrt.d", FGR64Opnd, FGR64Opnd>,
ROUND_W_FM_MM<0b1, 0b00001000>, ISA_MICROMIPS, FGR_64;
}
}
let DecoderNamespace = "MicroMips", DecoderMethod = "DecodeFMemMMR2" in {
- def LDC1_MM_D32 : MMRel, LW_FT<"ldc1", AFGR64Opnd, mem_mm_16, II_LDC1, load>,
+ def LDC1_MM_D32 : MMRel, LW_FT<"ldc1", AFGR64Opnd, mem_mm_16, load>,
LW_FM_MM<0x2f>, ISA_MICROMIPS, FGR_32 {
let BaseOpcode = "LDC132";
}
- def SDC1_MM_D32 : MMRel, SW_FT<"sdc1", AFGR64Opnd, mem_mm_16, II_SDC1, store>,
+ def SDC1_MM_D32 : MMRel, SW_FT<"sdc1", AFGR64Opnd, mem_mm_16, store>,
LW_FM_MM<0x2e>, ISA_MICROMIPS, FGR_32 {
let BaseOpcode = "SDC164";
}
- def LWC1_MM : MMRel, LW_FT<"lwc1", FGR32Opnd, mem_mm_16, II_LWC1, load>,
+ def LWC1_MM : MMRel, LW_FT<"lwc1", FGR32Opnd, mem_mm_16, load>,
LW_FM_MM<0x27>, ISA_MICROMIPS;
- def SWC1_MM : MMRel, SW_FT<"swc1", FGR32Opnd, mem_mm_16, II_SWC1, store>,
+ def SWC1_MM : MMRel, SW_FT<"swc1", FGR32Opnd, mem_mm_16, store>,
LW_FM_MM<0x26>, ISA_MICROMIPS;
}
let DecoderNamespace = "Mips64", DecoderMethod = "DecodeFMemMMR2" in {
- def LDC1_MM_D64 : MMRel, LW_FT<"ldc1", FGR64Opnd, mem_mm_16, II_LDC1, load>,
+ def LDC1_MM_D64 : MMRel, LW_FT<"ldc1", FGR64Opnd, mem_mm_16, load>,
LW_FM_MM<0x2f>, ISA_MICROMIPS, FGR_64 {
let BaseOpcode = "LDC164";
}
- def SDC1_MM_D64 : MMRel, SW_FT<"sdc1", FGR64Opnd, mem_mm_16, II_SDC1, store>,
+ def SDC1_MM_D64 : MMRel, SW_FT<"sdc1", FGR64Opnd, mem_mm_16, store>,
LW_FM_MM<0x2e>, ISA_MICROMIPS, FGR_64 {
let BaseOpcode = "SDC164";
}
}
-multiclass C_COND_MM<string TypeStr, RegisterOperand RC, bits<2> fmt,
- InstrItinClass itin> {
- def C_F_#NAME#_MM : MMRel, C_COND_FT<"f", TypeStr, RC, itin>,
+multiclass C_COND_MM<string TypeStr, RegisterOperand RC, bits<2> fmt> {
+ def C_F_#NAME#_MM : MMRel, C_COND_FT<"f", TypeStr, RC>,
C_COND_FM_MM<fmt, 0> {
let BaseOpcode = "c.f."#NAME;
let isCommutable = 1;
}
- def C_UN_#NAME#_MM : MMRel, C_COND_FT<"un", TypeStr, RC, itin>,
+ def C_UN_#NAME#_MM : MMRel, C_COND_FT<"un", TypeStr, RC>,
C_COND_FM_MM<fmt, 1> {
let BaseOpcode = "c.un."#NAME;
let isCommutable = 1;
}
- def C_EQ_#NAME#_MM : MMRel, C_COND_FT<"eq", TypeStr, RC, itin>,
+ def C_EQ_#NAME#_MM : MMRel, C_COND_FT<"eq", TypeStr, RC>,
C_COND_FM_MM<fmt, 2> {
let BaseOpcode = "c.eq."#NAME;
let isCommutable = 1;
}
- def C_UEQ_#NAME#_MM : MMRel, C_COND_FT<"ueq", TypeStr, RC, itin>,
+ def C_UEQ_#NAME#_MM : MMRel, C_COND_FT<"ueq", TypeStr, RC>,
C_COND_FM_MM<fmt, 3> {
let BaseOpcode = "c.ueq."#NAME;
let isCommutable = 1;
}
- def C_OLT_#NAME#_MM : MMRel, C_COND_FT<"olt", TypeStr, RC, itin>,
+ def C_OLT_#NAME#_MM : MMRel, C_COND_FT<"olt", TypeStr, RC>,
C_COND_FM_MM<fmt, 4> {
let BaseOpcode = "c.olt."#NAME;
}
- def C_ULT_#NAME#_MM : MMRel, C_COND_FT<"ult", TypeStr, RC, itin>,
+ def C_ULT_#NAME#_MM : MMRel, C_COND_FT<"ult", TypeStr, RC>,
C_COND_FM_MM<fmt, 5> {
let BaseOpcode = "c.ult."#NAME;
}
- def C_OLE_#NAME#_MM : MMRel, C_COND_FT<"ole", TypeStr, RC, itin>,
+ def C_OLE_#NAME#_MM : MMRel, C_COND_FT<"ole", TypeStr, RC>,
C_COND_FM_MM<fmt, 6> {
let BaseOpcode = "c.ole."#NAME;
}
- def C_ULE_#NAME#_MM : MMRel, C_COND_FT<"ule", TypeStr, RC, itin>,
+ def C_ULE_#NAME#_MM : MMRel, C_COND_FT<"ule", TypeStr, RC>,
C_COND_FM_MM<fmt, 7> {
let BaseOpcode = "c.ule."#NAME;
}
let mayRaiseFPException = 1 in {
- def C_SF_#NAME#_MM : MMRel, C_COND_FT<"sf", TypeStr, RC, itin>,
+ def C_SF_#NAME#_MM : MMRel, C_COND_FT<"sf", TypeStr, RC>,
C_COND_FM_MM<fmt, 8> {
let BaseOpcode = "c.sf."#NAME;
let isCommutable = 1;
}
- def C_NGLE_#NAME#_MM : MMRel, C_COND_FT<"ngle", TypeStr, RC, itin>,
+ def C_NGLE_#NAME#_MM : MMRel, C_COND_FT<"ngle", TypeStr, RC>,
C_COND_FM_MM<fmt, 9> {
let BaseOpcode = "c.ngle."#NAME;
}
- def C_SEQ_#NAME#_MM : MMRel, C_COND_FT<"seq", TypeStr, RC, itin>,
+ def C_SEQ_#NAME#_MM : MMRel, C_COND_FT<"seq", TypeStr, RC>,
C_COND_FM_MM<fmt, 10> {
let BaseOpcode = "c.seq."#NAME;
let isCommutable = 1;
}
- def C_NGL_#NAME#_MM : MMRel, C_COND_FT<"ngl", TypeStr, RC, itin>,
+ def C_NGL_#NAME#_MM : MMRel, C_COND_FT<"ngl", TypeStr, RC>,
C_COND_FM_MM<fmt, 11> {
let BaseOpcode = "c.ngl."#NAME;
}
- def C_LT_#NAME#_MM : MMRel, C_COND_FT<"lt", TypeStr, RC, itin>,
+ def C_LT_#NAME#_MM : MMRel, C_COND_FT<"lt", TypeStr, RC>,
C_COND_FM_MM<fmt, 12> {
let BaseOpcode = "c.lt."#NAME;
}
- def C_NGE_#NAME#_MM : MMRel, C_COND_FT<"nge", TypeStr, RC, itin>,
+ def C_NGE_#NAME#_MM : MMRel, C_COND_FT<"nge", TypeStr, RC>,
C_COND_FM_MM<fmt, 13> {
let BaseOpcode = "c.nge."#NAME;
}
- def C_LE_#NAME#_MM : MMRel, C_COND_FT<"le", TypeStr, RC, itin>,
+ def C_LE_#NAME#_MM : MMRel, C_COND_FT<"le", TypeStr, RC>,
C_COND_FM_MM<fmt, 14> {
let BaseOpcode = "c.le."#NAME;
}
- def C_NGT_#NAME#_MM : MMRel, C_COND_FT<"ngt", TypeStr, RC, itin>,
+ def C_NGT_#NAME#_MM : MMRel, C_COND_FT<"ngt", TypeStr, RC>,
C_COND_FM_MM<fmt, 15> {
let BaseOpcode = "c.ngt."#NAME;
}
}
}
let DecoderNamespace = "MicroMips" in {
- defm S : C_COND_MM<"s", FGR32Opnd, 0b00, II_C_CC_S>,
+ defm S : C_COND_MM<"s", FGR32Opnd, 0b00>,
ISA_MICROMIPS32_NOT_MIPS32R6;
- defm D32 : C_COND_MM<"d", AFGR64Opnd, 0b01, II_C_CC_D>,
+ defm D32 : C_COND_MM<"d", AFGR64Opnd, 0b01>,
ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
}
let DecoderNamespace = "Mips64" in
- defm D64 : C_COND_MM<"d", FGR64Opnd, 0b01, II_C_CC_D>,
+ defm D64 : C_COND_MM<"d", FGR64Opnd, 0b01>,
ISA_MICROMIPS32_NOT_MIPS32R6, FGR_64;
defm S_MM : C_COND_ALIASES<"s", FGR32Opnd>, HARDFLOAT,
diff --git a/llvm/lib/Target/Mips/MicroMipsInstrFormats.td b/llvm/lib/Target/Mips/MicroMipsInstrFormats.td
index f848fe6e58912..ff2b0ff491a3c 100644
--- a/llvm/lib/Target/Mips/MicroMipsInstrFormats.td
+++ b/llvm/lib/Target/Mips/MicroMipsInstrFormats.td
@@ -19,7 +19,7 @@
// This class does not depend on the instruction size.
//
class MicroMipsInstBase<dag outs, dag ins, string asmstr, list<dag> pattern,
- InstrItinClass itin, Format f> : Instruction,
+ Format f> : Instruction,
PredicateControl {
let Namespace = "Mips";
let DecoderNamespace = "MicroMips";
@@ -29,8 +29,6 @@ class MicroMipsInstBase<dag outs, dag ins, string asmstr, list<dag> pattern,
let AsmString = asmstr;
let Pattern = pattern;
- let Itinerary = itin;
-
let EncodingPredicates = [InMicroMips];
Format Form = f;
@@ -40,8 +38,8 @@ class MicroMipsInstBase<dag outs, dag ins, string asmstr, list<dag> pattern,
// Base class for MicroMIPS 16-bit instructions.
//
class MicroMipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
- InstrItinClass itin, Format f> :
- MicroMipsInstBase<outs, ins, asmstr, pattern, itin, f>
+ Format f> :
+ MicroMipsInstBase<outs, ins, asmstr, pattern, f>
{
let Size = 2;
field bits<16> Inst;
diff --git a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
index b44bf1391b73e..dff57a5d59dc1 100644
--- a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
@@ -196,7 +196,7 @@ def simm23_lsl2 : Operand<i32> {
class CompactBranchMM<string opstr, DAGOperand opnd, RegisterOperand RO> :
InstSE<(outs), (ins RO:$rs, opnd:$offset),
- !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZC, FrmI> {
+ !strconcat(opstr, "\t$rs, $offset"), [], FrmI> {
let isBranch = 1;
let isTerminator = 1;
let hasDelaySlot = 0;
@@ -205,11 +205,11 @@ class CompactBranchMM<string opstr, DAGOperand opnd, RegisterOperand RO> :
let canFoldAsLoad = 1 in
class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
- Operand MemOpnd, InstrItinClass Itin> :
+ Operand MemOpnd> :
InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
!strconcat(opstr, "\t$rt, $addr"),
[(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
- Itin, FrmI> {
+ FrmI> {
let DecoderMethod = "DecodeMemMMImm12";
string Constraints = "$src = $rt";
let BaseOpcode = opstr;
@@ -218,10 +218,10 @@ class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
}
class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
- Operand MemOpnd, InstrItinClass Itin>:
+ Operand MemOpnd>:
InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
!strconcat(opstr, "\t$rt, $addr"),
- [(OpNode RO:$rt, addrimm12:$addr)], Itin, FrmI> {
+ [(OpNode RO:$rt, addrimm12:$addr)], FrmI> {
let DecoderMethod = "DecodeMemMMImm12";
let BaseOpcode = opstr;
bit mayLoad = 0;
@@ -232,7 +232,7 @@ class MovePMM16<string opstr, RegisterOperand RO1, RegisterOperand RO2,
RegisterOperand RO3> :
MicroMipsInst16<(outs RO1:$rd1, RO2:$rd2), (ins RO3:$rs, RO3:$rt),
!strconcat(opstr, "\t$rd1, $rd2, $rs, $rt"), [],
- NoItinerary, FrmR> {
+ FrmR> {
let isReMaterializable = 1;
let isMoveReg = 1;
let DecoderMethod = "DecodeMovePOperands";
@@ -240,7 +240,7 @@ MicroMipsInst16<(outs RO1:$rd1, RO2:$rd2), (ins RO3:$rs, RO3:$rt),
class StorePairMM<string opstr>
: InstSE<(outs), (ins GPR32Opnd:$rt, GPR32Opnd:$rt2, mem_simm12:$addr),
- !strconcat(opstr, "\t$rt, $addr"), [], II_SWP, FrmI, opstr> {
+ !strconcat(opstr, "\t$rt, $addr"), [], FrmI, opstr> {
let DecoderMethod = "DecodeMemMMImm12";
let mayStore = 1;
let AsmMatchConverter = "ConvertXWPOperands";
@@ -248,7 +248,7 @@ class StorePairMM<string opstr>
class LoadPairMM<string opstr>
: InstSE<(outs GPR32Opnd:$rt, GPR32Opnd:$rt2), (ins mem_simm12:$addr),
- !strconcat(opstr, "\t$rt, $addr"), [], II_LWP, FrmI, opstr> {
+ !strconcat(opstr, "\t$rt, $addr"), [], FrmI, opstr> {
let DecoderMethod = "DecodeMemMMImm12";
let mayLoad = 1;
let AsmMatchConverter = "ConvertXWPOperands";
@@ -256,14 +256,14 @@ class LoadPairMM<string opstr>
class LLBaseMM<string opstr, RegisterOperand RO> :
InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
- !strconcat(opstr, "\t$rt, $addr"), [], II_LL, FrmI> {
+ !strconcat(opstr, "\t$rt, $addr"), [], FrmI> {
let DecoderMethod = "DecodeMemMMImm12";
let mayLoad = 1;
}
class LLEBaseMM<string opstr, RegisterOperand RO> :
InstSE<(outs RO:$rt), (ins mem_simm9:$addr),
- !strconcat(opstr, "\t$rt, $addr"), [], II_LLE, FrmI> {
+ !strconcat(opstr, "\t$rt, $addr"), [], FrmI> {
let DecoderMethod = "DecodeMemMMImm9";
string BaseOpcode = opstr;
let mayLoad = 1;
@@ -271,7 +271,7 @@ class LLEBaseMM<string opstr, RegisterOperand RO> :
class SCBaseMM<string opstr, RegisterOperand RO> :
InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
- !strconcat(opstr, "\t$rt, $addr"), [], II_SC, FrmI> {
+ !strconcat(opstr, "\t$rt, $addr"), [], FrmI> {
let DecoderMethod = "DecodeMemMMImm12";
let mayStore = 1;
let Constraints = "$rt = $dst";
@@ -279,7 +279,7 @@ class SCBaseMM<string opstr, RegisterOperand RO> :
class SCEBaseMM<string opstr, RegisterOperand RO> :
InstSE<(outs RO:$dst), (ins RO:$rt, mem_simm9:$addr),
- !strconcat(opstr, "\t$rt, $addr"), [], II_SCE, FrmI> {
+ !strconcat(opstr, "\t$rt, $addr"), [], FrmI> {
let DecoderMethod = "DecodeMemMMImm9";
string BaseOpcode = opstr;
let mayStore = 1;
@@ -287,35 +287,32 @@ class SCEBaseMM<string opstr, RegisterOperand RO> :
}
class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
- InstrItinClass Itin = NoItinerary, DAGOperand MO = mem_mm_12> :
+ DAGOperand MO = mem_mm_12> :
InstSE<(outs RO:$rt), (ins MO:$addr),
!strconcat(opstr, "\t$rt, $addr"),
- [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI, opstr> {
+ [(set RO:$rt, (OpNode addrimm12:$addr))], FrmI, opstr> {
let DecoderMethod = "DecodeMemMMImm12";
let canFoldAsLoad = 1;
let mayLoad = 1;
}
class ArithRMM16<string opstr, RegisterOperand RO, bit isComm = 0,
- InstrItinClass Itin = NoItinerary,
SDPatternOperator OpNode = null_frag> :
MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, RO:$rt),
!strconcat(opstr, "\t$rd, $rs, $rt"),
- [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
+ [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], FrmR> {
let isCommutable = isComm;
}
-class AndImmMM16<string opstr, RegisterOperand RO,
- InstrItinClass Itin = NoItinerary> :
+class AndImmMM16<string opstr, RegisterOperand RO> :
MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, uimm4_andi:$imm),
- !strconcat(opstr, "\t$rd, $rs, $imm"), [], Itin, FrmI>;
+ !strconcat(opstr, "\t$rd, $rs, $imm"), [], FrmI>;
class LogicRMM16<string opstr, RegisterOperand RO,
- InstrItinClass Itin = NoItinerary,
SDPatternOperator OpNode = null_frag> :
MicroMipsInst16<(outs RO:$dst), (ins RO:$rs, RO:$rt),
!strconcat(opstr, "\t$rt, $rs"),
- [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
+ [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], FrmR> {
let isCommutable = 1;
let Constraints = "$rt = $dst";
}
@@ -323,51 +320,45 @@ class LogicRMM16<string opstr, RegisterOperand RO,
class NotMM16<string opstr, RegisterOperand RO> :
MicroMipsInst16<(outs RO:$rt), (ins RO:$rs),
!strconcat(opstr, "\t$rt, $rs"),
- [(set RO:$rt, (not RO:$rs))], II_NOT, FrmR>;
+ [(set RO:$rt, (not RO:$rs))], FrmR>;
-class ShiftIMM16<string opstr, Operand ImmOpnd, RegisterOperand RO,
- InstrItinClass Itin = NoItinerary> :
+class ShiftIMM16<string opstr, Operand ImmOpnd, RegisterOperand RO> :
MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
- !strconcat(opstr, "\t$rd, $rt, $shamt"), [], Itin, FrmR>;
+ !strconcat(opstr, "\t$rd, $rt, $shamt"), [], FrmR>;
-class LoadMM16<string opstr, DAGOperand RO,
- InstrItinClass Itin, Operand MemOpnd> :
+class LoadMM16<string opstr, DAGOperand RO, Operand MemOpnd> :
MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$addr),
- !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
+ !strconcat(opstr, "\t$rt, $addr"), [], FrmI> {
let DecoderMethod = "DecodeMemMMImm4";
let canFoldAsLoad = 1;
let mayLoad = 1;
}
-class StoreMM16<string opstr, DAGOperand RTOpnd, InstrItinClass Itin,
- Operand MemOpnd> :
+class StoreMM16<string opstr, DAGOperand RTOpnd, Operand MemOpnd> :
MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
- !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
+ !strconcat(opstr, "\t$rt, $addr"), [], FrmI> {
let DecoderMethod = "DecodeMemMMImm4";
let mayStore = 1;
}
-class LoadSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
- Operand MemOpnd> :
+class LoadSPMM16<string opstr, DAGOperand RO, Operand MemOpnd> :
MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
- !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
+ !strconcat(opstr, "\t$rt, $offset"), [], FrmI> {
let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
let canFoldAsLoad = 1;
let mayLoad = 1;
}
-class StoreSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
- Operand MemOpnd> :
+class StoreSPMM16<string opstr, DAGOperand RO, Operand MemOpnd> :
MicroMipsInst16<(outs), (ins RO:$rt, MemOpnd:$offset),
- !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
+ !strconcat(opstr, "\t$rt, $offset"), [], FrmI> {
let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
let mayStore = 1;
}
-class LoadGPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
- Operand MemOpnd> :
+class LoadGPMM16<string opstr, DAGOperand RO, Operand MemOpnd> :
MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
- !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
+ !strconcat(opstr, "\t$rt, $offset"), [], FrmI> {
let DecoderMethod = "DecodeMemMMGPImm7Lsl2";
let canFoldAsLoad = 1;
let mayLoad = 1;
@@ -376,27 +367,27 @@ class LoadGPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
class AddImmUR2<string opstr, RegisterOperand RO> :
MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm),
!strconcat(opstr, "\t$rd, $rs, $imm"),
- [], II_ADDIU, FrmR> {
+ [], FrmR> {
let isCommutable = 1;
}
class AddImmUS5<string opstr, RegisterOperand RO> :
MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm),
- !strconcat(opstr, "\t$rd, $imm"), [], II_ADDIU, FrmR> {
+ !strconcat(opstr, "\t$rd, $imm"), [], FrmR> {
let Constraints = "$rd = $dst";
}
class AddImmUR1SP<string opstr, RegisterOperand RO> :
MicroMipsInst16<(outs RO:$rd), (ins uimm6_lsl2:$imm),
- !strconcat(opstr, "\t$rd, $imm"), [], II_ADDIU, FrmR>;
+ !strconcat(opstr, "\t$rd, $imm"), [], FrmR>;
class AddImmUSP<string opstr> :
MicroMipsInst16<(outs), (ins simm9_addiusp:$imm),
- !strconcat(opstr, "\t$imm"), [], II_ADDIU, FrmI>;
+ !strconcat(opstr, "\t$imm"), [], FrmI>;
class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
- [], II_MFHI_MFLO, FrmR> {
+ [], FrmR> {
let Uses = [UseReg];
let hasSideEffects = 0;
let isMoveReg = 1;
@@ -404,21 +395,21 @@ class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
class MoveMM16<string opstr, RegisterOperand RO>
: MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
- !strconcat(opstr, "\t$rd, $rs"), [], II_MOVE, FrmR> {
+ !strconcat(opstr, "\t$rd, $rs"), [], FrmR> {
let isReMaterializable = 1;
let isMoveReg = 1;
}
class LoadImmMM16<string opstr, Operand Od, RegisterOperand RO> :
MicroMipsInst16<(outs RO:$rd), (ins Od:$imm),
- !strconcat(opstr, "\t$rd, $imm"), [], II_LI, FrmI> {
+ !strconcat(opstr, "\t$rd, $imm"), [], FrmI> {
let isReMaterializable = 1;
}
// 16-bit Jump and Link (Call)
class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
- [(MipsJmpLink RO:$rs)], II_JALR, FrmR> {
+ [(MipsJmpLink RO:$rs)], FrmR> {
let isCall = 1;
let hasDelaySlot = 1;
let Defs = [RA];
@@ -428,7 +419,7 @@ class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
// 16-bit Jump Reg
class JumpRegMM16<string opstr, RegisterOperand RO> :
MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
- [], II_JR, FrmR> {
+ [], FrmR> {
let hasDelaySlot = 1;
let isBranch = 1;
let isIndirectBranch = 1;
@@ -437,7 +428,7 @@ class JumpRegMM16<string opstr, RegisterOperand RO> :
// Base class for JRADDIUSP instruction.
class JumpRAddiuStackMM16 :
MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jraddiusp\t$imm",
- [], II_JRADDIUSP, FrmR> {
+ [], FrmR> {
let isTerminator = 1;
let isBarrier = 1;
let isBranch = 1;
@@ -447,7 +438,7 @@ class JumpRAddiuStackMM16 :
// 16-bit Jump and Link (Call) - Short Delay Slot
class JumpLinkRegSMM16<string opstr, RegisterOperand RO> :
MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
- [], II_JALRS, FrmR> {
+ [], FrmR> {
let isCall = 1;
let hasDelaySlot = 1;
let Defs = [RA];
@@ -456,7 +447,7 @@ class JumpLinkRegSMM16<string opstr, RegisterOperand RO> :
// 16-bit Jump Register Compact - No delay slot
class JumpRegCMM16<string opstr, RegisterOperand RO> :
MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
- [], II_JRC, FrmR> {
+ [], FrmR> {
let isTerminator = 1;
let isBarrier = 1;
let isBranch = 1;
@@ -464,14 +455,14 @@ class JumpRegCMM16<string opstr, RegisterOperand RO> :
}
// Break16 and Sdbbp16
-class BrkSdbbp16MM<string opstr, InstrItinClass Itin> :
+class BrkSdbbp16MM<string opstr> :
MicroMipsInst16<(outs), (ins uimm4:$code_),
!strconcat(opstr, "\t$code_"),
- [], Itin, FrmOther>;
+ [], FrmOther>;
class CBranchZeroMM<string opstr, DAGOperand opnd, RegisterOperand RO> :
MicroMipsInst16<(outs), (ins RO:$rs, opnd:$offset),
- !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZ, FrmI> {
+ !strconcat(opstr, "\t$rs, $offset"), [], FrmI> {
let isBranch = 1;
let isTerminator = 1;
let hasDelaySlot = 1;
@@ -482,32 +473,32 @@ class CBranchZeroMM<string opstr, DAGOperand opnd, RegisterOperand RO> :
let isCall = 1, hasDelaySlot = 1, Defs = [RA] in {
class JumpLinkMM<string opstr, DAGOperand opnd> :
InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
- [], II_JALS, FrmJ, opstr> {
+ [], FrmJ, opstr> {
let DecoderMethod = "DecodeJumpTargetMM";
}
class JumpLinkRegMM<string opstr, RegisterOperand RO>:
InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
- [], II_JALRS, FrmR>;
+ [], FrmR>;
class BranchCompareToZeroLinkMM<string opstr, DAGOperand opnd,
RegisterOperand RO> :
InstSE<(outs), (ins RO:$rs, opnd:$offset),
- !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZALS, FrmI, opstr>;
+ !strconcat(opstr, "\t$rs, $offset"), [], FrmI, opstr>;
}
class LoadWordIndexedScaledMM<string opstr, RegisterOperand RO> :
InstSE<(outs RO:$rd), (ins PtrRC:$base, PtrRC:$index),
- !strconcat(opstr, "\t$rd, ${index}(${base})"), [], II_LWXS, FrmFI>;
+ !strconcat(opstr, "\t$rd, ${index}(${base})"), [], FrmFI>;
class PrefetchIndexed<string opstr> :
InstSE<(outs), (ins PtrRC:$base, PtrRC:$index, uimm5:$hint),
!strconcat(opstr, "\t$hint, ${index}(${base})"),
- [], II_PREF, FrmOther>;
+ [], FrmOther>;
class AddImmUPC<string opstr, RegisterOperand RO> :
InstSE<(outs RO:$rs), (ins simm23_lsl2:$imm),
- !strconcat(opstr, "\t$rs, $imm"), [], II_ADDIU, FrmR>;
+ !strconcat(opstr, "\t$rs, $imm"), [], FrmR>;
/// A list of registers used by load/store multiple instructions.
def RegListAsmOperand : AsmOperandClass {
@@ -536,30 +527,30 @@ def reglist16 : Operand<i32> {
let ParserMatchClass = RegList16AsmOperand;
}
-class StoreMultMM<string opstr, InstrItinClass Itin> :
+class StoreMultMM<string opstr> :
InstSE<(outs), (ins reglist:$rt, mem_mm_12:$addr),
- !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
+ !strconcat(opstr, "\t$rt, $addr"), [], FrmI, opstr> {
let DecoderMethod = "DecodeMemMMImm12";
let mayStore = 1;
}
-class LoadMultMM<string opstr, InstrItinClass Itin> :
+class LoadMultMM<string opstr> :
InstSE<(outs reglist:$rt), (ins mem_mm_12:$addr),
- !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
+ !strconcat(opstr, "\t$rt, $addr"), [], FrmI, opstr> {
let DecoderMethod = "DecodeMemMMImm12";
let mayLoad = 1;
}
-class StoreMultMM16<string opstr, InstrItinClass Itin> :
+class StoreMultMM16<string opstr> :
MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr),
- !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
+ !strconcat(opstr, "\t$rt, $addr"), [], FrmI> {
let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
let mayStore = 1;
}
-class LoadMultMM16<string opstr, InstrItinClass Itin> :
+class LoadMultMM16<string opstr> :
MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
- !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
+ !strconcat(opstr, "\t$rt, $addr"), [], FrmI> {
let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
let mayLoad = 1;
}
@@ -567,7 +558,7 @@ class LoadMultMM16<string opstr, InstrItinClass Itin> :
class UncondBranchMM16<string opstr> :
MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
!strconcat(opstr, "\t$offset"),
- [], II_B, FrmI> {
+ [], FrmI> {
let isBranch = 1;
let isTerminator = 1;
let isBarrier = 1;
@@ -578,74 +569,74 @@ class UncondBranchMM16<string opstr> :
class HypcallMM<string opstr> :
InstSE<(outs), (ins uimm10:$code_),
- !strconcat(opstr, "\t$code_"), [], II_HYPCALL, FrmOther> {
+ !strconcat(opstr, "\t$code_"), [], FrmOther> {
let BaseOpcode = opstr;
}
-class TLBINVMM<string opstr, InstrItinClass Itin> :
- InstSE<(outs), (ins), opstr, [], Itin, FrmOther> {
+class TLBINVMM<string opstr> :
+ InstSE<(outs), (ins), opstr, [], FrmOther> {
let BaseOpcode = opstr;
}
class MfCop0MM<string opstr, RegisterOperand DstRC,
- RegisterOperand SrcRC, InstrItinClass Itin> :
+ RegisterOperand SrcRC> :
InstSE<(outs DstRC:$rt), (ins SrcRC:$rs, uimm3:$sel),
- !strconcat(opstr, "\t$rt, $rs, $sel"), [], Itin, FrmR> {
+ !strconcat(opstr, "\t$rt, $rs, $sel"), [], FrmR> {
let BaseOpcode = opstr;
}
class MtCop0MM<string opstr, RegisterOperand DstRC,
- RegisterOperand SrcRC, InstrItinClass Itin> :
+ RegisterOperand SrcRC> :
InstSE<(outs DstRC:$rs), (ins SrcRC:$rt, uimm3:$sel),
- !strconcat(opstr, "\t$rt, $rs, $sel"), [], Itin, FrmR> {
+ !strconcat(opstr, "\t$rt, $rs, $sel"), [], FrmR> {
let BaseOpcode = opstr;
}
let FastISelShouldIgnore = 1 in {
- def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
+ def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, add>,
ARITH_FM_MM16<0>, ISA_MICROMIPS32_NOT_MIPS32R6;
- def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
+ def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, and>,
LOGIC_FM_MM16<0x2>, ISA_MICROMIPS32_NOT_MIPS32R6;
}
-def ANDI16_MM : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, ANDI_FM_MM16<0x0b>,
+def ANDI16_MM : AndImmMM16<"andi16", GPRMM16Opnd>, ANDI_FM_MM16<0x0b>,
ISA_MICROMIPS32_NOT_MIPS32R6;
def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>,
ISA_MICROMIPS32_NOT_MIPS32R6;
let FastISelShouldIgnore = 1 in
- def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>, LOGIC_FM_MM16<0x3>,
+ def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, or>, LOGIC_FM_MM16<0x3>,
ISA_MICROMIPS32_NOT_MIPS32R6;
-def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
+def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd>,
SHIFT_FM_MM16<0>, ISA_MICROMIPS32_NOT_MIPS32R6;
-def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
+def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd>,
SHIFT_FM_MM16<1>, ISA_MICROMIPS32_NOT_MIPS32R6;
let FastISelShouldIgnore = 1 in {
- def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
+ def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, sub>,
ARITH_FM_MM16<1>, ISA_MICROMIPS32_NOT_MIPS32R6;
- def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
+ def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, xor>,
LOGIC_FM_MM16<0x1>, ISA_MICROMIPS32_NOT_MIPS32R6;
}
-def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, II_LBU, mem_mm_4>,
+def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, mem_mm_4>,
LOAD_STORE_FM_MM16<0x02>, ISA_MICROMIPS;
-def LHU16_MM : LoadMM16<"lhu16", GPRMM16Opnd, II_LHU, mem_mm_4_lsl1>,
+def LHU16_MM : LoadMM16<"lhu16", GPRMM16Opnd, mem_mm_4_lsl1>,
LOAD_STORE_FM_MM16<0x0a>, ISA_MICROMIPS;
-def LW16_MM : LoadMM16<"lw16", GPRMM16Opnd, II_LW, mem_mm_4_lsl2>,
+def LW16_MM : LoadMM16<"lw16", GPRMM16Opnd, mem_mm_4_lsl2>,
LOAD_STORE_FM_MM16<0x1a>, ISA_MICROMIPS;
-def SB16_MM : StoreMM16<"sb16", GPRMM16OpndZero, II_SB, mem_mm_4>,
+def SB16_MM : StoreMM16<"sb16", GPRMM16OpndZero, mem_mm_4>,
LOAD_STORE_FM_MM16<0x22>,
ISA_MICROMIPS32_NOT_MIPS32R6;
-def SH16_MM : StoreMM16<"sh16", GPRMM16OpndZero, II_SH, mem_mm_4_lsl1>,
+def SH16_MM : StoreMM16<"sh16", GPRMM16OpndZero, mem_mm_4_lsl1>,
LOAD_STORE_FM_MM16<0x2a>,
ISA_MICROMIPS32_NOT_MIPS32R6;
-def SW16_MM : StoreMM16<"sw16", GPRMM16OpndZero, II_SW, mem_mm_4_lsl2>,
+def SW16_MM : StoreMM16<"sw16", GPRMM16OpndZero, mem_mm_4_lsl2>,
LOAD_STORE_FM_MM16<0x3a>,
ISA_MICROMIPS32_NOT_MIPS32R6;
-def LWGP_MM : LoadGPMM16<"lw", GPRMM16Opnd, II_LW, mem_mm_gp_simm7_lsl2>,
+def LWGP_MM : LoadGPMM16<"lw", GPRMM16Opnd, mem_mm_gp_simm7_lsl2>,
LOAD_GP_FM_MM16<0x19>, ISA_MICROMIPS;
-def LWSP_MM : LoadSPMM16<"lw", GPR32Opnd, II_LW, mem_mm_sp_imm5_lsl2>,
+def LWSP_MM : LoadSPMM16<"lw", GPR32Opnd, mem_mm_sp_imm5_lsl2>,
LOAD_STORE_SP_FM_MM16<0x12>, ISA_MICROMIPS;
-def SWSP_MM : StoreSPMM16<"swsp", GPR32Opnd, II_SW, mem_mm_sp_imm5_lsl2>,
+def SWSP_MM : StoreSPMM16<"swsp", GPR32Opnd, mem_mm_sp_imm5_lsl2>,
LOAD_STORE_SP_FM_MM16<0x32>, ISA_MICROMIPS32_NOT_MIPS32R6;
def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16,
ISA_MICROMIPS;
@@ -680,26 +671,26 @@ def BEQZ16_MM : CBranchZeroMM<"beqz16", brtarget7_mm, GPRMM16Opnd>,
def BNEZ16_MM : CBranchZeroMM<"bnez16", brtarget7_mm, GPRMM16Opnd>,
BEQNEZ_FM_MM16<0x2b>, ISA_MICROMIPS32_NOT_MIPS32R6;
def B16_MM : UncondBranchMM16<"b16">, B16_FM, ISA_MICROMIPS32_NOT_MIPS32R6;
-def BREAK16_MM : BrkSdbbp16MM<"break16", II_BREAK>, BRKSDBBP16_FM_MM<0x28>,
+def BREAK16_MM : BrkSdbbp16MM<"break16">, BRKSDBBP16_FM_MM<0x28>,
ISA_MICROMIPS32_NOT_MIPS32R6;
-def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16", II_SDBBP>, BRKSDBBP16_FM_MM<0x2C>,
+def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16">, BRKSDBBP16_FM_MM<0x2C>,
ISA_MICROMIPS32_NOT_MIPS32R6;
class WaitMM<string opstr> :
InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],
- II_WAIT, FrmOther, opstr>;
+ FrmOther, opstr>;
let DecoderNamespace = "MicroMips" in {
/// Load and Store Instructions - multiple
- def SWM16_MM : StoreMultMM16<"swm16", II_SWM>, LWM_FM_MM16<0x5>,
+ def SWM16_MM : StoreMultMM16<"swm16">, LWM_FM_MM16<0x5>,
ISA_MICROMIPS32_NOT_MIPS32R6;
- def LWM16_MM : LoadMultMM16<"lwm16", II_LWM>, LWM_FM_MM16<0x4>,
+ def LWM16_MM : LoadMultMM16<"lwm16">, LWM_FM_MM16<0x4>,
ISA_MICROMIPS32_NOT_MIPS32R6;
def CFC2_MM : InstSE<(outs GPR32Opnd:$rt), (ins COP2Opnd:$impl),
- "cfc2\t$rt, $impl", [], II_CFC2, FrmFR, "cfc2">,
+ "cfc2\t$rt, $impl", [], FrmFR, "cfc2">,
POOL32A_CFTC2_FM_MM<0b1100110100>, ISA_MICROMIPS;
def CTC2_MM : InstSE<(outs COP2Opnd:$impl), (ins GPR32Opnd:$rt),
- "ctc2\t$rt, $impl", [], II_CTC2, FrmFR, "ctc2">,
+ "ctc2\t$rt, $impl", [], FrmFR, "ctc2">,
POOL32A_CFTC2_FM_MM<0b1101110100>, ISA_MICROMIPS;
/// Compact Branch Instructions
@@ -709,20 +700,20 @@ let DecoderNamespace = "MicroMips" in {
COMPACT_BRANCH_FM_MM<0x5>, ISA_MICROMIPS32_NOT_MIPS32R6;
/// Arithmetic Instructions (ALU Immediate)
- def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU>,
+ def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>,
ADDI_FM_MM<0xc>, ISA_MICROMIPS32_NOT_MIPS32R6;
- def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd, II_ADDI>,
+ def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>,
ADDI_FM_MM<0x4>, ISA_MICROMIPS32_NOT_MIPS32R6;
def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
SLTI_FM_MM<0x24>, ISA_MICROMIPS;
def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
SLTI_FM_MM<0x2c>, ISA_MICROMIPS;
- def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI>,
+ def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>,
ADDI_FM_MM<0x34>, ISA_MICROMIPS32_NOT_MIPS32R6;
- def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
+ def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, immZExt16,
or>, ADDI_FM_MM<0x14>,
ISA_MICROMIPS32_NOT_MIPS32R6;
- def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI,
+ def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd,
immZExt16, xor>, ADDI_FM_MM<0x1c>,
ISA_MICROMIPS32_NOT_MIPS32R6;
def LUi_MM : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16_relaxed>, LUI_FM_MM,
@@ -732,36 +723,36 @@ let DecoderNamespace = "MicroMips" in {
LW_FM_MM<0xc>, ISA_MICROMIPS;
/// Arithmetic Instructions (3-Operand, R-Type)
- def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
+ def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, add>,
ADD_FM_MM<0, 0x150>, ISA_MICROMIPS32_NOT_MIPS32R6;
- def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
+ def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, sub>,
ADD_FM_MM<0, 0x1d0>, ISA_MICROMIPS32_NOT_MIPS32R6;
let Defs = [HI0, LO0] in
- def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
+ def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, mul>,
ADD_FM_MM<0, 0x210>, ISA_MICROMIPS32_NOT_MIPS32R6;
- def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd, 1, II_ADD>,
+ def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd, 1>,
ADD_FM_MM<0, 0x110>, ISA_MICROMIPS32_NOT_MIPS32R6;
- def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>,
+ def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd, 0>,
ADD_FM_MM<0, 0x190>, ISA_MICROMIPS32_NOT_MIPS32R6;
def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>,
ISA_MICROMIPS;
def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
ADD_FM_MM<0, 0x390>, ISA_MICROMIPS;
- def AND_MM : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
+ def AND_MM : MMRel, ArithLogicR<"and", GPR32Opnd, 1, and>,
ADD_FM_MM<0, 0x250>, ISA_MICROMIPS32_NOT_MIPS32R6;
- def OR_MM : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
+ def OR_MM : MMRel, ArithLogicR<"or", GPR32Opnd, 1, or>,
ADD_FM_MM<0, 0x290>, ISA_MICROMIPS32_NOT_MIPS32R6;
- def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
+ def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, xor>,
ADD_FM_MM<0, 0x310>, ISA_MICROMIPS32_NOT_MIPS32R6;
def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>,
ISA_MICROMIPS32_NOT_MIPS32R6;
- def MULT_MM : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
+ def MULT_MM : MMRel, Mult<"mult", GPR32Opnd, [HI0, LO0]>,
MULT_FM_MM<0x22c>, ISA_MICROMIPS32_NOT_MIPS32R6;
- def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
+ def MULTu_MM : MMRel, Mult<"multu", GPR32Opnd, [HI0, LO0]>,
MULT_FM_MM<0x26c>, ISA_MICROMIPS32_NOT_MIPS32R6;
- def SDIV_MM : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
+ def SDIV_MM : MMRel, Div<"div", GPR32Opnd, [HI0, LO0]>,
MULT_FM_MM<0x2ac>, ISA_MICROMIPS32_NOT_MIPS32R6;
- def UDIV_MM : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
+ def UDIV_MM : MMRel, Div<"divu", GPR32Opnd, [HI0, LO0]>,
MULT_FM_MM<0x2ec>, ISA_MICROMIPS32_NOT_MIPS32R6;
/// Arithmetic Instructions with PC and Immediate
@@ -769,24 +760,24 @@ let DecoderNamespace = "MicroMips" in {
ISA_MICROMIPS32_NOT_MIPS32R6;
/// Shift Instructions
- def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,
+ def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd>,
SRA_FM_MM<0, 0>, ISA_MICROMIPS;
- def SRL_MM : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>,
+ def SRL_MM : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd>,
SRA_FM_MM<0x40, 0>, ISA_MICROMIPS;
- def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,
+ def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd>,
SRA_FM_MM<0x80, 0>, ISA_MICROMIPS;
- def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>,
+ def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd>,
SRLV_FM_MM<0x10, 0>, ISA_MICROMIPS;
- def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>,
+ def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd>,
SRLV_FM_MM<0x50, 0>, ISA_MICROMIPS;
- def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>,
+ def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd>,
SRLV_FM_MM<0x90, 0>, ISA_MICROMIPS;
- def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
+ def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd>,
SRA_FM_MM<0xc0, 0>, ISA_MICROMIPS {
list<dag> Pattern = [(set GPR32Opnd:$rd,
(rotr GPR32Opnd:$rt, immZExt5:$shamt))];
}
- def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,
+ def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd>,
SRLV_FM_MM<0xd0, 0>, ISA_MICROMIPS {
list<dag> Pattern = [(set GPR32Opnd:$rd,
(rotr GPR32Opnd:$rt, GPR32Opnd:$rs))];
@@ -794,61 +785,51 @@ let DecoderNamespace = "MicroMips" in {
/// Load and Store Instructions - aligned
let DecoderMethod = "DecodeMemMMImm16" in {
- def LB_MM : LoadMemory<"lb", GPR32Opnd, mem_mm_16, sextloadi8, II_LB>,
+ def LB_MM : LoadMemory<"lb", GPR32Opnd, mem_mm_16, sextloadi8>,
MMRel, LW_FM_MM<0x7>, ISA_MICROMIPS;
- def LBu_MM : LoadMemory<"lbu", GPR32Opnd, mem_mm_16, zextloadi8, II_LBU>,
+ def LBu_MM : LoadMemory<"lbu", GPR32Opnd, mem_mm_16, zextloadi8>,
MMRel, LW_FM_MM<0x5>, ISA_MICROMIPS;
- def LH_MM : LoadMemory<"lh", GPR32Opnd, mem_simmptr, sextloadi16, II_LH,
+ def LH_MM : LoadMemory<"lh", GPR32Opnd, mem_simmptr, sextloadi16,
addrDefault>, MMRel, LW_FM_MM<0xf>, ISA_MICROMIPS;
- def LHu_MM : LoadMemory<"lhu", GPR32Opnd, mem_simmptr, zextloadi16, II_LHU>,
+ def LHu_MM : LoadMemory<"lhu", GPR32Opnd, mem_simmptr, zextloadi16>,
MMRel, LW_FM_MM<0xd>, ISA_MICROMIPS;
- def LW_MM : Load<"lw", GPR32Opnd, null_frag, II_LW>, MMRel, LW_FM_MM<0x3f>,
+ def LW_MM : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>,
ISA_MICROMIPS;
- def SB_MM : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel,
+ def SB_MM : Store<"sb", GPR32Opnd, truncstorei8>, MMRel,
LW_FM_MM<0x6>, ISA_MICROMIPS;
- def SH_MM : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel,
+ def SH_MM : Store<"sh", GPR32Opnd, truncstorei16>, MMRel,
LW_FM_MM<0xe>, ISA_MICROMIPS;
- def SW_MM : Store<"sw", GPR32Opnd, null_frag, II_SW>, MMRel,
+ def SW_MM : Store<"sw", GPR32Opnd>, MMRel,
LW_FM_MM<0x3e>, ISA_MICROMIPS;
}
let DecoderMethod = "DecodeMemMMImm9" in {
- def LBE_MM : MMRel, Load<"lbe", GPR32Opnd, null_frag, II_LBE>,
+ def LBE_MM : MMRel, Load<"lbe", GPR32Opnd>,
POOL32C_LHUE_FM_MM<0x18, 0x6, 0x4>, ISA_MICROMIPS, ASE_EVA;
- def LBuE_MM : MMRel, Load<"lbue", GPR32Opnd, null_frag, II_LBUE>,
+ def LBuE_MM : MMRel, Load<"lbue", GPR32Opnd>,
POOL32C_LHUE_FM_MM<0x18, 0x6, 0x0>, ISA_MICROMIPS, ASE_EVA;
- def LHE_MM : MMRel, LoadMemory<"lhe", GPR32Opnd, mem_simm9, null_frag,
- II_LHE>,
+ def LHE_MM : MMRel, LoadMemory<"lhe", GPR32Opnd, mem_simm9>,
POOL32C_LHUE_FM_MM<0x18, 0x6, 0x5>, ISA_MICROMIPS, ASE_EVA;
- def LHuE_MM : MMRel, LoadMemory<"lhue", GPR32Opnd, mem_simm9, null_frag,
- II_LHUE>,
+ def LHuE_MM : MMRel, LoadMemory<"lhue", GPR32Opnd, mem_simm9>,
POOL32C_LHUE_FM_MM<0x18, 0x6, 0x1>, ISA_MICROMIPS, ASE_EVA;
- def LWE_MM : MMRel, LoadMemory<"lwe", GPR32Opnd, mem_simm9, null_frag,
- II_LWE>,
+ def LWE_MM : MMRel, LoadMemory<"lwe", GPR32Opnd, mem_simm9>,
POOL32C_LHUE_FM_MM<0x18, 0x6, 0x7>, ISA_MICROMIPS, ASE_EVA;
- def SBE_MM : MMRel, StoreMemory<"sbe", GPR32Opnd, mem_simm9, null_frag,
- II_SBE>,
+ def SBE_MM : MMRel, StoreMemory<"sbe", GPR32Opnd, mem_simm9>,
POOL32C_LHUE_FM_MM<0x18, 0xa, 0x4>, ISA_MICROMIPS, ASE_EVA;
- def SHE_MM : MMRel, StoreMemory<"she", GPR32Opnd, mem_simm9, null_frag,
- II_SHE>,
+ def SHE_MM : MMRel, StoreMemory<"she", GPR32Opnd, mem_simm9>,
POOL32C_LHUE_FM_MM<0x18, 0xa, 0x5>, ISA_MICROMIPS, ASE_EVA;
- def SWE_MM : MMRel, StoreMemory<"swe", GPR32Opnd, mem_simm9, null_frag,
- II_SWE>,
+ def SWE_MM : MMRel, StoreMemory<"swe", GPR32Opnd, mem_simm9>,
POOL32C_LHUE_FM_MM<0x18, 0xa, 0x7>, ISA_MICROMIPS, ASE_EVA;
- def LWLE_MM : MMRel, LoadLeftRightMM<"lwle", MipsLWL, GPR32Opnd, mem_mm_9,
- II_LWLE>,
+ def LWLE_MM : MMRel, LoadLeftRightMM<"lwle", MipsLWL, GPR32Opnd, mem_mm_9>,
POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x2>,
ISA_MICROMIPS32_NOT_MIPS32R6, ASE_EVA;
- def LWRE_MM : MMRel, LoadLeftRightMM<"lwre", MipsLWR, GPR32Opnd, mem_mm_9,
- II_LWRE>,
+ def LWRE_MM : MMRel, LoadLeftRightMM<"lwre", MipsLWR, GPR32Opnd, mem_mm_9>,
POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x3>,
ISA_MICROMIPS32_NOT_MIPS32R6, ASE_EVA;
- def SWLE_MM : MMRel, StoreLeftRightMM<"swle", MipsSWL, GPR32Opnd, mem_mm_9,
- II_SWLE>,
+ def SWLE_MM : MMRel, StoreLeftRightMM<"swle", MipsSWL, GPR32Opnd, mem_mm_9>,
POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x0>,
ISA_MICROMIPS32_NOT_MIPS32R6, ASE_EVA;
- def SWRE_MM : MMRel, StoreLeftRightMM<"swre", MipsSWR, GPR32Opnd, mem_mm_9,
- II_SWRE>,
+ def SWRE_MM : MMRel, StoreLeftRightMM<"swre", MipsSWR, GPR32Opnd, mem_mm_9>,
POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x1>,
ISA_MICROMIPS32_NOT_MIPS32R6, ASE_EVA;
}
@@ -857,22 +838,18 @@ let DecoderNamespace = "MicroMips" in {
ISA_MICROMIPS;
/// Load and Store Instructions - unaligned
- def LWL_MM : MMRel, LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12,
- II_LWL>, LWL_FM_MM<0x0>,
- ISA_MICROMIPS32_NOT_MIPS32R6;
- def LWR_MM : MMRel, LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12,
- II_LWR>, LWL_FM_MM<0x1>,
- ISA_MICROMIPS32_NOT_MIPS32R6;
- def SWL_MM : MMRel, StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12,
- II_SWL>, LWL_FM_MM<0x8>,
- ISA_MICROMIPS32_NOT_MIPS32R6;
- def SWR_MM : MMRel, StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12,
- II_SWR>, LWL_FM_MM<0x9>,
- ISA_MICROMIPS32_NOT_MIPS32R6;
+ def LWL_MM : MMRel, LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>,
+ LWL_FM_MM<0x0>, ISA_MICROMIPS32_NOT_MIPS32R6;
+ def LWR_MM : MMRel, LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12>,
+ LWL_FM_MM<0x1>, ISA_MICROMIPS32_NOT_MIPS32R6;
+ def SWL_MM : MMRel, StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12>,
+ LWL_FM_MM<0x8>, ISA_MICROMIPS32_NOT_MIPS32R6;
+ def SWR_MM : MMRel, StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>,
+ LWL_FM_MM<0x9>, ISA_MICROMIPS32_NOT_MIPS32R6;
/// Load and Store Instructions - multiple
- def SWM32_MM : StoreMultMM<"swm32", II_SWM>, LWM_FM_MM<0xd>, ISA_MICROMIPS;
- def LWM32_MM : LoadMultMM<"lwm32", II_LWM>, LWM_FM_MM<0x5>, ISA_MICROMIPS;
+ def SWM32_MM : StoreMultMM<"swm32">, LWM_FM_MM<0xd>, ISA_MICROMIPS;
+ def LWM32_MM : LoadMultMM<"lwm32">, LWM_FM_MM<0x5>, ISA_MICROMIPS;
/// Load and Store Pair Instructions
def SWP_MM : StorePairMM<"swp">, LWM_FM_MM<0x9>, ISA_MICROMIPS;
@@ -892,15 +869,13 @@ let DecoderNamespace = "MicroMips" in {
def LWM_MM : LoadWordMultMM<"lwm">, ISA_MICROMIPS;
/// Move Conditional
- def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
- II_MOVZ>, ADD_FM_MM<0, 0x58>,
- ISA_MICROMIPS32_NOT_MIPS32R6;
- def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
- II_MOVN>, ADD_FM_MM<0, 0x18>,
- ISA_MICROMIPS32_NOT_MIPS32R6;
- def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT, MipsCMovFP_T>,
+ def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd>,
+ ADD_FM_MM<0, 0x58>, ISA_MICROMIPS32_NOT_MIPS32R6;
+ def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd>,
+ ADD_FM_MM<0, 0x18>, ISA_MICROMIPS32_NOT_MIPS32R6;
+ def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, MipsCMovFP_T>,
CMov_F_I_FM_MM<0x25>, ISA_MICROMIPS32_NOT_MIPS32R6;
- def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF, MipsCMovFP_F>,
+ def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, MipsCMovFP_F>,
CMov_F_I_FM_MM<0x5>, ISA_MICROMIPS32_NOT_MIPS32R6;
/// Move to/from HI/LO
def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>,
@@ -913,29 +888,29 @@ let DecoderNamespace = "MicroMips" in {
MFLO_FM_MM<0x075>, ISA_MICROMIPS32_NOT_MIPS32R6;
/// Multiply Add/Sub Instructions
- def MADD_MM : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>,
+ def MADD_MM : MMRel, MArithR<"madd", 1>, MULT_FM_MM<0x32c>,
ISA_MICROMIPS32_NOT_MIPS32R6;
- def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>,
+ def MADDU_MM : MMRel, MArithR<"maddu", 1>, MULT_FM_MM<0x36c>,
ISA_MICROMIPS32_NOT_MIPS32R6;
- def MSUB_MM : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>,
+ def MSUB_MM : MMRel, MArithR<"msub">, MULT_FM_MM<0x3ac>,
ISA_MICROMIPS32_NOT_MIPS32R6;
- def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>,
+ def MSUBU_MM : MMRel, MArithR<"msubu">, MULT_FM_MM<0x3ec>,
ISA_MICROMIPS32_NOT_MIPS32R6;
/// Count Leading
- def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd, II_CLZ>, CLO_FM_MM<0x16c>,
+ def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM_MM<0x16c>,
ISA_MICROMIPS;
- def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd, II_CLO>, CLO_FM_MM<0x12c>,
+ def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM_MM<0x12c>,
ISA_MICROMIPS;
/// Sign Ext In Register Instructions.
- def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
+ def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd>,
SEB_FM_MM<0x0ac>, ISA_MICROMIPS;
- def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
+ def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd>,
SEB_FM_MM<0x0ec>, ISA_MICROMIPS;
/// Word Swap Bytes Within Halfwords
- def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>,
+ def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd>,
SEB_FM_MM<0x1ec>, ISA_MICROMIPS;
// TODO: Add '0 < pos+size <= 32' constraint check to ext instruction
def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1, immZExt5,
@@ -1005,44 +980,44 @@ let DecoderNamespace = "MicroMips" in {
def SYNCI_MM : MMRel, SYNCI_FT<"synci", mem_mm_16>, SYNCI_FM_MM,
ISA_MICROMIPS32_NOT_MIPS32R6;
def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM, ISA_MICROMIPS;
- def SYSCALL_MM : MMRel, SYS_FT<"syscall", uimm10, II_SYSCALL>, SYS_FM_MM,
+ def SYSCALL_MM : MMRel, SYS_FT<"syscall", uimm10>, SYS_FM_MM,
ISA_MICROMIPS;
def WAIT_MM : MMRel, WaitMM<"wait">, WAIT_FM_MM, ISA_MICROMIPS;
- def ERET_MM : MMRel, ER_FT<"eret", II_ERET>, ER_FM_MM<0x3cd>,
+ def ERET_MM : MMRel, ER_FT<"eret">, ER_FM_MM<0x3cd>,
ISA_MICROMIPS;
- def DERET_MM : MMRel, ER_FT<"deret", II_DERET>, ER_FM_MM<0x38d>,
+ def DERET_MM : MMRel, ER_FT<"deret">, ER_FM_MM<0x38d>,
ISA_MICROMIPS;
- def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd, II_EI>, EI_FM_MM<0x15d>,
+ def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM_MM<0x15d>,
ISA_MICROMIPS;
- def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd, II_DI>, EI_FM_MM<0x11d>,
+ def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM_MM<0x11d>,
ISA_MICROMIPS;
def TRAP_MM : TrapBase<BREAK_MM>, ISA_MICROMIPS;
/// Trap Instructions
- def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd, uimm4, II_TEQ>, TEQ_FM_MM<0x0>,
+ def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd, uimm4>, TEQ_FM_MM<0x0>,
ISA_MICROMIPS;
- def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd, uimm4, II_TGE>, TEQ_FM_MM<0x08>,
+ def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd, uimm4>, TEQ_FM_MM<0x08>,
ISA_MICROMIPS;
- def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd, uimm4, II_TGEU>,
+ def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd, uimm4>,
TEQ_FM_MM<0x10>, ISA_MICROMIPS;
- def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd, uimm4, II_TLT>, TEQ_FM_MM<0x20>,
+ def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd, uimm4>, TEQ_FM_MM<0x20>,
ISA_MICROMIPS;
- def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd, uimm4, II_TLTU>,
+ def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd, uimm4>,
TEQ_FM_MM<0x28>, ISA_MICROMIPS;
- def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd, uimm4, II_TNE>, TEQ_FM_MM<0x30>,
+ def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd, uimm4>, TEQ_FM_MM<0x30>,
ISA_MICROMIPS;
- def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd, II_TEQI>, TEQI_FM_MM<0x0e>,
+ def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM_MM<0x0e>,
ISA_MICROMIPS32_NOT_MIPS32R6;
- def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd, II_TGEI>, TEQI_FM_MM<0x09>,
+ def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM_MM<0x09>,
ISA_MICROMIPS32_NOT_MIPS32R6;
- def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd, II_TGEIU>,
+ def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>,
TEQI_FM_MM<0x0b>, ISA_MICROMIPS32_NOT_MIPS32R6;
- def TLTI_MM : MMRel, TEQI_FT<"tlti", GPR32Opnd, II_TLTI>, TEQI_FM_MM<0x08>,
+ def TLTI_MM : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM_MM<0x08>,
ISA_MICROMIPS32_NOT_MIPS32R6;
- def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd, II_TTLTIU>,
+ def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd>,
TEQI_FM_MM<0x0a>, ISA_MICROMIPS32_NOT_MIPS32R6;
- def TNEI_MM : MMRel, TEQI_FT<"tnei", GPR32Opnd, II_TNEI>, TEQI_FM_MM<0x0c>,
+ def TNEI_MM : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM_MM<0x0c>,
ISA_MICROMIPS32_NOT_MIPS32R6;
/// Load-linked, Store-conditional
@@ -1057,35 +1032,35 @@ let DecoderNamespace = "MicroMips" in {
ISA_MICROMIPS, ASE_EVA;
let DecoderMethod = "DecodeCacheOpMM" in {
- def CACHE_MM : MMRel, CacheOp<"cache", mem_mm_12, II_CACHE>,
+ def CACHE_MM : MMRel, CacheOp<"cache", mem_mm_12>,
CACHE_PREF_FM_MM<0x08, 0x6>, ISA_MICROMIPS32_NOT_MIPS32R6;
- def PREF_MM : MMRel, CacheOp<"pref", mem_mm_12, II_PREF>,
+ def PREF_MM : MMRel, CacheOp<"pref", mem_mm_12>,
CACHE_PREF_FM_MM<0x18, 0x2>, ISA_MICROMIPS32_NOT_MIPS32R6;
}
let DecoderMethod = "DecodePrefeOpMM" in {
- def PREFE_MM : MMRel, CacheOp<"prefe", mem_mm_9, II_PREFE>,
+ def PREFE_MM : MMRel, CacheOp<"prefe", mem_mm_9>,
CACHE_PREFE_FM_MM<0x18, 0x2>, ISA_MICROMIPS, ASE_EVA;
- def CACHEE_MM : MMRel, CacheOp<"cachee", mem_mm_9, II_CACHEE>,
+ def CACHEE_MM : MMRel, CacheOp<"cachee", mem_mm_9>,
CACHE_PREFE_FM_MM<0x18, 0x3>, ISA_MICROMIPS, ASE_EVA;
}
- def SSNOP_MM : MMRel, Barrier<"ssnop", II_SSNOP>, BARRIER_FM_MM<0x1>,
+ def SSNOP_MM : MMRel, Barrier<"ssnop">, BARRIER_FM_MM<0x1>,
ISA_MICROMIPS;
- def EHB_MM : MMRel, Barrier<"ehb", II_EHB>, BARRIER_FM_MM<0x3>,
+ def EHB_MM : MMRel, Barrier<"ehb">, BARRIER_FM_MM<0x3>,
ISA_MICROMIPS;
- def PAUSE_MM : MMRel, Barrier<"pause", II_PAUSE>, BARRIER_FM_MM<0x5>,
+ def PAUSE_MM : MMRel, Barrier<"pause">, BARRIER_FM_MM<0x5>,
ISA_MICROMIPS;
- def TLBP_MM : MMRel, TLB<"tlbp", II_TLBP>, COP0_TLB_FM_MM<0x0d>,
+ def TLBP_MM : MMRel, TLB<"tlbp">, COP0_TLB_FM_MM<0x0d>,
ISA_MICROMIPS;
- def TLBR_MM : MMRel, TLB<"tlbr", II_TLBR>, COP0_TLB_FM_MM<0x4d>,
+ def TLBR_MM : MMRel, TLB<"tlbr">, COP0_TLB_FM_MM<0x4d>,
ISA_MICROMIPS;
- def TLBWI_MM : MMRel, TLB<"tlbwi", II_TLBWI>, COP0_TLB_FM_MM<0x8d>,
+ def TLBWI_MM : MMRel, TLB<"tlbwi">, COP0_TLB_FM_MM<0x8d>,
ISA_MICROMIPS;
- def TLBWR_MM : MMRel, TLB<"tlbwr", II_TLBWR>, COP0_TLB_FM_MM<0xcd>,
+ def TLBWR_MM : MMRel, TLB<"tlbwr">, COP0_TLB_FM_MM<0xcd>,
ISA_MICROMIPS;
- def SDBBP_MM : MMRel, SYS_FT<"sdbbp", uimm10, II_SDBBP>, SDBBP_FM_MM,
+ def SDBBP_MM : MMRel, SYS_FT<"sdbbp", uimm10>, SDBBP_FM_MM,
ISA_MICROMIPS;
def PREFX_MM : PrefetchIndexed<"prefx">, POOL32F_PREFX_FM_MM<0x15, 0x1A0>,
@@ -1093,9 +1068,9 @@ let DecoderNamespace = "MicroMips" in {
}
let AdditionalPredicates = [NotDSP] in {
- def PseudoMULT_MM : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>,
+ def PseudoMULT_MM : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult>,
ISA_MICROMIPS32_NOT_MIPS32R6;
- def PseudoMULTu_MM : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>,
+ def PseudoMULTu_MM : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu>,
ISA_MICROMIPS32_NOT_MIPS32R6;
def PseudoMFHI_MM : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>,
ISA_MICROMIPS32_NOT_MIPS32R6;
@@ -1103,13 +1078,13 @@ let AdditionalPredicates = [NotDSP] in {
ISA_MICROMIPS32_NOT_MIPS32R6;
def PseudoMTLOHI_MM : PseudoMTLOHI<ACC64, GPR32>,
ISA_MICROMIPS32_NOT_MIPS32R6;
- def PseudoMADD_MM : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,
+ def PseudoMADD_MM : MAddSubPseudo<MADD, MipsMAdd>,
ISA_MICROMIPS32_NOT_MIPS32R6;
- def PseudoMADDU_MM : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>,
+ def PseudoMADDU_MM : MAddSubPseudo<MADDU, MipsMAddu>,
ISA_MICROMIPS32_NOT_MIPS32R6;
- def PseudoMSUB_MM : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>,
+ def PseudoMSUB_MM : MAddSubPseudo<MSUB, MipsMSub>,
ISA_MICROMIPS32_NOT_MIPS32R6;
- def PseudoMSUBU_MM : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>,
+ def PseudoMSUBU_MM : MAddSubPseudo<MSUBU, MipsMSubu>,
ISA_MICROMIPS32_NOT_MIPS32R6;
}
@@ -1125,35 +1100,34 @@ def PseudoIndirectBranch_MM : PseudoIndirectBranchBase<JR_MM, GPR32Opnd>,
let DecoderNamespace = "MicroMips" in {
def RDHWR_MM : MMRel, R6MMR6Rel, ReadHardware<GPR32Opnd, HWRegsOpnd>,
RDHWR_FM_MM, ISA_MICROMIPS32_NOT_MIPS32R6;
- def LWU_MM : MMRel, LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU,
- mem_simm12>, LL_FM_MM<0xe>,
- ISA_MICROMIPS32_NOT_MIPS32R6;
+ def LWU_MM : MMRel, LoadMM<"lwu", GPR32Opnd, zextloadi32, mem_simm12>,
+ LL_FM_MM<0xe>, ISA_MICROMIPS32_NOT_MIPS32R6;
- def MFGC0_MM : MMRel, MfCop0MM<"mfgc0", GPR32Opnd, COP0Opnd, II_MFGC0>,
+ def MFGC0_MM : MMRel, MfCop0MM<"mfgc0", GPR32Opnd, COP0Opnd>,
POOL32A_MFTC0_FM_MM<0b10011, 0b111100>,
ISA_MICROMIPS32R5, ASE_VIRT;
- def MFHGC0_MM : MMRel, MfCop0MM<"mfhgc0", GPR32Opnd, COP0Opnd, II_MFHGC0>,
+ def MFHGC0_MM : MMRel, MfCop0MM<"mfhgc0", GPR32Opnd, COP0Opnd>,
POOL32A_MFTC0_FM_MM<0b10011, 0b110100>,
ISA_MICROMIPS32R5, ASE_VIRT;
- def MTGC0_MM : MMRel, MtCop0MM<"mtgc0", COP0Opnd, GPR32Opnd, II_MTGC0>,
+ def MTGC0_MM : MMRel, MtCop0MM<"mtgc0", COP0Opnd, GPR32Opnd>,
POOL32A_MFTC0_FM_MM<0b11011, 0b111100>,
ISA_MICROMIPS32R5, ASE_VIRT;
- def MTHGC0_MM : MMRel, MtCop0MM<"mthgc0", COP0Opnd, GPR32Opnd, II_MTHGC0>,
+ def MTHGC0_MM : MMRel, MtCop0MM<"mthgc0", COP0Opnd, GPR32Opnd>,
POOL32A_MFTC0_FM_MM<0b11011, 0b110100>,
ISA_MICROMIPS32R5, ASE_VIRT;
def HYPCALL_MM : MMRel, HypcallMM<"hypcall">, POOL32A_HYPCALL_FM_MM,
ISA_MICROMIPS32R5, ASE_VIRT;
- def TLBGINV_MM : MMRel, TLBINVMM<"tlbginv", II_TLBGINV>,
+ def TLBGINV_MM : MMRel, TLBINVMM<"tlbginv">,
POOL32A_TLBINV_FM_MM<0x105>, ISA_MICROMIPS32R5, ASE_VIRT;
- def TLBGINVF_MM : MMRel, TLBINVMM<"tlbginvf", II_TLBGINVF>,
+ def TLBGINVF_MM : MMRel, TLBINVMM<"tlbginvf">,
POOL32A_TLBINV_FM_MM<0x145>, ISA_MICROMIPS32R5, ASE_VIRT;
- def TLBGP_MM : MMRel, TLBINVMM<"tlbgp", II_TLBGP>,
+ def TLBGP_MM : MMRel, TLBINVMM<"tlbgp">,
POOL32A_TLBINV_FM_MM<0x5>, ISA_MICROMIPS32R5, ASE_VIRT;
- def TLBGR_MM : MMRel, TLBINVMM<"tlbgr", II_TLBGR>,
+ def TLBGR_MM : MMRel, TLBINVMM<"tlbgr">,
POOL32A_TLBINV_FM_MM<0x45>, ISA_MICROMIPS32R5, ASE_VIRT;
- def TLBGWI_MM : MMRel, TLBINVMM<"tlbgwi", II_TLBGWI>,
+ def TLBGWI_MM : MMRel, TLBINVMM<"tlbgwi">,
POOL32A_TLBINV_FM_MM<0x85>, ISA_MICROMIPS32R5, ASE_VIRT;
- def TLBGWR_MM : MMRel, TLBINVMM<"tlbgwr", II_TLBGWR>,
+ def TLBGWR_MM : MMRel, TLBINVMM<"tlbgwr">,
POOL32A_TLBINV_FM_MM<0xc5>, ISA_MICROMIPS32R5, ASE_VIRT;
}
@@ -1314,9 +1288,9 @@ def B_MM_Pseudo : UncondBranchMMPseudo<"b">, ISA_MICROMIPS;
let EncodingPredicates = [InMicroMips] in {
def SDIV_MM_Pseudo : MultDivPseudo<SDIV_MM, ACC64, GPR32Opnd, MipsDivRem,
- II_DIV, 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
+ 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
def UDIV_MM_Pseudo : MultDivPseudo<UDIV_MM, ACC64, GPR32Opnd, MipsDivRemU,
- II_DIVU, 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
+ 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>, ISA_MICROMIPS;
def : MipsInstAlias<"nop", (SLL_MM ZERO, ZERO, 0), 1>, ISA_MICROMIPS;
diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td
index 8176c63d8660c..41d38f10da816 100644
--- a/llvm/lib/Target/Mips/Mips.td
+++ b/llvm/lib/Target/Mips/Mips.td
@@ -247,7 +247,6 @@ def MIPS64 : HwMode<[IsPTR64bit]>;
//===----------------------------------------------------------------------===//
include "MipsRegisterInfo.td"
-include "MipsSchedule.td"
include "MipsInstrInfo.td"
include "MipsCallingConv.td"
include "MipsRegisterBanks.td"
diff --git a/llvm/lib/Target/Mips/Mips16InstrFormats.td b/llvm/lib/Target/Mips/Mips16InstrFormats.td
index 1a4bbacb48d3e..8879b97c85dae 100644
--- a/llvm/lib/Target/Mips/Mips16InstrFormats.td
+++ b/llvm/lib/Target/Mips/Mips16InstrFormats.td
@@ -32,8 +32,8 @@
// Base class for Mips 16 Format
// This class does not depend on the instruction size
//
-class MipsInst16_Base<dag outs, dag ins, string asmstr, list<dag> pattern,
- InstrItinClass itin>: Instruction
+class MipsInst16_Base<dag outs, dag ins, string asmstr,
+ list<dag> pattern>: Instruction
{
let Namespace = "Mips";
@@ -43,7 +43,6 @@ class MipsInst16_Base<dag outs, dag ins, string asmstr, list<dag> pattern,
let AsmString = asmstr;
let Pattern = pattern;
- let Itinerary = itin;
let Predicates = [InMips16Mode];
}
@@ -51,9 +50,9 @@ class MipsInst16_Base<dag outs, dag ins, string asmstr, list<dag> pattern,
//
// Generic Mips 16 Format
//
-class MipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
- InstrItinClass itin>:
- MipsInst16_Base<outs, ins, asmstr, pattern, itin>
+class MipsInst16<dag outs, dag ins, string asmstr,
+ list<dag> pattern>:
+ MipsInst16_Base<outs, ins, asmstr, pattern>
{
field bits<16> Inst;
bits<5> Opcode = 0;
@@ -67,18 +66,18 @@ class MipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
//
// For 32 bit extended instruction forms.
//
-class MipsInst16_32<dag outs, dag ins, string asmstr, list<dag> pattern,
- InstrItinClass itin>:
- MipsInst16_Base<outs, ins, asmstr, pattern, itin>
+class MipsInst16_32<dag outs, dag ins, string asmstr,
+ list<dag> pattern>:
+ MipsInst16_Base<outs, ins, asmstr, pattern>
{
field bits<32> Inst;
let Size=4;
}
-class MipsInst16_EXTEND<dag outs, dag ins, string asmstr, list<dag> pattern,
- InstrItinClass itin>:
- MipsInst16_32<outs, ins, asmstr, pattern, itin>
+class MipsInst16_EXTEND<dag outs, dag ins, string asmstr,
+ list<dag> pattern>:
+ MipsInst16_32<outs, ins, asmstr, pattern>
{
let Inst{31-27} = 0b11110;
}
@@ -87,7 +86,7 @@ class MipsInst16_EXTEND<dag outs, dag ins, string asmstr, list<dag> pattern,
// Mips Pseudo Instructions Format
class MipsPseudo16<dag outs, dag ins, string asmstr, list<dag> pattern>:
- MipsInst16<outs, ins, asmstr, pattern, IIPseudo> {
+ MipsInst16<outs, ins, asmstr, pattern> {
let isCodeGenOnly = 1;
let isPseudo = 1;
}
@@ -97,9 +96,9 @@ class MipsPseudo16<dag outs, dag ins, string asmstr, list<dag> pattern>:
// Format I instruction class in Mips : <|opcode|imm11|>
//===----------------------------------------------------------------------===//
-class FI16<bits<5> op, dag outs, dag ins, string asmstr, list<dag> pattern,
- InstrItinClass itin>:
- MipsInst16<outs, ins, asmstr, pattern, itin>
+class FI16<bits<5> op, dag outs, dag ins, string asmstr,
+ list<dag> pattern>:
+ MipsInst16<outs, ins, asmstr, pattern>
{
bits<11> imm11;
@@ -113,8 +112,8 @@ class FI16<bits<5> op, dag outs, dag ins, string asmstr, list<dag> pattern,
//===----------------------------------------------------------------------===//
class FRI16<bits<5> op, dag outs, dag ins, string asmstr,
- list<dag> pattern, InstrItinClass itin>:
- MipsInst16<outs, ins, asmstr, pattern, itin>
+ list<dag> pattern>:
+ MipsInst16<outs, ins, asmstr, pattern>
{
bits<3> rx;
bits<8> imm8;
@@ -130,8 +129,8 @@ class FRI16<bits<5> op, dag outs, dag ins, string asmstr,
//===----------------------------------------------------------------------===//
class FRR16<bits<5> _funct, dag outs, dag ins, string asmstr,
- list<dag> pattern, InstrItinClass itin>:
- MipsInst16<outs, ins, asmstr, pattern, itin>
+ list<dag> pattern>:
+ MipsInst16<outs, ins, asmstr, pattern>
{
bits<3> rx;
bits<3> ry;
@@ -146,8 +145,8 @@ class FRR16<bits<5> _funct, dag outs, dag ins, string asmstr,
}
class FRRBreak16<dag outs, dag ins, string asmstr,
- list<dag> pattern, InstrItinClass itin>:
- MipsInst16<outs, ins, asmstr, pattern, itin>
+ list<dag> pattern>:
+ MipsInst16<outs, ins, asmstr, pattern>
{
bits<6> Code;
bits<5> funct;
@@ -163,8 +162,8 @@ class FRRBreak16<dag outs, dag ins, string asmstr,
// For conversion functions.
//
class FRR_SF16<bits<5> _funct, bits<3> _subfunct, dag outs, dag ins,
- string asmstr, list<dag> pattern, InstrItinClass itin>:
- MipsInst16<outs, ins, asmstr, pattern, itin>
+ string asmstr, list<dag> pattern>:
+ MipsInst16<outs, ins, asmstr, pattern>
{
bits<3> rx;
bits<3> subfunct;
@@ -183,8 +182,8 @@ class FRR_SF16<bits<5> _funct, bits<3> _subfunct, dag outs, dag ins,
// just used for breakpoint (hardware and software) instructions.
//
class FC16<bits<5> _funct, dag outs, dag ins, string asmstr,
- list<dag> pattern, InstrItinClass itin>:
- MipsInst16<outs, ins, asmstr, pattern, itin>
+ list<dag> pattern>:
+ MipsInst16<outs, ins, asmstr, pattern>
{
bits<6> _code; // code is a keyword in tablegen
bits<5> funct;
@@ -201,8 +200,8 @@ class FC16<bits<5> _funct, dag outs, dag ins, string asmstr,
//
class FRR16_JALRC<bits<1> _nd, bits<1> _l, bits<1> r_a,
dag outs, dag ins, string asmstr,
- list<dag> pattern, InstrItinClass itin>:
- MipsInst16<outs, ins, asmstr, pattern, itin>
+ list<dag> pattern>:
+ MipsInst16<outs, ins, asmstr, pattern>
{
bits<3> rx;
bits<1> nd;
@@ -227,8 +226,8 @@ class FRR16_JALRC<bits<1> _nd, bits<1> _l, bits<1> r_a,
//===----------------------------------------------------------------------===//
class FRRI16<bits<5> op, dag outs, dag ins, string asmstr,
- list<dag> pattern, InstrItinClass itin>:
- MipsInst16<outs, ins, asmstr, pattern, itin>
+ list<dag> pattern>:
+ MipsInst16<outs, ins, asmstr, pattern>
{
bits<3> rx;
bits<3> ry;
@@ -247,8 +246,8 @@ class FRRI16<bits<5> op, dag outs, dag ins, string asmstr,
//===----------------------------------------------------------------------===//
class FRRR16<bits<2> _f, dag outs, dag ins, string asmstr,
- list<dag> pattern, InstrItinClass itin>:
- MipsInst16<outs, ins, asmstr, pattern, itin>
+ list<dag> pattern>:
+ MipsInst16<outs, ins, asmstr, pattern>
{
bits<3> rx;
bits<3> ry;
@@ -269,8 +268,8 @@ class FRRR16<bits<2> _f, dag outs, dag ins, string asmstr,
//===----------------------------------------------------------------------===//
class FRRI_A16<bits<1> _f, dag outs, dag ins, string asmstr,
- list<dag> pattern, InstrItinClass itin>:
- MipsInst16<outs, ins, asmstr, pattern, itin>
+ list<dag> pattern>:
+ MipsInst16<outs, ins, asmstr, pattern>
{
bits<3> rx;
bits<3> ry;
@@ -291,8 +290,8 @@ class FRRI_A16<bits<1> _f, dag outs, dag ins, string asmstr,
//===----------------------------------------------------------------------===//
class FSHIFT16<bits<2> _f, dag outs, dag ins, string asmstr,
- list<dag> pattern, InstrItinClass itin>:
- MipsInst16<outs, ins, asmstr, pattern, itin>
+ list<dag> pattern>:
+ MipsInst16<outs, ins, asmstr, pattern>
{
bits<3> rx;
bits<3> ry;
@@ -313,8 +312,8 @@ class FSHIFT16<bits<2> _f, dag outs, dag ins, string asmstr,
//===----------------------------------------------------------------------===//
class FI816<bits<3> _func, dag outs, dag ins, string asmstr,
- list<dag> pattern, InstrItinClass itin>:
- MipsInst16<outs, ins, asmstr, pattern, itin>
+ list<dag> pattern>:
+ MipsInst16<outs, ins, asmstr, pattern>
{
bits<3> func;
bits<8> imm8;
@@ -331,8 +330,8 @@ class FI816<bits<3> _func, dag outs, dag ins, string asmstr,
//===----------------------------------------------------------------------===//
class FI8_MOVR3216<dag outs, dag ins, string asmstr,
- list<dag> pattern, InstrItinClass itin>:
- MipsInst16<outs, ins, asmstr, pattern, itin>
+ list<dag> pattern>:
+ MipsInst16<outs, ins, asmstr, pattern>
{
// FIXME: this seems wrong? 'ry' should be 3 bits, and 'r32' 5?
bits<4> ry;
@@ -353,8 +352,8 @@ class FI8_MOVR3216<dag outs, dag ins, string asmstr,
//===----------------------------------------------------------------------===//
class FI8_MOV32R16<dag outs, dag ins, string asmstr,
- list<dag> pattern, InstrItinClass itin>:
- MipsInst16<outs, ins, asmstr, pattern, itin>
+ list<dag> pattern>:
+ MipsInst16<outs, ins, asmstr, pattern>
{
bits<3> func;
@@ -377,8 +376,8 @@ class FI8_MOV32R16<dag outs, dag ins, string asmstr,
//===----------------------------------------------------------------------===//
class FI8_SVRS16<bits<1> _s, dag outs, dag ins, string asmstr,
- list<dag> pattern, InstrItinClass itin>:
- MipsInst16<outs, ins, asmstr, pattern, itin>
+ list<dag> pattern>:
+ MipsInst16<outs, ins, asmstr, pattern>
{
bits<1> s;
bits<1> ra = 0;
@@ -404,8 +403,8 @@ class FI8_SVRS16<bits<1> _s, dag outs, dag ins, string asmstr,
//===----------------------------------------------------------------------===//
class FJAL16<bits<1> _X, dag outs, dag ins, string asmstr,
- list<dag> pattern, InstrItinClass itin>:
- MipsInst16_32<outs, ins, asmstr, pattern, itin>
+ list<dag> pattern>:
+ MipsInst16_32<outs, ins, asmstr, pattern>
{
bits<1> X;
bits<26> imm26;
@@ -427,8 +426,8 @@ class FJAL16<bits<1> _X, dag outs, dag ins, string asmstr,
//===----------------------------------------------------------------------===//
class FEXT_I16<bits<5> _eop, dag outs, dag ins, string asmstr,
- list<dag> pattern, InstrItinClass itin>:
- MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
+ list<dag> pattern>:
+ MipsInst16_EXTEND<outs, ins, asmstr, pattern>
{
bits<16> imm16;
bits<5> eop;
@@ -449,8 +448,8 @@ class FEXT_I16<bits<5> _eop, dag outs, dag ins, string asmstr,
//===----------------------------------------------------------------------===//
class FASMACRO16<dag outs, dag ins, string asmstr,
- list<dag> pattern, InstrItinClass itin>:
- MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
+ list<dag> pattern>:
+ MipsInst16_EXTEND<outs, ins, asmstr, pattern>
{
bits<3> select;
bits<3> p4;
@@ -478,8 +477,8 @@ class FASMACRO16<dag outs, dag ins, string asmstr,
//===----------------------------------------------------------------------===//
class FEXT_RI16<bits<5> _op, dag outs, dag ins, string asmstr,
- list<dag> pattern, InstrItinClass itin>:
- MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
+ list<dag> pattern>:
+ MipsInst16_EXTEND<outs, ins, asmstr, pattern>
{
bits<16> imm16;
bits<5> op;
@@ -502,8 +501,8 @@ class FEXT_RI16<bits<5> _op, dag outs, dag ins, string asmstr,
//===----------------------------------------------------------------------===//
class FEXT_RRI16<bits<5> _op, dag outs, dag ins, string asmstr,
- list<dag> pattern, InstrItinClass itin>:
- MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
+ list<dag> pattern>:
+ MipsInst16_EXTEND<outs, ins, asmstr, pattern>
{
bits<5> op;
bits<16> imm16;
@@ -527,8 +526,8 @@ class FEXT_RRI16<bits<5> _op, dag outs, dag ins, string asmstr,
//===----------------------------------------------------------------------===//
class FEXT_RRI_A16<bits<1> _f, dag outs, dag ins, string asmstr,
- list<dag> pattern, InstrItinClass itin>:
- MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
+ list<dag> pattern>:
+ MipsInst16_EXTEND<outs, ins, asmstr, pattern>
{
bits<15> imm15;
bits<3> rx;
@@ -553,8 +552,8 @@ class FEXT_RRI_A16<bits<1> _f, dag outs, dag ins, string asmstr,
//===----------------------------------------------------------------------===//
class FEXT_SHIFT16<bits<2> _f, dag outs, dag ins, string asmstr,
- list<dag> pattern, InstrItinClass itin>:
- MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
+ list<dag> pattern>:
+ MipsInst16_EXTEND<outs, ins, asmstr, pattern>
{
bits<6> sa6;
bits<3> rx;
@@ -580,8 +579,8 @@ class FEXT_SHIFT16<bits<2> _f, dag outs, dag ins, string asmstr,
//===----------------------------------------------------------------------===//
class FEXT_I816<bits<3> _funct, dag outs, dag ins, string asmstr,
- list<dag> pattern, InstrItinClass itin>:
- MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
+ list<dag> pattern>:
+ MipsInst16_EXTEND<outs, ins, asmstr, pattern>
{
bits<16> imm16;
bits<5> I8;
@@ -605,8 +604,8 @@ class FEXT_I816<bits<3> _funct, dag outs, dag ins, string asmstr,
//===----------------------------------------------------------------------===//
class FEXT_I8_SVRS16<bits<1> s_, dag outs, dag ins, string asmstr,
- list<dag> pattern, InstrItinClass itin>:
- MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
+ list<dag> pattern>:
+ MipsInst16_EXTEND<outs, ins, asmstr, pattern>
{
bits<3> xsregs =0;
bits<8> framesize =0;
diff --git a/llvm/lib/Target/Mips/Mips16InstrInfo.td b/llvm/lib/Target/Mips/Mips16InstrInfo.td
index 296414c6a06db..1505e50de1cf2 100644
--- a/llvm/lib/Target/Mips/Mips16InstrInfo.td
+++ b/llvm/lib/Target/Mips/Mips16InstrInfo.td
@@ -50,9 +50,9 @@ def pcrel16 : Operand<i32>;
// this is only used by bimm. the actual assembly value is a 12 bit signed
// number
//
-class FI16_ins<bits<5> op, string asmstr, InstrItinClass itin>:
+class FI16_ins<bits<5> op, string asmstr>:
FI16<op, (outs), (ins brtarget:$imm11),
- !strconcat(asmstr, "\t$imm11 # 16 bit inst"), [], itin>;
+ !strconcat(asmstr, "\t$imm11 # 16 bit inst"), []>;
//
//
@@ -60,57 +60,48 @@ class FI16_ins<bits<5> op, string asmstr, InstrItinClass itin>:
//
class FI816_ins_base<bits<3> _func, string asmstr,
- string asmstr2, InstrItinClass itin>:
+ string asmstr2>:
FI816<_func, (outs), (ins simm16:$imm8), !strconcat(asmstr, asmstr2),
- [], itin>;
+ []>;
-class FI816_ins<bits<3> _func, string asmstr,
- InstrItinClass itin>:
- FI816_ins_base<_func, asmstr, "\t$imm8 # 16 bit inst", itin>;
+class FI816_ins<bits<3> _func, string asmstr>:
+ FI816_ins_base<_func, asmstr, "\t$imm8 # 16 bit inst">;
-class FI816_SP_ins<bits<3> _func, string asmstr,
- InstrItinClass itin>:
- FI816_ins_base<_func, asmstr, "\t$$sp, $imm8 # 16 bit inst", itin>;
+class FI816_SP_ins<bits<3> _func, string asmstr>:
+ FI816_ins_base<_func, asmstr, "\t$$sp, $imm8 # 16 bit inst">;
//
// RI instruction format
//
-class FRI16_ins_base<bits<5> op, string asmstr, string asmstr2,
- InstrItinClass itin>:
+class FRI16_ins_base<bits<5> op, string asmstr, string asmstr2>:
FRI16<op, (outs CPU16Regs:$rx), (ins simm16:$imm8),
- !strconcat(asmstr, asmstr2), [], itin>;
+ !strconcat(asmstr, asmstr2), []>;
-class FRI16_ins<bits<5> op, string asmstr,
- InstrItinClass itin>:
- FRI16_ins_base<op, asmstr, "\t$rx, $imm8 \t# 16 bit inst", itin>;
+class FRI16_ins<bits<5> op, string asmstr>:
+ FRI16_ins_base<op, asmstr, "\t$rx, $imm8 \t# 16 bit inst">;
-class FRI16_TCP_ins<bits<5> _op, string asmstr,
- InstrItinClass itin>:
+class FRI16_TCP_ins<bits<5> _op, string asmstr>:
FRI16<_op, (outs CPU16Regs:$rx), (ins pcrel16:$imm8),
- !strconcat(asmstr, "\t$rx, $imm8\t# 16 bit inst"), [], itin>;
+ !strconcat(asmstr, "\t$rx, $imm8\t# 16 bit inst"), []>;
-class FRI16R_ins_base<bits<5> op, string asmstr, string asmstr2,
- InstrItinClass itin>:
+class FRI16R_ins_base<bits<5> op, string asmstr, string asmstr2>:
FRI16<op, (outs), (ins CPU16Regs:$rx, simm16:$imm8),
- !strconcat(asmstr, asmstr2), [], itin>;
+ !strconcat(asmstr, asmstr2), []>;
-class FRI16R_ins<bits<5> op, string asmstr,
- InstrItinClass itin>:
- FRI16R_ins_base<op, asmstr, "\t$rx, $imm8 \t# 16 bit inst", itin>;
+class FRI16R_ins<bits<5> op, string asmstr>:
+ FRI16R_ins_base<op, asmstr, "\t$rx, $imm8 \t# 16 bit inst">;
-class F2RI16_ins<bits<5> _op, string asmstr,
- InstrItinClass itin>:
+class F2RI16_ins<bits<5> _op, string asmstr>:
FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm8),
- !strconcat(asmstr, "\t$rx, $imm8\t# 16 bit inst"), [], itin> {
+ !strconcat(asmstr, "\t$rx, $imm8\t# 16 bit inst"), []> {
let Constraints = "$rx_ = $rx";
}
-class FRI16_B_ins<bits<5> _op, string asmstr,
- InstrItinClass itin>:
+class FRI16_B_ins<bits<5> _op, string asmstr>:
FRI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm8),
- !strconcat(asmstr, "\t$rx, $imm8 # 16 bit inst"), [], itin>;
+ !strconcat(asmstr, "\t$rx, $imm8 # 16 bit inst"), []>;
//
// Compare a register and immediate and place result in CC
// Implicit use of T8
@@ -126,20 +117,16 @@ class FEXT_CCRXI16_ins<string asmstr>:
// JAL and JALX instruction format
//
-class FJAL16_ins<bits<1> _X, string asmstr,
- InstrItinClass itin>:
+class FJAL16_ins<bits<1> _X, string asmstr>:
FJAL16<_X, (outs), (ins uimm26:$imm26),
- !strconcat(asmstr, "\t$imm26\n\tnop"),[],
- itin> {
+ !strconcat(asmstr, "\t$imm26\n\tnop"),[]> {
let isCodeGenOnly=1;
let Size=6;
}
-class FJALB16_ins<bits<1> _X, string asmstr,
- InstrItinClass itin>:
+class FJALB16_ins<bits<1> _X, string asmstr>:
FJAL16<_X, (outs), (ins uimm26:$imm26),
- !strconcat(asmstr, "\t$imm26\t# branch\n\tnop"),[],
- itin> {
+ !strconcat(asmstr, "\t$imm26\t# branch\n\tnop"),[]> {
let isCodeGenOnly=1;
let Size=6;
}
@@ -147,26 +134,24 @@ class FJALB16_ins<bits<1> _X, string asmstr,
//
// EXT-I instruction format
//
-class FEXT_I16_ins<bits<5> eop, string asmstr, InstrItinClass itin> :
+class FEXT_I16_ins<bits<5> eop, string asmstr> :
FEXT_I16<eop, (outs), (ins brtarget:$imm16),
- !strconcat(asmstr, "\t$imm16"),[], itin>;
+ !strconcat(asmstr, "\t$imm16"),[]>;
//
// EXT-I8 instruction format
//
class FEXT_I816_ins_base<bits<3> _func, string asmstr,
- string asmstr2, InstrItinClass itin>:
+ string asmstr2>:
FEXT_I816<_func, (outs), (ins simm16:$imm16), !strconcat(asmstr, asmstr2),
- [], itin>;
+ []>;
-class FEXT_I816_ins<bits<3> _func, string asmstr,
- InstrItinClass itin>:
- FEXT_I816_ins_base<_func, asmstr, "\t$imm16", itin>;
+class FEXT_I816_ins<bits<3> _func, string asmstr>:
+ FEXT_I816_ins_base<_func, asmstr, "\t$imm16">;
-class FEXT_I816_SP_ins<bits<3> _func, string asmstr,
- InstrItinClass itin>:
- FEXT_I816_ins_base<_func, asmstr, "\t$$sp, $imm16", itin>;
+class FEXT_I816_SP_ins<bits<3> _func, string asmstr>:
+ FEXT_I816_ins_base<_func, asmstr, "\t$$sp, $imm16">;
//
// Assembler formats in alphabetical order.
@@ -188,41 +173,34 @@ class FCCRR16_ins<string asmstr> :
// EXT-RI instruction format
//
-class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2,
- InstrItinClass itin>:
+class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2>:
FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm16),
- !strconcat(asmstr, asmstr2), [], itin>;
+ !strconcat(asmstr, asmstr2), []>;
-class FEXT_RI16_ins<bits<5> _op, string asmstr,
- InstrItinClass itin>:
- FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm16", itin>;
+class FEXT_RI16_ins<bits<5> _op, string asmstr>:
+ FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm16">;
-class FEXT_RI16R_ins_base<bits<5> _op, string asmstr, string asmstr2,
- InstrItinClass itin>:
+class FEXT_RI16R_ins_base<bits<5> _op, string asmstr, string asmstr2>:
FEXT_RI16<_op, (outs ), (ins CPU16Regs:$rx, simm16:$imm16),
- !strconcat(asmstr, asmstr2), [], itin>;
+ !strconcat(asmstr, asmstr2), []>;
-class FEXT_RI16R_ins<bits<5> _op, string asmstr,
- InstrItinClass itin>:
- FEXT_RI16R_ins_base<_op, asmstr, "\t$rx, $imm16", itin>;
+class FEXT_RI16R_ins<bits<5> _op, string asmstr>:
+ FEXT_RI16R_ins_base<_op, asmstr, "\t$rx, $imm16">;
-class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>:
- FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm16", itin>;
+class FEXT_RI16_PC_ins<bits<5> _op, string asmstr>:
+ FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm16">;
-class FEXT_RI16_B_ins<bits<5> _op, string asmstr,
- InstrItinClass itin>:
+class FEXT_RI16_B_ins<bits<5> _op, string asmstr>:
FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm16),
- !strconcat(asmstr, "\t$rx, $imm16"), [], itin>;
+ !strconcat(asmstr, "\t$rx, $imm16"), []>;
-class FEXT_RI16_TCP_ins<bits<5> _op, string asmstr,
- InstrItinClass itin>:
+class FEXT_RI16_TCP_ins<bits<5> _op, string asmstr>:
FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins pcrel16:$imm16),
- !strconcat(asmstr, "\t$rx, $imm16"), [], itin>;
+ !strconcat(asmstr, "\t$rx, $imm16"), []>;
-class FEXT_2RI16_ins<bits<5> _op, string asmstr,
- InstrItinClass itin>:
+class FEXT_2RI16_ins<bits<5> _op, string asmstr>:
FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm16),
- !strconcat(asmstr, "\t$rx, $imm16"), [], itin> {
+ !strconcat(asmstr, "\t$rx, $imm16"), []> {
let Constraints = "$rx_ = $rx";
}
@@ -230,32 +208,29 @@ class FEXT_2RI16_ins<bits<5> _op, string asmstr,
// EXT-RRI instruction format
//
-class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd,
- InstrItinClass itin>:
+class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd>:
FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins (MemOpnd $rx, $imm16):$addr),
- !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
+ !strconcat(asmstr, "\t$ry, $addr"), []>;
-class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd,
- InstrItinClass itin>:
+class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd>:
FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, (MemOpnd $rx, $imm16):$addr),
- !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
+ !strconcat(asmstr, "\t$ry, $addr"), []>;
//
//
// EXT-RRI-A instruction format
//
-class FEXT_RRI_A16_mem_ins<bits<1> op, string asmstr, Operand MemOpnd,
- InstrItinClass itin>:
+class FEXT_RRI_A16_mem_ins<bits<1> op, string asmstr, Operand MemOpnd>:
FEXT_RRI_A16<op, (outs CPU16Regs:$ry), (ins (MemOpnd $rx, $imm15):$addr),
- !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
+ !strconcat(asmstr, "\t$ry, $addr"), []>;
//
// EXT-SHIFT instruction format
//
-class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>:
+class FEXT_SHIFT16_ins<bits<2> _f, string asmstr>:
FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, uimm5:$sa6),
- !strconcat(asmstr, "\t$rx, $ry, $sa6"), [], itin>;
+ !strconcat(asmstr, "\t$rx, $ry, $sa6"), []>;
//
// EXT-T8I8
@@ -286,17 +261,17 @@ class FEXT_T8I8I16_ins<string asmstr, string asmstr2>:
//
// I8_MOVR32 instruction format (used only by the MOVR32 instructio
//
-class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>:
+class FI8_MOVR3216_ins<string asmstr>:
FI8_MOVR3216<(outs CPU16Regs:$ry), (ins GPR32:$r32),
- !strconcat(asmstr, "\t$ry, $r32"), [], itin>;
+ !strconcat(asmstr, "\t$ry, $r32"), []>;
//
// I8_MOV32R instruction format (used only by MOV32R instruction)
//
-class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>:
+class FI8_MOV32R16_ins<string asmstr>:
FI8_MOV32R16<(outs GPR32:$r32), (ins CPU16Regs:$rz),
- !strconcat(asmstr, "\t$r32, $rz"), [], itin>;
+ !strconcat(asmstr, "\t$r32, $rz"), []>;
//
// This are pseudo formats for multiply
@@ -321,19 +296,19 @@ class FMULT16_LO_ins<string asmstr> :
// RR-type instruction format
//
-class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
+class FRR16_ins<bits<5> f, string asmstr> :
FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
- !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
+ !strconcat(asmstr, "\t$rx, $ry"), []> {
}
-class FRRBreakNull16_ins<string asmstr, InstrItinClass itin> :
- FRRBreak16<(outs), (ins), asmstr, [], itin> {
+class FRRBreakNull16_ins<string asmstr> :
+ FRRBreak16<(outs), (ins), asmstr, []> {
let Code=0;
}
-class FRR16R_ins<bits<5> f, string asmstr, InstrItinClass itin> :
+class FRR16R_ins<bits<5> f, string asmstr> :
FRR16<f, (outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
- !strconcat(asmstr, "\t$rx, $ry"), [], itin> {
+ !strconcat(asmstr, "\t$rx, $ry"), []> {
}
class FRRTR16_ins<string asmstr> :
@@ -343,55 +318,53 @@ class FRRTR16_ins<string asmstr> :
//
// maybe refactor but need a $zero as a dummy first parameter
//
-class FRR16_div_ins<bits<5> f, string asmstr, InstrItinClass itin> :
+class FRR16_div_ins<bits<5> f, string asmstr> :
FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry),
- !strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ;
+ !strconcat(asmstr, "\t$$zero, $rx, $ry"), []> ;
-class FUnaryRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
+class FUnaryRR16_ins<bits<5> f, string asmstr> :
FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
- !strconcat(asmstr, "\t$rx, $ry"), [], itin> ;
+ !strconcat(asmstr, "\t$rx, $ry"), []> ;
-class FRR16_M_ins<bits<5> f, string asmstr,
- InstrItinClass itin> :
+class FRR16_M_ins<bits<5> f, string asmstr> :
FRR16<f, (outs CPU16Regs:$rx), (ins),
- !strconcat(asmstr, "\t$rx"), [], itin>;
+ !strconcat(asmstr, "\t$rx"), []>;
-class FRxRxRy16_ins<bits<5> f, string asmstr,
- InstrItinClass itin> :
+class FRxRxRy16_ins<bits<5> f, string asmstr> :
FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
!strconcat(asmstr, "\t$rz, $ry"),
- [], itin> {
+ []> {
let Constraints = "$rx = $rz";
}
let rx=0 in
class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_,
- string asmstr, InstrItinClass itin>:
+ string asmstr>:
FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t$$ra"),
- [], itin> ;
+ []> ;
class FRR16_JALRC_ins<bits<1> nd, bits<1> l, bits<1> ra,
- string asmstr, InstrItinClass itin>:
+ string asmstr>:
FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx),
- !strconcat(asmstr, "\t$rx"), [], itin> ;
+ !strconcat(asmstr, "\t$rx"), []> ;
class FRR_SF16_ins
<bits<5> _funct, bits<3> _subfunc,
- string asmstr, InstrItinClass itin>:
+ string asmstr>:
FRR_SF16<_funct, _subfunc, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_),
!strconcat(asmstr, "\t $rx"),
- [], itin> {
+ []> {
let Constraints = "$rx_ = $rx";
}
//
// RRR-type instruction format
//
-class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> :
+class FRRR16_ins<bits<2> _f, string asmstr> :
FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
- !strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>;
+ !strconcat(asmstr, "\t$rz, $rx, $ry"), []>;
//
// These Sel patterns support the generation of conditional move
@@ -526,20 +499,20 @@ class MayStore {
// Purpose: Add Immediate Unsigned Word (2-Operand, Extended)
// To add a constant to a 32-bit integer.
//
-def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIM16Alu>;
+def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu">;
-def AddiuRxRxImm16: F2RI16_ins<0b01001, "addiu", IIM16Alu>,
+def AddiuRxRxImm16: F2RI16_ins<0b01001, "addiu">,
ArithLogic16Defs<0> {
let AddedComplexity = 5;
}
-def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIM16Alu>,
+def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu">,
ArithLogic16Defs<0> {
let isCodeGenOnly = 1;
}
let DecoderMethod = "DecodeFIXMEInstruction" in
def AddiuRxRyOffMemX16:
- FEXT_RRI_A16_mem_ins<0, "addiu", mem16_ea, IIM16Alu>;
+ FEXT_RRI_A16_mem_ins<0, "addiu", mem16_ea>;
//
@@ -547,7 +520,7 @@ def AddiuRxRyOffMemX16:
// Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended)
// To add a constant to the program counter.
//
-def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIM16Alu>;
+def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu">;
//
// Format: ADDIU sp, immediate MIPS16e
@@ -555,14 +528,14 @@ def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIM16Alu>;
// To add a constant to the stack pointer.
//
def AddiuSpImm16
- : FI816_SP_ins<0b011, "addiu", IIM16Alu> {
+ : FI816_SP_ins<0b011, "addiu"> {
let Defs = [SP];
let Uses = [SP];
let AddedComplexity = 5;
}
def AddiuSpImmX16
- : FEXT_I816_SP_ins<0b011, "addiu", IIM16Alu> {
+ : FEXT_I816_SP_ins<0b011, "addiu"> {
let Defs = [SP];
let Uses = [SP];
}
@@ -573,14 +546,14 @@ def AddiuSpImmX16
// To add 32-bit integers.
//
-def AdduRxRyRz16: FRRR16_ins<01, "addu", IIM16Alu>, ArithLogic16Defs<1>;
+def AdduRxRyRz16: FRRR16_ins<01, "addu">, ArithLogic16Defs<1>;
//
// Format: AND rx, ry MIPS16e
// Purpose: AND
// To do a bitwise logical AND.
-def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIM16Alu>, ArithLogic16Defs<1>;
+def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and">, ArithLogic16Defs<1>;
//
@@ -588,7 +561,7 @@ def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIM16Alu>, ArithLogic16Defs<1>;
// Purpose: Branch on Equal to Zero
// To test a GPR then do a PC-relative conditional branch.
//
-def BeqzRxImm16: FRI16_B_ins<0b00100, "beqz", IIM16Alu>, cbranch16;
+def BeqzRxImm16: FRI16_B_ins<0b00100, "beqz">, cbranch16;
//
@@ -596,7 +569,7 @@ def BeqzRxImm16: FRI16_B_ins<0b00100, "beqz", IIM16Alu>, cbranch16;
// Purpose: Branch on Equal to Zero (Extended)
// To test a GPR then do a PC-relative conditional branch.
//
-def BeqzRxImmX16: FEXT_RI16_B_ins<0b00100, "beqz", IIM16Alu>, cbranch16;
+def BeqzRxImmX16: FEXT_RI16_B_ins<0b00100, "beqz">, cbranch16;
//
// Format: B offset MIPS16e
@@ -604,27 +577,27 @@ def BeqzRxImmX16: FEXT_RI16_B_ins<0b00100, "beqz", IIM16Alu>, cbranch16;
// To do an unconditional PC-relative branch.
//
-def Bimm16: FI16_ins<0b00010, "b", IIM16Alu>, branch16;
+def Bimm16: FI16_ins<0b00010, "b">, branch16;
// Format: B offset MIPS16e
// Purpose: Unconditional Branch
// To do an unconditional PC-relative branch.
//
-def BimmX16: FEXT_I16_ins<0b00010, "b", IIM16Alu>, branch16;
+def BimmX16: FEXT_I16_ins<0b00010, "b">, branch16;
//
// Format: BNEZ rx, offset MIPS16e
// Purpose: Branch on Not Equal to Zero
// To test a GPR then do a PC-relative conditional branch.
//
-def BnezRxImm16: FRI16_B_ins<0b00101, "bnez", IIM16Alu>, cbranch16;
+def BnezRxImm16: FRI16_B_ins<0b00101, "bnez">, cbranch16;
//
// Format: BNEZ rx, offset MIPS16e
// Purpose: Branch on Not Equal to Zero (Extended)
// To test a GPR then do a PC-relative conditional branch.
//
-def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIM16Alu>, cbranch16;
+def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez">, cbranch16;
//
@@ -632,17 +605,17 @@ def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIM16Alu>, cbranch16;
// Purpose: Breakpoint
// To cause a Breakpoint exception.
-def Break16: FRRBreakNull16_ins<"break 0", IIM16Alu>;
+def Break16: FRRBreakNull16_ins<"break 0">;
//
// Format: BTEQZ offset MIPS16e
// Purpose: Branch on T Equal to Zero (Extended)
// To test special register T then do a PC-relative conditional branch.
//
-def Bteqz16: FI816_ins<0b000, "bteqz", IIM16Alu>, cbranch16 {
+def Bteqz16: FI816_ins<0b000, "bteqz">, cbranch16 {
let Uses = [T8];
}
-def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIM16Alu>, cbranch16 {
+def BteqzX16: FEXT_I816_ins<0b000, "bteqz">, cbranch16 {
let Uses = [T8];
}
@@ -666,11 +639,11 @@ def BteqzT8SltiuX16: FEXT_T8I8I16_ins<"bteqz", "sltiu">,
// To test special register T then do a PC-relative conditional branch.
//
-def Btnez16: FI816_ins<0b001, "btnez", IIM16Alu>, cbranch16 {
+def Btnez16: FI816_ins<0b001, "btnez">, cbranch16 {
let Uses = [T8];
}
-def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIM16Alu> ,cbranch16 {
+def BtnezX16: FEXT_I816_ins<0b001, "btnez"> ,cbranch16 {
let Uses = [T8];
}
@@ -692,7 +665,7 @@ def BtnezT8SltiuX16: FEXT_T8I8I16_ins<"btnez", "sltiu">,
// Purpose: Compare
// To compare the contents of two GPRs.
//
-def CmpRxRy16: FRR16R_ins<0b01010, "cmp", IIM16Alu> {
+def CmpRxRy16: FRR16R_ins<0b01010, "cmp"> {
let Defs = [T8];
}
@@ -701,7 +674,7 @@ def CmpRxRy16: FRR16R_ins<0b01010, "cmp", IIM16Alu> {
// Purpose: Compare Immediate
// To compare a constant with the contents of a GPR.
//
-def CmpiRxImm16: FRI16R_ins<0b01110, "cmpi", IIM16Alu> {
+def CmpiRxImm16: FRI16R_ins<0b01110, "cmpi"> {
let Defs = [T8];
}
@@ -710,7 +683,7 @@ def CmpiRxImm16: FRI16R_ins<0b01110, "cmpi", IIM16Alu> {
// Purpose: Compare Immediate (Extended)
// To compare a constant with the contents of a GPR.
//
-def CmpiRxImmX16: FEXT_RI16R_ins<0b01110, "cmpi", IIM16Alu> {
+def CmpiRxImmX16: FEXT_RI16R_ins<0b01110, "cmpi"> {
let Defs = [T8];
}
@@ -720,7 +693,7 @@ def CmpiRxImmX16: FEXT_RI16R_ins<0b01110, "cmpi", IIM16Alu> {
// Purpose: Divide Word
// To divide 32-bit signed integers.
//
-def DivRxRy16: FRR16_div_ins<0b11010, "div", IIM16Alu> {
+def DivRxRy16: FRR16_div_ins<0b11010, "div"> {
let Defs = [HI0, LO0];
}
@@ -729,7 +702,7 @@ def DivRxRy16: FRR16_div_ins<0b11010, "div", IIM16Alu> {
// Purpose: Divide Unsigned Word
// To divide 32-bit unsigned integers.
//
-def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIM16Alu> {
+def DivuRxRy16: FRR16_div_ins<0b11011, "divu"> {
let Defs = [HI0, LO0];
}
//
@@ -739,13 +712,13 @@ def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIM16Alu> {
// region and preserve the current ISA.
//
-def Jal16 : FJAL16_ins<0b0, "jal", IIM16Alu> {
+def Jal16 : FJAL16_ins<0b0, "jal"> {
let hasDelaySlot = 0; // not true, but we add the nop for now
let isCall=1;
let Defs = [RA];
}
-def JalB16 : FJALB16_ins<0b0, "jal", IIM16Alu>, branch16 {
+def JalB16 : FJALB16_ins<0b0, "jal">, branch16 {
let hasDelaySlot = 0; // not true, but we add the nop for now
let isBranch=1;
let Defs = [RA];
@@ -758,7 +731,7 @@ def JalB16 : FJALB16_ins<0b0, "jal", IIM16Alu>, branch16 {
// address register.
//
-def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIM16Alu> {
+def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr"> {
let isBranch = 1;
let isIndirectBranch = 1;
let hasDelaySlot = 1;
@@ -767,7 +740,7 @@ def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIM16Alu> {
let isReturn=1;
}
-def JrcRa16: FRR16_JALRC_RA_only_ins<1, 1, "jrc", IIM16Alu> {
+def JrcRa16: FRR16_JALRC_RA_only_ins<1, 1, "jrc"> {
let isBranch = 1;
let isIndirectBranch = 1;
let isTerminator=1;
@@ -775,7 +748,7 @@ def JrcRa16: FRR16_JALRC_RA_only_ins<1, 1, "jrc", IIM16Alu> {
let isReturn=1;
}
-def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIM16Alu> {
+def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc"> {
let isBranch = 1;
let isIndirectBranch = 1;
let isTerminator=1;
@@ -786,7 +759,7 @@ def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIM16Alu> {
// Purpose: Load Byte (Extended)
// To load a byte from memory as a signed value.
//
-def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, II_LB>, MayLoad{
+def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16>, MayLoad{
let isCodeGenOnly = 1;
}
@@ -796,7 +769,7 @@ def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, II_LB>, MayLoad{
// To load a byte from memory as a unsigned value.
//
def LbuRxRyOffMemX16:
- FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, II_LBU>, MayLoad {
+ FEXT_RRI16_mem_ins<0b10100, "lbu", mem16>, MayLoad {
let isCodeGenOnly = 1;
}
@@ -805,7 +778,7 @@ def LbuRxRyOffMemX16:
// Purpose: Load Halfword signed (Extended)
// To load a halfword from memory as a signed value.
//
-def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, II_LH>, MayLoad{
+def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16>, MayLoad{
let isCodeGenOnly = 1;
}
@@ -815,7 +788,7 @@ def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, II_LH>, MayLoad{
// To load a halfword from memory as an unsigned value.
//
def LhuRxRyOffMemX16:
- FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, II_LHU>, MayLoad {
+ FEXT_RRI16_mem_ins<0b10100, "lhu", mem16>, MayLoad {
let isCodeGenOnly = 1;
}
@@ -824,16 +797,16 @@ def LhuRxRyOffMemX16:
// Purpose: Load Immediate
// To load a constant into a GPR.
//
-def LiRxImm16: FRI16_ins<0b01101, "li", IIM16Alu>;
+def LiRxImm16: FRI16_ins<0b01101, "li">;
//
// Format: LI rx, immediate MIPS16e
// Purpose: Load Immediate (Extended)
// To load a constant into a GPR.
//
-def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIM16Alu>;
+def LiRxImmX16: FEXT_RI16_ins<0b01101, "li">;
-def LiRxImmAlignX16: FEXT_RI16_ins<0b01101, ".align 2\n\tli", IIM16Alu> {
+def LiRxImmAlignX16: FEXT_RI16_ins<0b01101, ".align 2\n\tli"> {
let isCodeGenOnly = 1;
}
@@ -842,7 +815,7 @@ def LiRxImmAlignX16: FEXT_RI16_ins<0b01101, ".align 2\n\tli", IIM16Alu> {
// Purpose: Load Word (Extended)
// To load a word from memory as a signed value.
//
-def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, II_LW>, MayLoad{
+def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16>, MayLoad{
let isCodeGenOnly = 1;
}
@@ -851,25 +824,25 @@ def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, II_LW>, MayLoad{
// To load an SP-relative word from memory as a signed value.
//
let DecoderMethod = "DecodeFIXMEInstruction" in
-def LwRxSpImmX16: FEXT_RRI16_mem_ins<0b10010, "lw", mem16sp, II_LW>, MayLoad;
+def LwRxSpImmX16: FEXT_RRI16_mem_ins<0b10010, "lw", mem16sp>, MayLoad;
-def LwRxPcTcp16: FRI16_TCP_ins<0b10110, "lw", II_LW>, MayLoad;
+def LwRxPcTcp16: FRI16_TCP_ins<0b10110, "lw">, MayLoad;
-def LwRxPcTcpX16: FEXT_RI16_TCP_ins<0b10110, "lw", II_LW>, MayLoad;
+def LwRxPcTcpX16: FEXT_RI16_TCP_ins<0b10110, "lw">, MayLoad;
//
// Format: MOVE r32, rz MIPS16e
// Purpose: Move
// To move the contents of a GPR to a GPR.
//
-def Move32R16: FI8_MOV32R16_ins<"move", IIM16Alu>;
+def Move32R16: FI8_MOV32R16_ins<"move">;
//
// Format: MOVE ry, r32 MIPS16e
//Purpose: Move
// To move the contents of a GPR to a GPR.
//
-def MoveR3216: FI8_MOVR3216_ins<"move", IIM16Alu> {
+def MoveR3216: FI8_MOVR3216_ins<"move"> {
let isMoveReg = 1;
}
@@ -878,7 +851,7 @@ def MoveR3216: FI8_MOVR3216_ins<"move", IIM16Alu> {
// Purpose: Move From HI Register
// To copy the special purpose HI register to a GPR.
//
-def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIM16Alu> {
+def Mfhi16: FRR16_M_ins<0b10000, "mfhi"> {
let ry = 0b000; // no 'ry' field
let Uses = [HI0];
let hasSideEffects = 0;
@@ -890,7 +863,7 @@ def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIM16Alu> {
// Purpose: Move From LO Register
// To copy the special purpose LO register to a GPR.
//
-def Mflo16: FRR16_M_ins<0b10010, "mflo", IIM16Alu> {
+def Mflo16: FRR16_M_ins<0b10010, "mflo"> {
let ry = 0b000; // no 'ry' field
let Uses = [LO0];
let hasSideEffects = 0;
@@ -939,21 +912,21 @@ def MultuRxRyRz16: FMULT16_LO_ins<"multu"> {
// Purpose: Negate
// To negate an integer value.
//
-def NegRxRy16: FUnaryRR16_ins<0b11101, "neg", IIM16Alu>;
+def NegRxRy16: FUnaryRR16_ins<0b11101, "neg">;
//
// Format: NOT rx, ry MIPS16e
// Purpose: Not
// To complement an integer value
//
-def NotRxRy16: FUnaryRR16_ins<0b01111, "not", IIM16Alu>;
+def NotRxRy16: FUnaryRR16_ins<0b01111, "not">;
//
// Format: OR rx, ry MIPS16e
// Purpose: Or
// To do a bitwise logical OR.
//
-def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIM16Alu>, ArithLogic16Defs<1>;
+def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or">, ArithLogic16Defs<1>;
//
// Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize}
@@ -966,7 +939,7 @@ def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIM16Alu>, ArithLogic16Defs<1>;
def Restore16:
FI8_SVRS16<0b1, (outs), (ins variable_ops),
- "", [], II_RESTORE >, MayLoad {
+ "", [] >, MayLoad {
let isCodeGenOnly = 1;
let Defs = [SP];
let Uses = [SP];
@@ -975,7 +948,7 @@ def Restore16:
def RestoreX16:
FI8_SVRS16<0b1, (outs), (ins variable_ops),
- "", [], II_RESTORE >, MayLoad {
+ "", [] >, MayLoad {
let isCodeGenOnly = 1;
let Defs = [SP];
let Uses = [SP];
@@ -990,7 +963,7 @@ def RestoreX16:
//
def Save16:
FI8_SVRS16<0b1, (outs), (ins variable_ops),
- "", [], II_SAVE >, MayStore {
+ "", [] >, MayStore {
let isCodeGenOnly = 1;
let Uses = [SP];
let Defs = [SP];
@@ -998,7 +971,7 @@ def Save16:
def SaveX16:
FI8_SVRS16<0b1, (outs), (ins variable_ops),
- "", [], II_SAVE >, MayStore {
+ "", [] >, MayStore {
let isCodeGenOnly = 1;
let Uses = [SP];
let Defs = [SP];
@@ -1010,7 +983,7 @@ def SaveX16:
//
let DecoderMethod = "DecodeFIXMEInstruction" in
def SbRxRyOffMemX16:
- FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, II_SB>, MayStore;
+ FEXT_RRI16_mem2_ins<0b11000, "sb", mem16>, MayStore;
//
// Format: SEB rx MIPS16e
@@ -1018,7 +991,7 @@ def SbRxRyOffMemX16:
// Sign-extend least significant byte in register rx.
//
def SebRx16
- : FRR_SF16_ins<0b10001, 0b100, "seb", IIM16Alu>;
+ : FRR_SF16_ins<0b10001, 0b100, "seb">;
//
// Format: SEH rx MIPS16e
@@ -1026,7 +999,7 @@ def SebRx16
// Sign-extend least significant word in register rx.
//
def SehRx16
- : FRR_SF16_ins<0b10001, 0b101, "seh", IIM16Alu>;
+ : FRR_SF16_ins<0b10001, 0b101, "seh">;
//
// The Sel(T) instructions are pseudos
@@ -1149,28 +1122,28 @@ def SelTBtneZSltiu: SeliT<"btnez", "sltiu">;
//
let DecoderMethod = "DecodeFIXMEInstruction" in
def ShRxRyOffMemX16:
- FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, II_SH>, MayStore;
+ FEXT_RRI16_mem2_ins<0b11001, "sh", mem16>, MayStore;
//
// Format: SLL rx, ry, sa MIPS16e
// Purpose: Shift Word Left Logical (Extended)
// To execute a left-shift of a word by a fixed number of bits-0 to 31 bits.
//
-def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIM16Alu>;
+def SllX16: FEXT_SHIFT16_ins<0b00, "sll">;
//
// Format: SLLV ry, rx MIPS16e
// Purpose: Shift Word Left Logical Variable
// To execute a left-shift of a word by a variable number of bits.
//
-def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIM16Alu>;
+def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv">;
// Format: SLTI rx, immediate MIPS16e
// Purpose: Set on Less Than Immediate
// To record the result of a less-than comparison with a constant.
//
//
-def SltiRxImm16: FRI16R_ins<0b01010, "slti", IIM16Alu> {
+def SltiRxImm16: FRI16R_ins<0b01010, "slti"> {
let Defs = [T8];
}
@@ -1180,7 +1153,7 @@ def SltiRxImm16: FRI16R_ins<0b01010, "slti", IIM16Alu> {
// To record the result of a less-than comparison with a constant.
//
//
-def SltiRxImmX16: FEXT_RI16R_ins<0b01010, "slti", IIM16Alu> {
+def SltiRxImmX16: FEXT_RI16R_ins<0b01010, "slti"> {
let Defs = [T8];
}
@@ -1191,7 +1164,7 @@ def SltiCCRxImmX16: FEXT_CCRXI16_ins<"slti">;
// To record the result of a less-than comparison with a constant.
//
//
-def SltiuRxImm16: FRI16R_ins<0b01011, "sltiu", IIM16Alu> {
+def SltiuRxImm16: FRI16R_ins<0b01011, "sltiu"> {
let Defs = [T8];
}
@@ -1201,7 +1174,7 @@ def SltiuRxImm16: FRI16R_ins<0b01011, "sltiu", IIM16Alu> {
// To record the result of a less-than comparison with a constant.
//
//
-def SltiuRxImmX16: FEXT_RI16R_ins<0b01011, "sltiu", IIM16Alu> {
+def SltiuRxImmX16: FEXT_RI16R_ins<0b01011, "sltiu"> {
let Defs = [T8];
}
//
@@ -1216,7 +1189,7 @@ def SltiuCCRxImmX16: FEXT_CCRXI16_ins<"sltiu">;
// Purpose: Set on Less Than
// To record the result of a less-than comparison.
//
-def SltRxRy16: FRR16R_ins<0b00010, "slt", IIM16Alu>{
+def SltRxRy16: FRR16R_ins<0b00010, "slt">{
let Defs = [T8];
}
@@ -1226,7 +1199,7 @@ def SltCCRxRy16: FCCRR16_ins<"slt">;
// Purpose: Set on Less Than Unsigned
// To record the result of an unsigned less-than comparison.
//
-def SltuRxRy16: FRR16R_ins<0b00011, "sltu", IIM16Alu>{
+def SltuRxRy16: FRR16R_ins<0b00011, "sltu">{
let Defs = [T8];
}
@@ -1243,7 +1216,7 @@ def SltuCCRxRy16: FCCRR16_ins<"sltu">;
// To execute an arithmetic right-shift of a word by a variable
// number of bits.
//
-def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIM16Alu>;
+def SravRxRy16: FRxRxRy16_ins<0b00111, "srav">;
//
@@ -1252,7 +1225,7 @@ def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIM16Alu>;
// To execute an arithmetic right-shift of a word by a fixed
// number of bits-1 to 8 bits.
//
-def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIM16Alu>;
+def SraX16: FEXT_SHIFT16_ins<0b11, "sra">;
//
@@ -1261,7 +1234,7 @@ def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIM16Alu>;
// To execute a logical right-shift of a word by a variable
// number of bits.
//
-def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIM16Alu>;
+def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv">;
//
@@ -1270,14 +1243,14 @@ def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIM16Alu>;
// To execute a logical right-shift of a word by a fixed
// number of bits-1 to 31 bits.
//
-def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIM16Alu>;
+def SrlX16: FEXT_SHIFT16_ins<0b10, "srl">;
//
// Format: SUBU rz, rx, ry MIPS16e
// Purpose: Subtract Unsigned Word
// To subtract 32-bit integers
//
-def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIM16Alu>, ArithLogic16Defs<0>;
+def SubuRxRyRz16: FRRR16_ins<0b11, "subu">, ArithLogic16Defs<0>;
//
// Format: SW ry, offset(rx) MIPS16e
@@ -1285,7 +1258,7 @@ def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIM16Alu>, ArithLogic16Defs<0>;
// To store a word to memory.
//
let DecoderMethod = "DecodeFIXMEInstruction" in
-def SwRxRyOffMemX16: FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, II_SW>, MayStore;
+def SwRxRyOffMemX16: FEXT_RRI16_mem2_ins<0b11011, "sw", mem16>, MayStore;
//
// Format: SW rx, offset(sp) MIPS16e
@@ -1293,7 +1266,7 @@ def SwRxRyOffMemX16: FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, II_SW>, MayStore;
// To store an SP-relative word to memory.
//
let DecoderMethod = "DecodeFIXMEInstruction" in
-def SwRxSpImmX16: FEXT_RRI16_mem2_ins<0b11010, "sw", mem16sp, II_SW>, MayStore;
+def SwRxSpImmX16: FEXT_RRI16_mem2_ins<0b11010, "sw", mem16sp>, MayStore;
//
//
@@ -1301,7 +1274,7 @@ def SwRxSpImmX16: FEXT_RRI16_mem2_ins<0b11010, "sw", mem16sp, II_SW>, MayStore;
// Purpose: Xor
// To do a bitwise logical XOR.
//
-def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIM16Alu>, ArithLogic16Defs<1>;
+def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor">, ArithLogic16Defs<1>;
class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> {
let Predicates = [InMips16Mode];
@@ -1386,7 +1359,7 @@ def: Mips16Pat<(brind CPU16Regs:$rs), (JrcRx16 CPU16Regs:$rs)> {
let isCall=1, hasDelaySlot=0 in
def JumpLinkReg16:
FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rx),
- "jalrc\t$rx", [(MipsJmpLink CPU16Regs:$rx)], II_JALRC> {
+ "jalrc\t$rx", [(MipsJmpLink CPU16Regs:$rx)]> {
let Defs = [RA];
}
diff --git a/llvm/lib/Target/Mips/Mips32r6InstrFormats.td b/llvm/lib/Target/Mips/Mips32r6InstrFormats.td
index 8536c52028c3e..f0b02c6419a79 100644
--- a/llvm/lib/Target/Mips/Mips32r6InstrFormats.td
+++ b/llvm/lib/Target/Mips/Mips32r6InstrFormats.td
@@ -29,7 +29,7 @@ class MipsR6Arch<string opstr> {
string BaseOpcode = opstr;
}
-class MipsR6Inst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
+class MipsR6Inst : MipsInst<(outs), (ins), "", [], FrmOther> {
let DecoderNamespace = "Mips32r6_64r6";
let EncodingPredicates = [HasStdEnc];
}
diff --git a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
index 01a110993fe54..5283a5da43eee 100644
--- a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
+++ b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
@@ -213,101 +213,98 @@ class SIGRIE_ENC : SIGRIE_FM;
class CMP_CONDN_DESC_BASE<string CondStr, string Typestr,
RegisterOperand FGROpnd,
RegisterOperand FGRCCOpnd,
- InstrItinClass Itin,
SDPatternOperator Op = null_frag> {
dag OutOperandList = (outs FGRCCOpnd:$fd);
dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft");
list<dag> Pattern = [(set FGRCCOpnd:$fd, (Op FGROpnd:$fs, FGROpnd:$ft))];
bit isCTI = 1;
- InstrItinClass Itinerary = Itin;
}
multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr,
RegisterOperand FGROpnd,
- RegisterOperand FGRCCOpnd,
- InstrItinClass Itin>{
+ RegisterOperand FGRCCOpnd>{
let AdditionalPredicates = [NotInMicroMips] in {
def CMP_F_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_AF>,
- CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd, FGRCCOpnd, Itin>,
+ CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd, FGRCCOpnd>,
MipsR6Arch<!strconcat("cmp.af.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
def CMP_UN_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>,
- CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, FGRCCOpnd, Itin, setuo>,
+ CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, FGRCCOpnd, setuo>,
MipsR6Arch<!strconcat("cmp.un.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
def CMP_EQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>,
- CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, FGRCCOpnd, Itin,
+ CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, FGRCCOpnd,
setoeq>,
MipsR6Arch<!strconcat("cmp.eq.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
def CMP_UEQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
FIELD_CMP_COND_UEQ>,
- CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, FGRCCOpnd, Itin,
+ CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, FGRCCOpnd,
setueq>,
MipsR6Arch<!strconcat("cmp.ueq.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
def CMP_LT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>,
- CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, FGRCCOpnd, Itin,
+ CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, FGRCCOpnd,
setolt>,
MipsR6Arch<!strconcat("cmp.lt.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
def CMP_ULT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
FIELD_CMP_COND_ULT>,
- CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, FGRCCOpnd, Itin,
+ CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, FGRCCOpnd,
setult>,
MipsR6Arch<!strconcat("cmp.ult.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
def CMP_LE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>,
- CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, FGRCCOpnd, Itin,
+ CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, FGRCCOpnd,
setole>,
MipsR6Arch<!strconcat("cmp.le.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
def CMP_ULE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
FIELD_CMP_COND_ULE>,
- CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, FGRCCOpnd, Itin,
+ CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, FGRCCOpnd,
setule>,
MipsR6Arch<!strconcat("cmp.ule.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
let mayRaiseFPException = 1 in {
def CMP_SAF_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
FIELD_CMP_COND_SAF>,
- CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd, FGRCCOpnd, Itin>,
+ CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd, FGRCCOpnd>,
MipsR6Arch<!strconcat("cmp.saf.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
def CMP_SUN_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
FIELD_CMP_COND_SUN>,
- CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd, FGRCCOpnd, Itin>,
+ CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd, FGRCCOpnd>,
MipsR6Arch<!strconcat("cmp.sun.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
def CMP_SEQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
FIELD_CMP_COND_SEQ>,
- CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd, FGRCCOpnd, Itin>,
+ CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd, FGRCCOpnd>,
MipsR6Arch<!strconcat("cmp.seq.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
def CMP_SUEQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
FIELD_CMP_COND_SUEQ>,
- CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd, FGRCCOpnd, Itin>,
+ CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd, FGRCCOpnd>,
MipsR6Arch<!strconcat("cmp.sueq.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
def CMP_SLT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
FIELD_CMP_COND_SLT>,
- CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd, FGRCCOpnd, Itin>,
+ CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd, FGRCCOpnd>,
MipsR6Arch<!strconcat("cmp.slt.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
def CMP_SULT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
FIELD_CMP_COND_SULT>,
- CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd, FGRCCOpnd, Itin>,
+ CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd, FGRCCOpnd>,
MipsR6Arch<!strconcat("cmp.sult.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
def CMP_SLE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
FIELD_CMP_COND_SLE>,
- CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd, FGRCCOpnd, Itin>,
+ CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd, FGRCCOpnd>,
MipsR6Arch<!strconcat("cmp.sle.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
def CMP_SULE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
FIELD_CMP_COND_SULE>,
- CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd, FGRCCOpnd, Itin>,
+ CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd, FGRCCOpnd>,
MipsR6Arch<!strconcat("cmp.sule.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
}
@@ -321,55 +318,48 @@ multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr,
//===----------------------------------------------------------------------===//
class PCREL_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- Operand ImmOpnd, InstrItinClass itin>
+ Operand ImmOpnd>
: MipsR6Arch<instr_asm> {
dag OutOperandList = (outs GPROpnd:$rs);
dag InOperandList = (ins ImmOpnd:$imm);
string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
list<dag> Pattern = [];
- InstrItinClass Itinerary = itin;
}
-class ADDIUPC_DESC : PCREL_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2,
- II_ADDIUPC>;
-class LWPC_DESC: PCREL_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2, II_LWPC>;
+class ADDIUPC_DESC : PCREL_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>;
+class LWPC_DESC: PCREL_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>;
class ALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- Operand ImmOpnd, InstrItinClass itin>
+ Operand ImmOpnd>
: MipsR6Arch<instr_asm> {
dag OutOperandList = (outs GPROpnd:$rd);
dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
list<dag> Pattern = [];
- InstrItinClass Itinerary = itin;
}
-class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2, II_ALIGN>;
+class ALIGN_DESC : ALIGN_DESC_BASE<"align", GPR32Opnd, uimm2>;
-class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- InstrItinClass itin = NoItinerary>
+class ALUIPC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
: MipsR6Arch<instr_asm> {
dag OutOperandList = (outs GPROpnd:$rs);
dag InOperandList = (ins simm16:$imm);
string AsmString = !strconcat(instr_asm, "\t$rs, $imm");
list<dag> Pattern = [];
- InstrItinClass Itinerary = itin;
}
-class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd, II_ALUIPC>;
-class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd, II_AUIPC>;
+class ALUIPC_DESC : ALUIPC_DESC_BASE<"aluipc", GPR32Opnd>;
+class AUIPC_DESC : ALUIPC_DESC_BASE<"auipc", GPR32Opnd>;
-class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- InstrItinClass itin = NoItinerary>
+class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
: MipsR6Arch<instr_asm> {
dag OutOperandList = (outs GPROpnd:$rt);
dag InOperandList = (ins GPROpnd:$rs, uimm16:$imm);
string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
list<dag> Pattern = [];
- InstrItinClass Itinerary = itin;
}
-class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd, II_AUI>;
+class AUI_DESC : AUI_DESC_BASE<"aui", GPR32Opnd>;
class BRANCH_DESC_BASE {
bit isBranch = 1;
@@ -384,7 +374,6 @@ class BC_DESC_BASE<string instr_asm, DAGOperand opnd> : BRANCH_DESC_BASE,
dag OutOperandList = (outs);
string AsmString = !strconcat(instr_asm, "\t$offset");
bit isBarrier = 1;
- InstrItinClass Itinerary = II_BC;
bit isCTI = 1;
}
@@ -401,7 +390,6 @@ class CMP_BC_DESC_BASE<string instr_asm, DAGOperand opnd,
dag OutOperandList = (outs);
string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset");
list<Register> Defs = [AT];
- InstrItinClass Itinerary = II_BCCC;
bit hasForbiddenSlot = 1;
bit isCTI = 1;
}
@@ -413,7 +401,6 @@ class CMP_CBR_EQNE_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
dag OutOperandList = (outs);
string AsmString = !strconcat(instr_asm, "\t$rs, $offset");
list<Register> Defs = [AT];
- InstrItinClass Itinerary = II_BCCZC;
bit hasForbiddenSlot = 1;
bit isCTI = 1;
}
@@ -425,7 +412,6 @@ class CMP_CBR_RT_Z_DESC_BASE<string instr_asm, DAGOperand opnd,
dag OutOperandList = (outs);
string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
list<Register> Defs = [AT];
- InstrItinClass Itinerary = II_BCCZC;
bit hasForbiddenSlot = 1;
bit isCTI = 1;
}
@@ -446,7 +432,6 @@ class NAL_DESC : NAL_DESC_BASE<"nal"> {
class BALC_DESC : BC_DESC_BASE<"balc", brtarget26> {
bit isCall = 1;
list<Register> Defs = [RA];
- InstrItinClass Itinerary = II_BALC;
bit isCTI = 1;
}
@@ -473,7 +458,6 @@ class COP1_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
dag OutOperandList = (outs);
string AsmString = instr_asm;
bit hasDelaySlot = 1;
- InstrItinClass Itinerary = II_BC1CCZ;
}
class BC1EQZ_DESC : COP1_BCCZ_DESC_BASE<"bc1eqz $ft, $offset">;
@@ -485,7 +469,6 @@ class COP2_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
string AsmString = instr_asm;
bit hasDelaySlot = 1;
bit isCTI = 1;
- InstrItinClass Itinerary = II_BC2CCZ;
}
class BC2EQZ_DESC : COP2_BCCZ_DESC_BASE<"bc2eqz $ct, $offset">;
@@ -495,27 +478,25 @@ class BOVC_DESC : CMP_BC_DESC_BASE<"bovc", brtarget, GPR32Opnd>;
class BNVC_DESC : CMP_BC_DESC_BASE<"bnvc", brtarget, GPR32Opnd>;
class JMP_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd,
- RegisterOperand GPROpnd,
- InstrItinClass itin = NoItinerary>
+ RegisterOperand GPROpnd>
: MipsR6Arch<opstr> {
dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
string AsmString = !strconcat(opstr, "\t$rt, $offset");
list<dag> Pattern = [];
bit hasDelaySlot = 0;
- InstrItinClass Itinerary = itin;
bit isCTI = 1;
bit isBranch = 1;
bit isIndirectBranch = 1;
}
class JIALC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
- GPR32Opnd, II_JIALC> {
+ GPR32Opnd> {
bit isCall = 1;
list<Register> Defs = [RA];
}
class JIC_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
- GPR32Opnd, II_JIALC> {
+ GPR32Opnd> {
bit isBarrier = 1;
bit isTerminator = 1;
list<Register> Defs = [AT];
@@ -528,52 +509,46 @@ class JR_HB_R6_DESC : JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
bit isTerminator=1;
bit isBarrier=1;
bit isCTI = 1;
- InstrItinClass Itinerary = II_JR_HB;
}
-class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- InstrItinClass itin>
+class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
: MipsR6Arch<instr_asm> {
dag OutOperandList = (outs GPROpnd:$rd);
dag InOperandList = (ins GPROpnd:$rt);
string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
list<dag> Pattern = [];
- InstrItinClass Itinerary = itin;
}
-class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd, II_BITSWAP>;
+class BITSWAP_DESC : BITSWAP_DESC_BASE<"bitswap", GPR32Opnd>;
class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- InstrItinClass itin,
SDPatternOperator Op=null_frag>
: MipsR6Arch<instr_asm> {
dag OutOperandList = (outs GPROpnd:$rd);
dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
- InstrItinClass Itinerary = itin;
// This instruction doesn't trap division by zero itself. We must insert
// teq instructions as well.
bit usesCustomInserter = 1;
}
-class DVPEVP_DESC_BASE<string instr_asm, InstrItinClass Itin>
+class DVPEVP_DESC_BASE<string instr_asm>
: MipsR6Arch<instr_asm> {
dag OutOperandList = (outs GPR32Opnd:$rt);
dag InOperandList = (ins);
string AsmString = !strconcat(instr_asm, "\t$rt");
list<dag> Pattern = [];
- InstrItinClass Itinerary = Itin;
bit hasUnModeledSideEffects = 1;
}
-class DVP_DESC : DVPEVP_DESC_BASE<"dvp", II_DVP>;
-class EVP_DESC : DVPEVP_DESC_BASE<"evp", II_EVP>;
+class DVP_DESC : DVPEVP_DESC_BASE<"dvp">;
+class EVP_DESC : DVPEVP_DESC_BASE<"evp">;
-class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd, II_DIV, sdiv>;
-class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd, II_DIVU, udiv>;
-class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd, II_MOD, srem>;
-class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd, II_MODU, urem>;
+class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd, sdiv>;
+class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd, udiv>;
+class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd, srem>;
+class MODU_DESC : DIVMOD_DESC_BASE<"modu", GPR32Opnd, urem>;
class BEQZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"beqzalc", brtarget, GPR32Opnd> {
list<Register> Defs = [RA];
@@ -600,24 +575,21 @@ class BNEZALC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bnezalc", brtarget, GPR32Opnd> {
}
class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- InstrItinClass itin,
SDPatternOperator Op=null_frag> : MipsR6Arch<instr_asm> {
dag OutOperandList = (outs GPROpnd:$rd);
dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
- InstrItinClass Itinerary = itin;
}
-class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd, II_MUH, mulhs>;
-class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd, II_MUHU, mulhu>;
-class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd, II_MUL, mul>;
-class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd, II_MULU>;
+class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd, mulhs>;
+class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd, mulhu>;
+class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd, mul>;
+class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>;
class COP1_SEL_DESC_BASE<string instr_asm,
RegisterOperand FGROpnd,
- RegisterOperand FGRCCOpnd,
- InstrItinClass itin> {
+ RegisterOperand FGRCCOpnd> {
dag OutOperandList = (outs FGROpnd:$fd);
dag InOperandList = (ins FGRCCOpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
@@ -625,12 +597,11 @@ class COP1_SEL_DESC_BASE<string instr_asm,
FGROpnd:$ft,
FGROpnd:$fs))];
string Constraints = "$fd_in = $fd";
- InstrItinClass Itinerary = itin;
}
-class SEL_D_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd, FGR64CCOpnd, II_SEL_D>,
+class SEL_D_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd, FGR64CCOpnd>,
MipsR6Arch<"sel.d">;
-class SEL_S_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd, FGR32CCOpnd, II_SEL_S>,
+class SEL_S_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd, FGR32CCOpnd>,
MipsR6Arch<"sel.s">;
class SELEQNE_Z_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
@@ -639,180 +610,158 @@ class SELEQNE_Z_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
list<dag> Pattern = [];
- InstrItinClass Itinerary = II_SELCCZ;
}
class SELEQZ_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR32Opnd>;
class SELNEZ_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR32Opnd>;
-class COP1_4R_DESC_BASE<string instr_asm, RegisterOperand FGROpnd,
- InstrItinClass itin = NoItinerary> {
+class COP1_4R_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
dag OutOperandList = (outs FGROpnd:$fd);
dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
list<dag> Pattern = [];
string Constraints = "$fd_in = $fd";
- InstrItinClass Itinerary = itin;
}
-class MADDF_S_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd, II_MADDF_S>;
-class MADDF_D_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd, II_MADDF_D>;
-class MSUBF_S_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd, II_MSUBF_S>;
-class MSUBF_D_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd, II_MSUBF_D>;
+class MADDF_S_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>;
+class MADDF_D_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>;
+class MSUBF_S_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>;
+class MSUBF_D_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>;
-class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd,
- InstrItinClass itin> {
+class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
dag OutOperandList = (outs FGROpnd:$fd);
dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
list<dag> Pattern = [];
- InstrItinClass Itinerary = itin;
}
-class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd, II_MAX_S>;
-class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd, II_MAX_D>;
-class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd, II_MIN_S>;
-class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd, II_MIN_D>;
+class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>;
+class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>;
+class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>;
+class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>;
-class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd, II_MAX_S>;
-class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd, II_MAX_D>;
-class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd, II_MIN_D>;
-class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd, II_MIN_S>;
+class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>;
+class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>;
+class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>;
+class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>;
-class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd,
- InstrItinClass itin> {
+class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
dag OutOperandList = (outs FGROpnd:$fd);
dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
list<dag> Pattern = [];
- InstrItinClass Itinerary = itin;
}
-class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd, II_SELCCZ_S>,
+class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>,
MipsR6Arch<"seleqz.s">;
-class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd, II_SELCCZ_D>,
+class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>,
MipsR6Arch<"seleqz.d">;
-class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd, II_SELCCZ_S>,
+class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>,
MipsR6Arch<"selnez.s">;
-class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd, II_SELCCZ_D>,
+class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>,
MipsR6Arch<"selnez.d">;
-class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd,
- InstrItinClass itin> {
+class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
dag OutOperandList = (outs FGROpnd:$fd);
dag InOperandList = (ins FGROpnd:$fs);
string AsmString = !strconcat(instr_asm, "\t$fd, $fs");
list<dag> Pattern = [];
- InstrItinClass Itinerary = itin;
}
-class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd, II_RINT_S>;
-class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd, II_RINT_D>;
-class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd, II_CLASS_S>;
-class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd, II_CLASS_D>;
+class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>;
+class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>;
+class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>;
+class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>;
-class CACHE_HINT_DESC<string instr_asm, Operand MemOpnd, InstrItinClass itin>
+class CACHE_HINT_DESC<string instr_asm, Operand MemOpnd>
: MipsR6Arch<instr_asm> {
dag OutOperandList = (outs);
dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
list<dag> Pattern = [];
string DecoderMethod = "DecodeCacheeOp_CacheOpR6";
- InstrItinClass Itinerary = itin;
}
-class CACHE_DESC : CACHE_HINT_DESC<"cache", mem_simm9, II_CACHE>;
-class PREF_DESC : CACHE_HINT_DESC<"pref", mem_simm9, II_PREF>;
+class CACHE_DESC : CACHE_HINT_DESC<"cache", mem_simm9>;
+class PREF_DESC : CACHE_HINT_DESC<"pref", mem_simm9>;
-class COP2LD_DESC_BASE<string instr_asm, RegisterOperand COPOpnd,
- InstrItinClass itin> {
+class COP2LD_DESC_BASE<string instr_asm, RegisterOperand COPOpnd> {
dag OutOperandList = (outs COPOpnd:$rt);
dag InOperandList = (ins mem_simm11:$addr);
string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
list<dag> Pattern = [];
bit mayLoad = 1;
string DecoderMethod = "DecodeFMemCop2R6";
- InstrItinClass Itinerary = itin;
}
-class LDC2_R6_DESC : COP2LD_DESC_BASE<"ldc2", COP2Opnd, II_LDC2>;
-class LWC2_R6_DESC : COP2LD_DESC_BASE<"lwc2", COP2Opnd, II_LWC2>;
+class LDC2_R6_DESC : COP2LD_DESC_BASE<"ldc2", COP2Opnd>;
+class LWC2_R6_DESC : COP2LD_DESC_BASE<"lwc2", COP2Opnd>;
-class COP2ST_DESC_BASE<string instr_asm, RegisterOperand COPOpnd,
- InstrItinClass itin> {
+class COP2ST_DESC_BASE<string instr_asm, RegisterOperand COPOpnd> {
dag OutOperandList = (outs);
dag InOperandList = (ins COPOpnd:$rt, mem_simm11:$addr);
string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
list<dag> Pattern = [];
bit mayStore = 1;
string DecoderMethod = "DecodeFMemCop2R6";
- InstrItinClass Itinerary = itin;
}
-class SDC2_R6_DESC : COP2ST_DESC_BASE<"sdc2", COP2Opnd, II_SDC2>;
-class SWC2_R6_DESC : COP2ST_DESC_BASE<"swc2", COP2Opnd, II_SWC2>;
+class SDC2_R6_DESC : COP2ST_DESC_BASE<"sdc2", COP2Opnd>;
+class SWC2_R6_DESC : COP2ST_DESC_BASE<"swc2", COP2Opnd>;
class LSA_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- Operand ImmOpnd, InstrItinClass itin>
+ Operand ImmOpnd>
: MipsR6Arch<instr_asm> {
dag OutOperandList = (outs GPROpnd:$rd);
dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $imm2");
list<dag> Pattern = [];
- InstrItinClass Itinerary = itin;
}
-class LSA_R6_DESC : LSA_R6_DESC_BASE<"lsa", GPR32Opnd, uimm2_plus1, II_LSA>;
+class LSA_R6_DESC : LSA_R6_DESC_BASE<"lsa", GPR32Opnd, uimm2_plus1>;
class LL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- Operand MemOpnd, InstrItinClass itin>
+ Operand MemOpnd>
: MipsR6Arch<instr_asm> {
dag OutOperandList = (outs GPROpnd:$rt);
dag InOperandList = (ins MemOpnd:$addr);
string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
list<dag> Pattern = [];
bit mayLoad = 1;
- InstrItinClass Itinerary = itin;
}
-class LL_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd, mem_simm9_exp, II_LL>;
+class LL_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd, mem_simm9_exp>;
-class SC_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- InstrItinClass itin> {
+class SC_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
dag OutOperandList = (outs GPROpnd:$dst);
dag InOperandList = (ins GPROpnd:$rt, mem_simm9_exp:$addr);
string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
list<dag> Pattern = [];
bit mayStore = 1;
string Constraints = "$rt = $dst";
- InstrItinClass Itinerary = itin;
}
-class SC_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd, II_SC>;
+class SC_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd>;
-class CLO_CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- InstrItinClass itin>
+class CLO_CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
: MipsR6Arch<instr_asm> {
dag OutOperandList = (outs GPROpnd:$rd);
dag InOperandList = (ins GPROpnd:$rs);
string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
- InstrItinClass Itinerary = itin;
}
-class CLO_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- InstrItinClass itin> :
- CLO_CLZ_R6_DESC_BASE<instr_asm, GPROpnd, itin> {
+class CLO_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> :
+ CLO_CLZ_R6_DESC_BASE<instr_asm, GPROpnd> {
list<dag> Pattern = [(set GPROpnd:$rd, (ctlz (not GPROpnd:$rs)))];
}
-class CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- InstrItinClass itin> :
- CLO_CLZ_R6_DESC_BASE<instr_asm, GPROpnd, itin> {
+class CLZ_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> :
+ CLO_CLZ_R6_DESC_BASE<instr_asm, GPROpnd> {
list<dag> Pattern = [(set GPROpnd:$rd, (ctlz GPROpnd:$rs))];
}
-class CLO_R6_DESC : CLO_R6_DESC_BASE<"clo", GPR32Opnd, II_CLO>;
-class CLZ_R6_DESC : CLZ_R6_DESC_BASE<"clz", GPR32Opnd, II_CLZ>;
+class CLO_R6_DESC : CLO_R6_DESC_BASE<"clo", GPR32Opnd>;
+class CLZ_R6_DESC : CLZ_R6_DESC_BASE<"clz", GPR32Opnd>;
class SDBBP_R6_DESC {
dag OutOperandList = (outs);
@@ -820,48 +769,44 @@ class SDBBP_R6_DESC {
string AsmString = "sdbbp\t$code_";
list<dag> Pattern = [];
bit isCTI = 1;
- InstrItinClass Itinerary = II_SDBBP;
}
-class CRC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- InstrItinClass itin> : MipsR6Arch<instr_asm> {
+class CRC_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
+ : MipsR6Arch<instr_asm> {
dag OutOperandList = (outs GPROpnd:$rd);
dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
list<dag> Pattern = [];
- InstrItinClass Itinerary = itin;
}
-class CRC32B_DESC : CRC_DESC_BASE<"crc32b", GPR32Opnd, II_CRC32B>;
-class CRC32H_DESC : CRC_DESC_BASE<"crc32h", GPR32Opnd, II_CRC32H>;
-class CRC32W_DESC : CRC_DESC_BASE<"crc32w", GPR32Opnd, II_CRC32W>;
-class CRC32CB_DESC : CRC_DESC_BASE<"crc32cb", GPR32Opnd, II_CRC32CB>;
-class CRC32CH_DESC : CRC_DESC_BASE<"crc32ch", GPR32Opnd, II_CRC32CH>;
-class CRC32CW_DESC : CRC_DESC_BASE<"crc32cw", GPR32Opnd, II_CRC32CW>;
+class CRC32B_DESC : CRC_DESC_BASE<"crc32b", GPR32Opnd>;
+class CRC32H_DESC : CRC_DESC_BASE<"crc32h", GPR32Opnd>;
+class CRC32W_DESC : CRC_DESC_BASE<"crc32w", GPR32Opnd>;
+class CRC32CB_DESC : CRC_DESC_BASE<"crc32cb", GPR32Opnd>;
+class CRC32CH_DESC : CRC_DESC_BASE<"crc32ch", GPR32Opnd>;
+class CRC32CW_DESC : CRC_DESC_BASE<"crc32cw", GPR32Opnd>;
-class GINV_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- InstrItinClass itin> : MipsR6Arch<instr_asm> {
+class GINV_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
+ : MipsR6Arch<instr_asm> {
dag OutOperandList = (outs);
dag InOperandList = (ins GPROpnd:$rs, uimm2:$type_);
string AsmString = !strconcat(instr_asm, "\t$rs, $type_");
list<dag> Pattern = [];
- InstrItinClass Itinerary = itin;
bit hasSideEffects = 1;
}
-class GINVI_DESC : GINV_DESC_BASE<"ginvi", GPR32Opnd, II_GINVI> {
+class GINVI_DESC : GINV_DESC_BASE<"ginvi", GPR32Opnd> {
bits<2> type_ = 0b00;
dag InOperandList = (ins GPR32Opnd:$rs);
string AsmString = "ginvi\t$rs";
}
-class GINVT_DESC : GINV_DESC_BASE<"ginvt", GPR32Opnd, II_GINVT>;
+class GINVT_DESC : GINV_DESC_BASE<"ginvt", GPR32Opnd>;
class SIGRIE_DESC {
dag OutOperandList = (outs);
dag InOperandList = (ins uimm16:$code_);
string AsmString = "sigrie\t$code_";
list<dag> Pattern = [];
- InstrItinClass Itinerary = II_SIGRIE;
}
//===----------------------------------------------------------------------===//
@@ -914,8 +859,8 @@ let AdditionalPredicates = [NotInMicroMips] in {
}
def CLO_R6 : R6MMR6Rel, CLO_R6_ENC, CLO_R6_DESC, ISA_MIPS32R6;
def CLZ_R6 : R6MMR6Rel, CLZ_R6_ENC, CLZ_R6_DESC, ISA_MIPS32R6;
-defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd, FGR32CCOpnd, II_CMP_CC_S>;
-defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd, FGR64CCOpnd, II_CMP_CC_D>;
+defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd, FGR32CCOpnd>;
+defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd, FGR64CCOpnd>;
let AdditionalPredicates = [NotInMicroMips] in {
def DIV : R6MMR6Rel, DIV_ENC, DIV_DESC, ISA_MIPS32R6;
def DIVU : R6MMR6Rel, DIVU_ENC, DIVU_DESC, ISA_MIPS32R6;
@@ -1186,14 +1131,13 @@ let AdditionalPredicates = [NotInMicroMips] in {
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
hasExtraSrcRegAllocReq = 1, isCTI = 1, Defs = [AT], hasPostISelHook = 1 in {
class TailCallRegR6<Instruction JumpInst, Register RT, RegisterOperand RO> :
- PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>,
+ PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)]>,
PseudoInstExpansion<(JumpInst RT:$rt, RO:$rs)>;
}
class PseudoIndirectBranchBaseR6<Instruction JumpInst, Register RT,
RegisterOperand RO> :
- MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)],
- II_IndirectBranchPseudo>,
+ MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)]>,
PseudoInstExpansion<(JumpInst RT:$rt, RO:$rs)> {
let isTerminator=1;
let isBarrier=1;
diff --git a/llvm/lib/Target/Mips/Mips64InstrInfo.td b/llvm/lib/Target/Mips/Mips64InstrInfo.td
index b22b0acf49507..1321dd3bde211 100644
--- a/llvm/lib/Target/Mips/Mips64InstrInfo.td
+++ b/llvm/lib/Target/Mips/Mips64InstrInfo.td
@@ -116,10 +116,10 @@ let isPseudo = 1, isCodeGenOnly = 1, hasNoSchedulingInfo = 1 in {
//===----------------------------------------------------------------------===//
let DecoderNamespace = "Mips64" in {
/// Arithmetic Instructions (ALU Immediate)
-def DADDi : ArithLogicI<"daddi", simm16_64, GPR64Opnd, II_DADDI>,
+def DADDi : ArithLogicI<"daddi", simm16_64, GPR64Opnd>,
ADDI_FM<0x18>, ISA_MIPS3_NOT_32R6_64R6;
let AdditionalPredicates = [NotInMicroMips] in {
- def DADDiu : ArithLogicI<"daddiu", simm16_64, GPR64Opnd, II_DADDIU,
+ def DADDiu : ArithLogicI<"daddiu", simm16_64, GPR64Opnd,
immSExt16, add>,
ADDI_FM<0x19>, IsAsCheapAsAMove, ISA_MIPS3;
}
@@ -129,94 +129,94 @@ def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>,
SLTI_FM<0xa>, GPR_64;
def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, GPR64Opnd>,
SLTI_FM<0xb>, GPR_64;
-def ANDi64 : ArithLogicI<"andi", uimm16_64, GPR64Opnd, II_AND, immZExt16, and>,
+def ANDi64 : ArithLogicI<"andi", uimm16_64, GPR64Opnd, immZExt16, and>,
ADDI_FM<0xc>, GPR_64;
-def ORi64 : ArithLogicI<"ori", uimm16_64, GPR64Opnd, II_OR, immZExt16, or>,
+def ORi64 : ArithLogicI<"ori", uimm16_64, GPR64Opnd, immZExt16, or>,
ADDI_FM<0xd>, GPR_64;
-def XORi64 : ArithLogicI<"xori", uimm16_64, GPR64Opnd, II_XOR, immZExt16, xor>,
+def XORi64 : ArithLogicI<"xori", uimm16_64, GPR64Opnd, immZExt16, xor>,
ADDI_FM<0xe>, GPR_64;
def LUi64 : LoadUpper<"lui", GPR64Opnd, uimm16_64_relaxed>, LUI_FM, GPR_64;
}
/// Arithmetic Instructions (3-Operand, R-Type)
let AdditionalPredicates = [NotInMicroMips] in {
- def DADD : ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>, ADD_FM<0, 0x2c>,
+ def DADD : ArithLogicR<"dadd", GPR64Opnd, 1>, ADD_FM<0, 0x2c>,
ISA_MIPS3;
- def DADDu : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>,
+ def DADDu : ArithLogicR<"daddu", GPR64Opnd, 1, add>,
ADD_FM<0, 0x2d>, ISA_MIPS3;
- def DSUBu : ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>,
+ def DSUBu : ArithLogicR<"dsubu", GPR64Opnd, 0, sub>,
ADD_FM<0, 0x2f>, ISA_MIPS3;
- def DSUB : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>,
+ def DSUB : ArithLogicR<"dsub", GPR64Opnd, 0>, ADD_FM<0, 0x2e>,
ISA_MIPS3;
}
let isCodeGenOnly = 1 in {
def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>, GPR_64;
def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>, GPR_64;
-def AND64 : ArithLogicR<"and", GPR64Opnd, 1, II_AND, and>, ADD_FM<0, 0x24>,
+def AND64 : ArithLogicR<"and", GPR64Opnd, 1, and>, ADD_FM<0, 0x24>,
GPR_64;
-def OR64 : ArithLogicR<"or", GPR64Opnd, 1, II_OR, or>, ADD_FM<0, 0x25>,
+def OR64 : ArithLogicR<"or", GPR64Opnd, 1, or>, ADD_FM<0, 0x25>,
GPR_64;
-def XOR64 : ArithLogicR<"xor", GPR64Opnd, 1, II_XOR, xor>, ADD_FM<0, 0x26>,
+def XOR64 : ArithLogicR<"xor", GPR64Opnd, 1, xor>, ADD_FM<0, 0x26>,
GPR_64;
def NOR64 : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>, GPR_64;
}
/// Shift Instructions
let AdditionalPredicates = [NotInMicroMips] in {
- def DSLL : shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL, mshl_64,
+ def DSLL : shift_rotate_imm<"dsll", uimm6, GPR64Opnd, mshl_64,
immZExt6>,
SRA_FM<0x38, 0>, ISA_MIPS3;
- def DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, msrl_64,
+ def DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, msrl_64,
immZExt6>,
SRA_FM<0x3a, 0>, ISA_MIPS3;
- def DSRA : shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA, msra_64,
+ def DSRA : shift_rotate_imm<"dsra", uimm6, GPR64Opnd, msra_64,
immZExt6>,
SRA_FM<0x3b, 0>, ISA_MIPS3;
- def DSLLV : shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, mshl_64>,
+ def DSLLV : shift_rotate_reg<"dsllv", GPR64Opnd, mshl_64>,
SRLV_FM<0x14, 0>, ISA_MIPS3;
- def DSRAV : shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, msra_64>,
+ def DSRAV : shift_rotate_reg<"dsrav", GPR64Opnd, msra_64>,
SRLV_FM<0x17, 0>, ISA_MIPS3;
- def DSRLV : shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, msrl_64>,
+ def DSRLV : shift_rotate_reg<"dsrlv", GPR64Opnd, msrl_64>,
SRLV_FM<0x16, 0>, ISA_MIPS3;
- def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, II_DSLL32>,
+ def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd>,
SRA_FM<0x3c, 0>, ISA_MIPS3;
- def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, II_DSRL32>,
+ def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd>,
SRA_FM<0x3e, 0>, ISA_MIPS3;
- def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>,
+ def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd>,
SRA_FM<0x3f, 0>, ISA_MIPS3;
// Rotate Instructions
- def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr,
+ def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, rotr,
immZExt6>,
SRA_FM<0x3a, 1>, ISA_MIPS64R2;
- def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>,
+ def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, rotr>,
SRLV_FM<0x16, 1>, ISA_MIPS64R2;
- def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, II_DROTR32>,
+ def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd>,
SRA_FM<0x3e, 1>, ISA_MIPS64R2;
}
/// Load and Store Instructions
/// aligned
let isCodeGenOnly = 1 in {
-def LB64 : Load<"lb", GPR64Opnd, sextloadi8, II_LB>, LW_FM<0x20>, GPR_64;
-def LBu64 : Load<"lbu", GPR64Opnd, zextloadi8, II_LBU>, LW_FM<0x24>, GPR_64;
-def LH64 : Load<"lh", GPR64Opnd, sextloadi16, II_LH>, LW_FM<0x21>, GPR_64;
-def LHu64 : Load<"lhu", GPR64Opnd, zextloadi16, II_LHU>, LW_FM<0x25>, GPR_64;
-def LW64 : Load<"lw", GPR64Opnd, sextloadi32, II_LW>, LW_FM<0x23>, GPR_64;
-def SB64 : Store<"sb", GPR64Opnd, truncstorei8, II_SB>, LW_FM<0x28>, GPR_64;
-def SH64 : Store<"sh", GPR64Opnd, truncstorei16, II_SH>, LW_FM<0x29>,
+def LB64 : Load<"lb", GPR64Opnd, sextloadi8>, LW_FM<0x20>, GPR_64;
+def LBu64 : Load<"lbu", GPR64Opnd, zextloadi8>, LW_FM<0x24>, GPR_64;
+def LH64 : Load<"lh", GPR64Opnd, sextloadi16>, LW_FM<0x21>, GPR_64;
+def LHu64 : Load<"lhu", GPR64Opnd, zextloadi16>, LW_FM<0x25>, GPR_64;
+def LW64 : Load<"lw", GPR64Opnd, sextloadi32>, LW_FM<0x23>, GPR_64;
+def SB64 : Store<"sb", GPR64Opnd, truncstorei8>, LW_FM<0x28>, GPR_64;
+def SH64 : Store<"sh", GPR64Opnd, truncstorei16>, LW_FM<0x29>,
GPR_64;
-def SW64 : Store<"sw", GPR64Opnd, truncstorei32, II_SW>, LW_FM<0x2b>,
+def SW64 : Store<"sw", GPR64Opnd, truncstorei32>, LW_FM<0x2b>,
GPR_64;
}
let AdditionalPredicates = [NotInMicroMips] in {
- def LWu : MMRel, Load<"lwu", GPR64Opnd, zextloadi32, II_LWU>,
+ def LWu : MMRel, Load<"lwu", GPR64Opnd, zextloadi32>,
LW_FM<0x27>, ISA_MIPS3;
- def LD : LoadMemory<"ld", GPR64Opnd, mem_simmptr, load, II_LD>,
+ def LD : LoadMemory<"ld", GPR64Opnd, mem_simmptr, load>,
LW_FM<0x37>, ISA_MIPS3;
- def SD : StoreMemory<"sd", GPR64Opnd, mem_simmptr, store, II_SD>,
+ def SD : StoreMemory<"sd", GPR64Opnd, mem_simmptr, store>,
LW_FM<0x3f>, ISA_MIPS3;
}
@@ -224,23 +224,23 @@ let AdditionalPredicates = [NotInMicroMips] in {
/// load/store left/right
let isCodeGenOnly = 1 in {
-def LWL64 : LoadLeftRight<"lwl", MipsLWL, GPR64Opnd, II_LWL>, LW_FM<0x22>,
+def LWL64 : LoadLeftRight<"lwl", MipsLWL, GPR64Opnd>, LW_FM<0x22>,
GPR_64;
-def LWR64 : LoadLeftRight<"lwr", MipsLWR, GPR64Opnd, II_LWR>, LW_FM<0x26>,
+def LWR64 : LoadLeftRight<"lwr", MipsLWR, GPR64Opnd>, LW_FM<0x26>,
GPR_64;
-def SWL64 : StoreLeftRight<"swl", MipsSWL, GPR64Opnd, II_SWL>, LW_FM<0x2a>,
+def SWL64 : StoreLeftRight<"swl", MipsSWL, GPR64Opnd>, LW_FM<0x2a>,
GPR_64;
-def SWR64 : StoreLeftRight<"swr", MipsSWR, GPR64Opnd, II_SWR>, LW_FM<0x2e>,
+def SWR64 : StoreLeftRight<"swr", MipsSWR, GPR64Opnd>, LW_FM<0x2e>,
GPR_64;
}
-def LDL : LoadLeftRight<"ldl", MipsLDL, GPR64Opnd, II_LDL>, LW_FM<0x1a>,
+def LDL : LoadLeftRight<"ldl", MipsLDL, GPR64Opnd>, LW_FM<0x1a>,
ISA_MIPS3_NOT_32R6_64R6;
-def LDR : LoadLeftRight<"ldr", MipsLDR, GPR64Opnd, II_LDR>, LW_FM<0x1b>,
+def LDR : LoadLeftRight<"ldr", MipsLDR, GPR64Opnd>, LW_FM<0x1b>,
ISA_MIPS3_NOT_32R6_64R6;
-def SDL : StoreLeftRight<"sdl", MipsSDL, GPR64Opnd, II_SDL>, LW_FM<0x2c>,
+def SDL : StoreLeftRight<"sdl", MipsSDL, GPR64Opnd>, LW_FM<0x2c>,
ISA_MIPS3_NOT_32R6_64R6;
-def SDR : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd, II_SDR>, LW_FM<0x2d>,
+def SDR : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd>, LW_FM<0x2d>,
ISA_MIPS3_NOT_32R6_64R6;
/// Load-linked, Store-conditional
@@ -310,31 +310,31 @@ let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,
/// Multiply and Divide Instructions.
let AdditionalPredicates = [NotInMicroMips] in {
- def DMULT : Mult<"dmult", II_DMULT, GPR64Opnd, [HI0_64, LO0_64]>,
+ def DMULT : Mult<"dmult", GPR64Opnd, [HI0_64, LO0_64]>,
MULT_FM<0, 0x1c>,
ISA_MIPS3_NOT_32R6_64R6_R5900;
- def DMULTu : Mult<"dmultu", II_DMULTU, GPR64Opnd, [HI0_64, LO0_64]>,
+ def DMULTu : Mult<"dmultu", GPR64Opnd, [HI0_64, LO0_64]>,
MULT_FM<0, 0x1d>,
ISA_MIPS3_NOT_32R6_64R6_R5900;
}
-def PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult, II_DMULT>,
+def PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult>,
ISA_MIPS3_NOT_32R6_64R6_R5900;
def PseudoDMULTu
- : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu, II_DMULTU>,
+ : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu>,
ISA_MIPS3_NOT_32R6_64R6_R5900;
let AdditionalPredicates = [NotInMicroMips] in {
- def DSDIV : Div<"ddiv", II_DDIV, GPR64Opnd, [HI0_64, LO0_64]>,
+ def DSDIV : Div<"ddiv", GPR64Opnd, [HI0_64, LO0_64]>,
MULT_FM<0, 0x1e>,
ISA_MIPS3_NOT_32R6_64R6_R5900;
- def DUDIV : Div<"ddivu", II_DDIVU, GPR64Opnd, [HI0_64, LO0_64]>,
+ def DUDIV : Div<"ddivu", GPR64Opnd, [HI0_64, LO0_64]>,
MULT_FM<0, 0x1f>,
ISA_MIPS3_NOT_32R6_64R6_R5900;
}
def PseudoDSDIV
- : MultDivPseudo<DSDIV, ACC128, GPR64Opnd, MipsDivRem, II_DDIV, 0, 1, 1>,
+ : MultDivPseudo<DSDIV, ACC128, GPR64Opnd, MipsDivRem, 0, 1, 1>,
ISA_MIPS3_NOT_32R6_64R6_R5900;
def PseudoDUDIV
- : MultDivPseudo<DUDIV, ACC128, GPR64Opnd, MipsDivRemU, II_DDIVU, 0, 1, 1>,
+ : MultDivPseudo<DUDIV, ACC128, GPR64Opnd, MipsDivRemU, 0, 1, 1>,
ISA_MIPS3_NOT_32R6_64R6_R5900;
let isCodeGenOnly = 1 in {
@@ -353,23 +353,23 @@ def PseudoMFLO64 : PseudoMFLOHI<GPR64, ACC128, MipsMFLO>,
def PseudoMTLOHI64 : PseudoMTLOHI<ACC128, GPR64>, ISA_MIPS3_NOT_32R6_64R6;
/// Sign Ext In Register Instructions.
-def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd, II_SEB>, SEB_FM<0x10, 0x20>,
+def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd>, SEB_FM<0x10, 0x20>,
ISA_MIPS32R2, GPR_64;
-def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd, II_SEH>, SEB_FM<0x18, 0x20>,
+def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd>, SEB_FM<0x18, 0x20>,
ISA_MIPS32R2, GPR_64;
}
/// Count Leading
let AdditionalPredicates = [NotInMicroMips] in {
- def DCLZ : CountLeading0<"dclz", GPR64Opnd, II_DCLZ>, CLO_FM<0x24>,
+ def DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>,
ISA_MIPS64_NOT_64R6, GPR_64;
- def DCLO : CountLeading1<"dclo", GPR64Opnd, II_DCLO>, CLO_FM<0x25>,
+ def DCLO : CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>,
ISA_MIPS64_NOT_64R6, GPR_64;
/// Double Word Swap Bytes/HalfWords
- def DSBH : SubwordSwap<"dsbh", GPR64Opnd, II_DSBH>, SEB_FM<2, 0x24>,
+ def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>,
ISA_MIPS64R2;
- def DSHD : SubwordSwap<"dshd", GPR64Opnd, II_DSHD>, SEB_FM<5, 0x24>,
+ def DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>,
ISA_MIPS64R2;
def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>,
@@ -419,18 +419,18 @@ let isCodeGenOnly = 1, AdditionalPredicates = [NotInMicroMips] in {
def DEXT64_32
: InstSE<(outs GPR64Opnd:$rt),
(ins GPR32Opnd:$rs, uimm5_report_uimm6:$pos, uimm5_plus1:$size),
- "dext $rt, $rs, $pos, $size", [], II_EXT, FrmR, "dext">,
+ "dext $rt, $rs, $pos, $size", [], FrmR, "dext">,
EXT_FM<3>, ISA_MIPS64R2;
}
let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
def DSLL64_32 : FR<0x00, 0x3c, (outs GPR64:$rd), (ins GPR32:$rt),
- "dsll\t$rd, $rt, 32", [], II_DSLL>, GPR_64;
+ "dsll\t$rd, $rt, 32", []>, GPR_64;
let isMoveReg = 1 in {
def SLL64_32 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR32:$rt),
- "sll\t$rd, $rt, 0", [], II_SLL>, GPR_64;
+ "sll\t$rd, $rt, 0", []>, GPR_64;
def SLL64_64 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR64:$rt),
- "sll\t$rd, $rt, 0", [], II_SLL>, GPR_64;
+ "sll\t$rd, $rt, 0", []>, GPR_64;
}
}
@@ -466,16 +466,16 @@ let DecoderNamespace = "CnMips",
class Count1s<string opstr, RegisterOperand RO>:
InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
- [(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr> {
+ [(set RO:$rd, (ctpop RO:$rs))], FrmR, opstr> {
let TwoOperandAliasConstraint = "$rd = $rs";
}
-class ExtsCins<string opstr, InstrItinClass itin, RegisterOperand RO,
+class ExtsCins<string opstr, RegisterOperand RO,
PatFrag PosImm, SDPatternOperator Op = null_frag>:
InstSE<(outs RO:$rt), (ins RO:$rs, uimm5:$pos, uimm5:$lenm1),
!strconcat(opstr, "\t$rt, $rs, $pos, $lenm1"),
[(set RO:$rt, (Op RO:$rs, PosImm:$pos, imm:$lenm1))],
- itin, FrmR, opstr> {
+ FrmR, opstr> {
let TwoOperandAliasConstraint = "$rt = $rs";
}
@@ -484,7 +484,7 @@ class SetCC64_R<string opstr, PatFrag cond_op> :
!strconcat(opstr, "\t$rd, $rs, $rt"),
[(set GPR64Opnd:$rd, (zext (cond_op GPR64Opnd:$rs,
GPR64Opnd:$rt)))],
- II_SEQ_SNE, FrmR, opstr> {
+ FrmR, opstr> {
let TwoOperandAliasConstraint = "$rd = $rs";
}
@@ -493,7 +493,7 @@ class SetCC64_I<string opstr, PatFrag cond_op>:
!strconcat(opstr, "\t$rt, $rs, $imm10"),
[(set GPR64Opnd:$rt, (zext (cond_op GPR64Opnd:$rs,
immSExt10_64:$imm10)))],
- II_SEQI_SNEI, FrmI, opstr> {
+ FrmI, opstr> {
let TwoOperandAliasConstraint = "$rt = $rs";
}
@@ -502,19 +502,19 @@ class CBranchBitNum<string opstr, DAGOperand opnd, PatFrag cond_op,
InstSE<(outs), (ins RO:$rs, ImmOp:$p, opnd:$offset),
!strconcat(opstr, "\t$rs, $p, $offset"),
[(brcond (i32 (cond_op (and RO:$rs, (shl shift, immZExt5_64:$p)), 0)),
- bb:$offset)], II_BBIT, FrmI, opstr> {
+ bb:$offset)], FrmI, opstr> {
let isBranch = 1;
let isTerminator = 1;
let hasDelaySlot = 1;
let Defs = [AT];
}
-class MFC2OP<string asmstr, RegisterOperand RO, InstrItinClass itin> :
+class MFC2OP<string asmstr, RegisterOperand RO> :
InstSE<(outs RO:$rt, uimm16:$imm16), (ins),
- !strconcat(asmstr, "\t$rt, $imm16"), [], itin, FrmFR>;
+ !strconcat(asmstr, "\t$rt, $imm16"), [], FrmFR>;
// Unsigned Byte Add
-def BADDu : ArithLogicR<"baddu", GPR64Opnd, 1, II_BADDU>,
+def BADDu : ArithLogicR<"baddu", GPR64Opnd, 1>,
ADD_FM<0x1c, 0x28>, ASE_CNMIPS {
let Pattern = [(set GPR64Opnd:$rd,
(and (add GPR64Opnd:$rs, GPR64Opnd:$rt), 255))];
@@ -533,29 +533,29 @@ def BBIT132: CBranchBitNum<"bbit132", brtarget, setne, GPR64Opnd, uimm5_64,
0x100000000>, BBIT_FM<0x3e>, ASE_CNMIPS;
// Multiply Doubleword to GPR
-def DMUL : ArithLogicR<"dmul", GPR64Opnd, 1, II_DMUL, mul>,
+def DMUL : ArithLogicR<"dmul", GPR64Opnd, 1, mul>,
ADD_FM<0x1c, 0x03>, ASE_CNMIPS {
let Defs = [HI0, LO0, P0, P1, P2];
}
let AdditionalPredicates = [NotInMicroMips] in {
// Extract a signed bit field /+32
- def EXTS : ExtsCins<"exts", II_EXT, GPR64Opnd, immZExt5>, EXTS_FM<0x3a>,
+ def EXTS : ExtsCins<"exts", GPR64Opnd, immZExt5>, EXTS_FM<0x3a>,
ASE_MIPS64_CNMIPS;
- def EXTS32: ExtsCins<"exts32", II_EXT, GPR64Opnd, immZExt5Plus32>,
+ def EXTS32: ExtsCins<"exts32", GPR64Opnd, immZExt5Plus32>,
EXTS_FM<0x3b>, ASE_MIPS64_CNMIPS;
// Clear and insert a bit field /+32
- def CINS : ExtsCins<"cins", II_INS, GPR64Opnd, immZExt5, MipsCIns>,
+ def CINS : ExtsCins<"cins", GPR64Opnd, immZExt5, MipsCIns>,
EXTS_FM<0x32>, ASE_MIPS64_CNMIPS;
- def CINS32: ExtsCins<"cins32", II_INS, GPR64Opnd, immZExt5Plus32, MipsCIns>,
+ def CINS32: ExtsCins<"cins32", GPR64Opnd, immZExt5Plus32, MipsCIns>,
EXTS_FM<0x33>, ASE_MIPS64_CNMIPS;
let isCodeGenOnly = 1 in {
- def CINS_i32 : ExtsCins<"cins", II_INS, GPR32Opnd, immZExt5, MipsCIns>,
+ def CINS_i32 : ExtsCins<"cins", GPR32Opnd, immZExt5, MipsCIns>,
EXTS_FM<0x32>, ASE_MIPS64_CNMIPS;
def CINS64_32 :InstSE<(outs GPR64Opnd:$rt),
(ins GPR32Opnd:$rs, uimm5:$pos, uimm5:$lenm1),
- "cins\t$rt, $rs, $pos, $lenm1", [], II_INS, FrmR,
+ "cins\t$rt, $rs, $pos, $lenm1", [], FrmR,
"cins">,
EXTS_FM<0x32>, ASE_MIPS64_CNMIPS;
}
@@ -583,27 +583,27 @@ def SNE : SetCC64_R<"sne", setne>, SEQ_FM<0x2b>, ASE_CNMIPS;
def SNEi : SetCC64_I<"snei", setne>, SEQI_FM<0x2f>, ASE_CNMIPS;
// 192-bit x 64-bit Unsigned Multiply and Add
-def V3MULU: ArithLogicR<"v3mulu", GPR64Opnd, 0, II_DMUL>, ADD_FM<0x1c, 0x11>,
+def V3MULU: ArithLogicR<"v3mulu", GPR64Opnd, 0>, ADD_FM<0x1c, 0x11>,
ASE_CNMIPS {
let Defs = [P0, P1, P2];
}
// 64-bit Unsigned Multiply and Add Move
-def VMM0 : ArithLogicR<"vmm0", GPR64Opnd, 0, II_DMUL>, ADD_FM<0x1c, 0x10>,
+def VMM0 : ArithLogicR<"vmm0", GPR64Opnd, 0>, ADD_FM<0x1c, 0x10>,
ASE_CNMIPS {
let Defs = [MPL0, P0, P1, P2];
}
// 64-bit Unsigned Multiply and Add
-def VMULU : ArithLogicR<"vmulu", GPR64Opnd, 0, II_DMUL>, ADD_FM<0x1c, 0x0f>,
+def VMULU : ArithLogicR<"vmulu", GPR64Opnd, 0>, ADD_FM<0x1c, 0x0f>,
ASE_CNMIPS {
let Defs = [MPL1, MPL2, P0, P1, P2];
}
// Move between CPU and coprocessor registers
-def DMFC2_OCTEON : MFC2OP<"dmfc2", GPR64Opnd, II_DMFC2>, MFC2OP_FM<0x12, 1>,
+def DMFC2_OCTEON : MFC2OP<"dmfc2", GPR64Opnd>, MFC2OP_FM<0x12, 1>,
ASE_CNMIPS;
-def DMTC2_OCTEON : MFC2OP<"dmtc2", GPR64Opnd, II_DMTC2>, MFC2OP_FM<0x12, 5>,
+def DMTC2_OCTEON : MFC2OP<"dmtc2", GPR64Opnd>, MFC2OP_FM<0x12, 5>,
ASE_CNMIPS;
}
@@ -614,7 +614,7 @@ let DecoderNamespace = "CnMipsP",
class Saa<string opstr>:
InstSE<(outs), (ins GPR64Opnd:$rt, GPR64Opnd:$rs),
- !strconcat(opstr, "\t$rt, (${rs})"), [], NoItinerary, FrmR, opstr>;
+ !strconcat(opstr, "\t$rt, (${rs})"), [], FrmR, opstr>;
def SAA : Saa<"saa">, SAA_FM<0x18>, ASE_CNMIPSP;
def SAAD : Saa<"saad">, SAA_FM<0x19>, ASE_CNMIPSP;
@@ -629,21 +629,21 @@ def SaadAddr : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rt, mem:$addr),
/// Move between CPU and coprocessor registers
let DecoderNamespace = "Mips64" in {
-def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd, COP0Opnd, II_DMFC0>,
+def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd, COP0Opnd>,
MFC3OP_FM<0x10, 1, 0>, ISA_MIPS3, GPR_64;
-def DMTC0 : MTC3OP<"dmtc0", COP0Opnd, GPR64Opnd, II_DMTC0>,
+def DMTC0 : MTC3OP<"dmtc0", COP0Opnd, GPR64Opnd>,
MFC3OP_FM<0x10, 5, 0>, ISA_MIPS3, GPR_64;
-def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd, COP2Opnd, II_DMFC2>,
+def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd, COP2Opnd>,
MFC3OP_FM<0x12, 1, 0>, ISA_MIPS3, GPR_64;
-def DMTC2 : MTC3OP<"dmtc2", COP2Opnd, GPR64Opnd, II_DMTC2>,
+def DMTC2 : MTC3OP<"dmtc2", COP2Opnd, GPR64Opnd>,
MFC3OP_FM<0x12, 5, 0>, ISA_MIPS3, GPR_64;
}
/// Move between CPU and guest coprocessor registers (Virtualization ASE)
let DecoderNamespace = "Mips64" in {
- def DMFGC0 : MFC3OP<"dmfgc0", GPR64Opnd, COP0Opnd, II_DMFGC0>,
+ def DMFGC0 : MFC3OP<"dmfgc0", GPR64Opnd, COP0Opnd>,
MFC3OP_FM<0x10, 3, 1>, ISA_MIPS64R5, ASE_VIRT;
- def DMTGC0 : MTC3OP<"dmtgc0", COP0Opnd, GPR64Opnd, II_DMTGC0>,
+ def DMTGC0 : MTC3OP<"dmtgc0", COP0Opnd, GPR64Opnd>,
MFC3OP_FM<0x10, 3, 3>, ISA_MIPS64R5, ASE_VIRT;
}
diff --git a/llvm/lib/Target/Mips/Mips64r6InstrInfo.td b/llvm/lib/Target/Mips/Mips64r6InstrInfo.td
index 810c8ffe13514..450d1ae71b75c 100644
--- a/llvm/lib/Target/Mips/Mips64r6InstrInfo.td
+++ b/llvm/lib/Target/Mips/Mips64r6InstrInfo.td
@@ -48,35 +48,33 @@ class CRC32CD_ENC : SPECIAL3_2R_SZ_CRC<3,1>;
//
//===----------------------------------------------------------------------===//
-class AHI_ATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- InstrItinClass itin> {
+class AHI_ATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
dag OutOperandList = (outs GPROpnd:$rs);
dag InOperandList = (ins GPROpnd:$rt, uimm16_altrelaxed:$imm);
string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm");
string Constraints = "$rs = $rt";
- InstrItinClass Itinerary = itin;
}
-class DALIGN_DESC : ALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3, II_DALIGN>;
-class DAHI_DESC : AHI_ATI_DESC_BASE<"dahi", GPR64Opnd, II_DAHI>;
-class DATI_DESC : AHI_ATI_DESC_BASE<"dati", GPR64Opnd, II_DATI>;
-class DAUI_DESC : AUI_DESC_BASE<"daui", GPR64Opnd, II_DAUI>;
-class DBITSWAP_DESC : BITSWAP_DESC_BASE<"dbitswap", GPR64Opnd, II_DBITSWAP>;
-class DCLO_R6_DESC : CLO_R6_DESC_BASE<"dclo", GPR64Opnd, II_DCLO>;
-class DCLZ_R6_DESC : CLZ_R6_DESC_BASE<"dclz", GPR64Opnd, II_DCLZ>;
-class DDIV_DESC : DIVMOD_DESC_BASE<"ddiv", GPR64Opnd, II_DDIV, sdiv>;
-class DDIVU_DESC : DIVMOD_DESC_BASE<"ddivu", GPR64Opnd, II_DDIVU, udiv>;
-class DLSA_R6_DESC : LSA_R6_DESC_BASE<"dlsa", GPR64Opnd, uimm2_plus1, II_DLSA>;
-class DMOD_DESC : DIVMOD_DESC_BASE<"dmod", GPR64Opnd, II_DMOD, srem>;
-class DMODU_DESC : DIVMOD_DESC_BASE<"dmodu", GPR64Opnd, II_DMODU, urem>;
-class DMUH_DESC : MUL_R6_DESC_BASE<"dmuh", GPR64Opnd, II_DMUH, mulhs>;
-class DMUHU_DESC : MUL_R6_DESC_BASE<"dmuhu", GPR64Opnd, II_DMUHU, mulhu>;
-class DMUL_R6_DESC : MUL_R6_DESC_BASE<"dmul", GPR64Opnd, II_DMUL, mul>;
-class DMULU_DESC : MUL_R6_DESC_BASE<"dmulu", GPR64Opnd, II_DMUL>;
-class LDPC_DESC : PCREL_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3, II_LDPC>;
-class LWUPC_DESC : PCREL_DESC_BASE<"lwupc", GPR32Opnd, simm19_lsl2, II_LWUPC>;
-class LLD_R6_DESC : LL_R6_DESC_BASE<"lld", GPR64Opnd, mem_simm9_exp, II_LLD>;
-class SCD_R6_DESC : SC_R6_DESC_BASE<"scd", GPR64Opnd, II_SCD>;
+class DALIGN_DESC : ALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3>;
+class DAHI_DESC : AHI_ATI_DESC_BASE<"dahi", GPR64Opnd>;
+class DATI_DESC : AHI_ATI_DESC_BASE<"dati", GPR64Opnd>;
+class DAUI_DESC : AUI_DESC_BASE<"daui", GPR64Opnd>;
+class DBITSWAP_DESC : BITSWAP_DESC_BASE<"dbitswap", GPR64Opnd>;
+class DCLO_R6_DESC : CLO_R6_DESC_BASE<"dclo", GPR64Opnd>;
+class DCLZ_R6_DESC : CLZ_R6_DESC_BASE<"dclz", GPR64Opnd>;
+class DDIV_DESC : DIVMOD_DESC_BASE<"ddiv", GPR64Opnd, sdiv>;
+class DDIVU_DESC : DIVMOD_DESC_BASE<"ddivu", GPR64Opnd, udiv>;
+class DLSA_R6_DESC : LSA_R6_DESC_BASE<"dlsa", GPR64Opnd, uimm2_plus1>;
+class DMOD_DESC : DIVMOD_DESC_BASE<"dmod", GPR64Opnd, srem>;
+class DMODU_DESC : DIVMOD_DESC_BASE<"dmodu", GPR64Opnd, urem>;
+class DMUH_DESC : MUL_R6_DESC_BASE<"dmuh", GPR64Opnd, mulhs>;
+class DMUHU_DESC : MUL_R6_DESC_BASE<"dmuhu", GPR64Opnd, mulhu>;
+class DMUL_R6_DESC : MUL_R6_DESC_BASE<"dmul", GPR64Opnd, mul>;
+class DMULU_DESC : MUL_R6_DESC_BASE<"dmulu", GPR64Opnd>;
+class LDPC_DESC : PCREL_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3>;
+class LWUPC_DESC : PCREL_DESC_BASE<"lwupc", GPR32Opnd, simm19_lsl2>;
+class LLD_R6_DESC : LL_R6_DESC_BASE<"lld", GPR64Opnd, mem_simm9_exp>;
+class SCD_R6_DESC : SC_R6_DESC_BASE<"scd", GPR64Opnd>;
class SELEQZ64_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR64Opnd>;
class SELNEZ64_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR64Opnd>;
@@ -94,20 +92,20 @@ class BEQZC64_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR64Opnd>;
class BNEZC64_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR64Opnd>;
class JIALC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16,
- GPR64Opnd, II_JIALC> {
+ GPR64Opnd> {
bit isCall = 1;
list<Register> Defs = [RA];
}
-class JIC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR64Opnd,
- II_JIC> {
+class JIC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16,
+ GPR64Opnd> {
bit isBarrier = 1;
bit isTerminator = 1;
list<Register> Defs = [AT];
}
-class LL64_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd, mem_simm9_exp, II_LL>;
-class SC64_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd, II_SC>;
+class LL64_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd, mem_simm9_exp>;
+class SC64_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd>;
class JR_HB64_R6_DESC : JR_HB_DESC_BASE<"jr.hb", GPR64Opnd> {
bit isBranch = 1;
@@ -116,11 +114,10 @@ class JR_HB64_R6_DESC : JR_HB_DESC_BASE<"jr.hb", GPR64Opnd> {
bit isTerminator=1;
bit isBarrier=1;
bit isCTI = 1;
- InstrItinClass Itinerary = II_JR_HB;
}
-class CRC32D_DESC : CRC_DESC_BASE<"crc32d", GPR32Opnd, II_CRC32D>;
-class CRC32CD_DESC : CRC_DESC_BASE<"crc32cd", GPR32Opnd, II_CRC32CD>;
+class CRC32D_DESC : CRC_DESC_BASE<"crc32d", GPR32Opnd>;
+class CRC32CD_DESC : CRC_DESC_BASE<"crc32cd", GPR32Opnd>;
//===----------------------------------------------------------------------===//
//
diff --git a/llvm/lib/Target/Mips/MipsCondMov.td b/llvm/lib/Target/Mips/MipsCondMov.td
index e9e09a188bf5b..b02883117901e 100644
--- a/llvm/lib/Target/Mips/MipsCondMov.td
+++ b/llvm/lib/Target/Mips/MipsCondMov.td
@@ -15,39 +15,37 @@
// MipsISelLowering::EmitInstrWithCustomInserter if target does not have
// conditional move instructions.
// cond:int, data:int
-class CMov_I_I_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC,
- InstrItinClass Itin> :
+class CMov_I_I_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC> :
InstSE<(outs DRC:$rd), (ins DRC:$rs, CRC:$rt, DRC:$F),
- !strconcat(opstr, "\t$rd, $rs, $rt"), [], Itin, FrmFR, opstr> {
+ !strconcat(opstr, "\t$rd, $rs, $rt"), [], FrmFR, opstr> {
let Constraints = "$F = $rd";
}
// cond:int, data:float
-class CMov_I_F_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC,
- InstrItinClass Itin> :
+class CMov_I_F_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC> :
InstSE<(outs DRC:$fd), (ins DRC:$fs, CRC:$rt, DRC:$F),
- !strconcat(opstr, "\t$fd, $fs, $rt"), [], Itin, FrmFR, opstr>,
+ !strconcat(opstr, "\t$fd, $fs, $rt"), [], FrmFR, opstr>,
HARDFLOAT {
let Constraints = "$F = $fd";
}
// cond:float, data:int
-class CMov_F_I_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
+class CMov_F_I_FT<string opstr, RegisterOperand RC,
SDPatternOperator OpNode = null_frag> :
InstSE<(outs RC:$rd), (ins RC:$rs, FCCRegsOpnd:$fcc, RC:$F),
!strconcat(opstr, "\t$rd, $rs, $fcc"),
[(set RC:$rd, (OpNode RC:$rs, FCCRegsOpnd:$fcc, RC:$F))],
- Itin, FrmFR, opstr>, HARDFLOAT {
+ FrmFR, opstr>, HARDFLOAT {
let Constraints = "$F = $rd";
}
// cond:float, data:float
-class CMov_F_F_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
+class CMov_F_F_FT<string opstr, RegisterOperand RC,
SDPatternOperator OpNode = null_frag> :
InstSE<(outs RC:$fd), (ins RC:$fs, FCCRegsOpnd:$fcc, RC:$F),
!strconcat(opstr, "\t$fd, $fs, $fcc"),
[(set RC:$fd, (OpNode RC:$fs, FCCRegsOpnd:$fcc, RC:$F))],
- Itin, FrmFR, opstr>, HARDFLOAT {
+ FrmFR, opstr>, HARDFLOAT {
let Constraints = "$F = $fd";
}
@@ -104,94 +102,94 @@ multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst,
// Instantiation of instructions.
let AdditionalPredicates = [NotInMicroMips] in {
- def MOVZ_I_I : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd, II_MOVZ>,
+ def MOVZ_I_I : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd>,
ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6;
let isCodeGenOnly = 1 in {
- def MOVZ_I_I64 : CMov_I_I_FT<"movz", GPR32Opnd, GPR64Opnd, II_MOVZ>,
+ def MOVZ_I_I64 : CMov_I_I_FT<"movz", GPR32Opnd, GPR64Opnd>,
ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
- def MOVZ_I64_I : CMov_I_I_FT<"movz", GPR64Opnd, GPR32Opnd, II_MOVZ>,
+ def MOVZ_I64_I : CMov_I_I_FT<"movz", GPR64Opnd, GPR32Opnd>,
ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
- def MOVZ_I64_I64 : CMov_I_I_FT<"movz", GPR64Opnd, GPR64Opnd, II_MOVZ>,
+ def MOVZ_I64_I64 : CMov_I_I_FT<"movz", GPR64Opnd, GPR64Opnd>,
ADD_FM<0, 0xa>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
}
- def MOVN_I_I : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd, II_MOVN>,
+ def MOVN_I_I : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd>,
ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6;
let isCodeGenOnly = 1 in {
- def MOVN_I_I64 : CMov_I_I_FT<"movn", GPR32Opnd, GPR64Opnd, II_MOVN>,
+ def MOVN_I_I64 : CMov_I_I_FT<"movn", GPR32Opnd, GPR64Opnd>,
ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
- def MOVN_I64_I : CMov_I_I_FT<"movn", GPR64Opnd, GPR32Opnd, II_MOVN>,
+ def MOVN_I64_I : CMov_I_I_FT<"movn", GPR64Opnd, GPR32Opnd>,
ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
- def MOVN_I64_I64 : CMov_I_I_FT<"movn", GPR64Opnd, GPR64Opnd, II_MOVN>,
+ def MOVN_I64_I64 : CMov_I_I_FT<"movn", GPR64Opnd, GPR64Opnd>,
ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
}
- def MOVZ_I_S : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, II_MOVZ_S>,
+ def MOVZ_I_S : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd>,
CMov_I_F_FM<18, 16>, INSN_MIPS4_32_NOT_32R6_64R6;
let isCodeGenOnly = 1 in
- def MOVZ_I64_S : CMov_I_F_FT<"movz.s", GPR64Opnd, FGR32Opnd, II_MOVZ_S>,
+ def MOVZ_I64_S : CMov_I_F_FT<"movz.s", GPR64Opnd, FGR32Opnd>,
CMov_I_F_FM<18, 16>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
- def MOVN_I_S : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, II_MOVN_S>,
+ def MOVN_I_S : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd>,
CMov_I_F_FM<19, 16>, INSN_MIPS4_32_NOT_32R6_64R6;
let isCodeGenOnly = 1 in
- def MOVN_I64_S : CMov_I_F_FT<"movn.s", GPR64Opnd, FGR32Opnd, II_MOVN_S>,
+ def MOVN_I64_S : CMov_I_F_FT<"movn.s", GPR64Opnd, FGR32Opnd>,
CMov_I_F_FM<19, 16>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
- def MOVZ_I_D32 : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd,
- II_MOVZ_D>, CMov_I_F_FM<18, 17>,
+ def MOVZ_I_D32 : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd>,
+ CMov_I_F_FM<18, 17>,
INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
- def MOVN_I_D32 : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd,
- II_MOVN_D>, CMov_I_F_FM<19, 17>,
+ def MOVN_I_D32 : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd>,
+ CMov_I_F_FM<19, 17>,
INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
let DecoderNamespace = "MipsFP64" in {
- def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", GPR32Opnd, FGR64Opnd, II_MOVZ_D>,
+ def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", GPR32Opnd, FGR64Opnd>,
CMov_I_F_FM<18, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
- def MOVN_I_D64 : CMov_I_F_FT<"movn.d", GPR32Opnd, FGR64Opnd, II_MOVN_D>,
+ def MOVN_I_D64 : CMov_I_F_FT<"movn.d", GPR32Opnd, FGR64Opnd>,
CMov_I_F_FM<19, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
let isCodeGenOnly = 1 in {
- def MOVZ_I64_D64 : CMov_I_F_FT<"movz.d", GPR64Opnd, FGR64Opnd, II_MOVZ_D>,
+ def MOVZ_I64_D64 : CMov_I_F_FT<"movz.d", GPR64Opnd, FGR64Opnd>,
CMov_I_F_FM<18, 17>,
INSN_MIPS4_32_NOT_32R6_64R6, GPR_64, FGR_64;
- def MOVN_I64_D64 : CMov_I_F_FT<"movn.d", GPR64Opnd, FGR64Opnd, II_MOVN_D>,
+ def MOVN_I64_D64 : CMov_I_F_FT<"movn.d", GPR64Opnd, FGR64Opnd>,
CMov_I_F_FM<19, 17>,
INSN_MIPS4_32_NOT_32R6_64R6, GPR_64, FGR_64;
}
}
- def MOVT_I : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT, MipsCMovFP_T>,
+ def MOVT_I : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, MipsCMovFP_T>,
CMov_F_I_FM<1>, INSN_MIPS4_32_NOT_32R6_64R6;
let isCodeGenOnly = 1 in
- def MOVT_I64 : CMov_F_I_FT<"movt", GPR64Opnd, II_MOVT, MipsCMovFP_T>,
+ def MOVT_I64 : CMov_F_I_FT<"movt", GPR64Opnd, MipsCMovFP_T>,
CMov_F_I_FM<1>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
- def MOVF_I : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF, MipsCMovFP_F>,
+ def MOVF_I : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, MipsCMovFP_F>,
CMov_F_I_FM<0>, INSN_MIPS4_32_NOT_32R6_64R6;
let isCodeGenOnly = 1 in
- def MOVF_I64 : CMov_F_I_FT<"movf", GPR64Opnd, II_MOVF, MipsCMovFP_F>,
+ def MOVF_I64 : CMov_F_I_FT<"movf", GPR64Opnd, MipsCMovFP_F>,
CMov_F_I_FM<0>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
- def MOVT_S : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S, MipsCMovFP_T>,
+ def MOVT_S : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, MipsCMovFP_T>,
CMov_F_F_FM<16, 1>, INSN_MIPS4_32_NOT_32R6_64R6;
- def MOVF_S : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S, MipsCMovFP_F>,
+ def MOVF_S : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, MipsCMovFP_F>,
CMov_F_F_FM<16, 0>, INSN_MIPS4_32_NOT_32R6_64R6;
- def MOVT_D32 : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D,
- MipsCMovFP_T>, CMov_F_F_FM<17, 1>,
+ def MOVT_D32 : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, MipsCMovFP_T>,
+ CMov_F_F_FM<17, 1>,
INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
- def MOVF_D32 : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D,
- MipsCMovFP_F>, CMov_F_F_FM<17, 0>,
+ def MOVF_D32 : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, MipsCMovFP_F>,
+ CMov_F_F_FM<17, 0>,
INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
let DecoderNamespace = "MipsFP64" in {
- def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64Opnd, II_MOVT_D, MipsCMovFP_T>,
+ def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64Opnd, MipsCMovFP_T>,
CMov_F_F_FM<17, 1>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
- def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64Opnd, II_MOVF_D, MipsCMovFP_F>,
+ def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64Opnd, MipsCMovFP_F>,
CMov_F_F_FM<17, 0>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
}
diff --git a/llvm/lib/Target/Mips/MipsDSPInstrFormats.td b/llvm/lib/Target/Mips/MipsDSPInstrFormats.td
index abb6aea507104..b6eceaae644c2 100644
--- a/llvm/lib/Target/Mips/MipsDSPInstrFormats.td
+++ b/llvm/lib/Target/Mips/MipsDSPInstrFormats.td
@@ -44,15 +44,14 @@ def SPECIAL3_OPCODE : Field6<0b011111>;
def REGIMM_OPCODE : Field6<0b000001>;
class DSPInst<string opstr = "">
- : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
+ : MipsInst<(outs), (ins), "", [], FrmOther> {
let ASEPredicate = [HasDSP];
string BaseOpcode = opstr;
string Arch = "dsp";
}
-class PseudoDSP<dag outs, dag ins, list<dag> pattern,
- InstrItinClass itin = IIPseudo>
- : MipsPseudo<outs, ins, pattern, itin> {
+class PseudoDSP<dag outs, dag ins, list<dag> pattern>
+ : MipsPseudo<outs, ins, pattern> {
let ASEPredicate = [HasDSP];
}
diff --git a/llvm/lib/Target/Mips/MipsDSPInstrInfo.td b/llvm/lib/Target/Mips/MipsDSPInstrInfo.td
index bad7d504271af..9d7f12fbe01ec 100644
--- a/llvm/lib/Target/Mips/MipsDSPInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsDSPInstrInfo.td
@@ -274,153 +274,137 @@ class PREPEND_ENC : APPEND_FMT<0b00001>;
// Instruction desc.
class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
- InstrItinClass itin, RegisterOperand ROD,
+ RegisterOperand ROD,
RegisterOperand ROS, RegisterOperand ROT = ROS> {
dag OutOperandList = (outs ROD:$rd);
dag InOperandList = (ins ROS:$rs, ROT:$rt);
string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
- InstrItinClass Itinerary = itin;
string BaseOpcode = instr_asm;
}
class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
- InstrItinClass itin, RegisterOperand ROD,
+ RegisterOperand ROD,
RegisterOperand ROS = ROD> {
dag OutOperandList = (outs ROD:$rd);
dag InOperandList = (ins ROS:$rs);
string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs))];
- InstrItinClass Itinerary = itin;
string BaseOpcode = instr_asm;
}
class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
- InstrItinClass itin, RegisterOperand ROS,
+ RegisterOperand ROS,
RegisterOperand ROT = ROS> {
dag OutOperandList = (outs);
dag InOperandList = (ins ROS:$rs, ROT:$rt);
string AsmString = !strconcat(instr_asm, "\t$rs, $rt");
list<dag> Pattern = [(OpNode ROS:$rs, ROT:$rt)];
- InstrItinClass Itinerary = itin;
string BaseOpcode = instr_asm;
}
class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
- InstrItinClass itin, RegisterOperand ROD,
+ RegisterOperand ROD,
RegisterOperand ROS, RegisterOperand ROT = ROS> {
dag OutOperandList = (outs ROD:$rd);
dag InOperandList = (ins ROS:$rs, ROT:$rt);
string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
- InstrItinClass Itinerary = itin;
string BaseOpcode = instr_asm;
}
class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
- InstrItinClass itin, RegisterOperand ROT,
+ RegisterOperand ROT,
RegisterOperand ROS = ROT> {
dag OutOperandList = (outs ROT:$rt);
dag InOperandList = (ins ROS:$rs, uimm5:$sa, ROS:$src);
string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
list<dag> Pattern = [(set ROT:$rt, (OpNode ROS:$src, ROS:$rs, timmZExt5:$sa))];
- InstrItinClass Itinerary = itin;
string Constraints = "$src = $rt";
string BaseOpcode = instr_asm;
}
class ABSQ_S_PH_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
- InstrItinClass itin, RegisterOperand ROD,
+ RegisterOperand ROD,
RegisterOperand ROT = ROD> {
dag OutOperandList = (outs ROD:$rd);
dag InOperandList = (ins ROT:$rt);
string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
list<dag> Pattern = [(set ROD:$rd, (OpNode ROT:$rt))];
- InstrItinClass Itinerary = itin;
string BaseOpcode = instr_asm;
}
class REPL_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
- Operand ImmOp, ImmLeaf immPat, InstrItinClass itin,
+ Operand ImmOp, ImmLeaf immPat,
RegisterOperand RO> {
dag OutOperandList = (outs RO:$rd);
dag InOperandList = (ins ImmOp:$imm);
string AsmString = !strconcat(instr_asm, "\t$rd, $imm");
list<dag> Pattern = [(set RO:$rd, (OpNode immPat:$imm))];
- InstrItinClass Itinerary = itin;
string BaseOpcode = instr_asm;
}
class SHLL_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
- InstrItinClass itin, RegisterOperand RO> {
+ RegisterOperand RO> {
dag OutOperandList = (outs RO:$rd);
dag InOperandList = (ins RO:$rt, GPR32Opnd:$rs_sa);
string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs_sa))];
- InstrItinClass Itinerary = itin;
string BaseOpcode = instr_asm;
}
class SHLL_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
- SDPatternOperator ImmPat, InstrItinClass itin,
+ SDPatternOperator ImmPat,
RegisterOperand RO, Operand ImmOpnd> {
dag OutOperandList = (outs RO:$rd);
dag InOperandList = (ins RO:$rt, ImmOpnd:$rs_sa);
string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs_sa");
list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, ImmPat:$rs_sa))];
- InstrItinClass Itinerary = itin;
bit hasSideEffects = 1;
string BaseOpcode = instr_asm;
}
-class LX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
- InstrItinClass itin> {
+class LX_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
dag OutOperandList = (outs GPR32Opnd:$rd);
dag InOperandList = (ins PtrRC:$base, PtrRC:$index);
string AsmString = !strconcat(instr_asm, "\t$rd, ${index}(${base})");
list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode iPTR:$base, iPTR:$index))];
- InstrItinClass Itinerary = itin;
bit mayLoad = 1;
string BaseOpcode = instr_asm;
}
class ADDUH_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
- InstrItinClass itin, RegisterOperand ROD,
+ RegisterOperand ROD,
RegisterOperand ROS = ROD, RegisterOperand ROT = ROD> {
dag OutOperandList = (outs ROD:$rd);
dag InOperandList = (ins ROS:$rs, ROT:$rt);
string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
- InstrItinClass Itinerary = itin;
string BaseOpcode = instr_asm;
}
class APPEND_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
- Operand ImmOp, SDPatternOperator Imm,
- InstrItinClass itin> {
+ Operand ImmOp, SDPatternOperator Imm> {
dag OutOperandList = (outs GPR32Opnd:$rt);
dag InOperandList = (ins GPR32Opnd:$rs, ImmOp:$sa, GPR32Opnd:$src);
string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
list<dag> Pattern = [(set GPR32Opnd:$rt,
(OpNode GPR32Opnd:$src, GPR32Opnd:$rs, Imm:$sa))];
- InstrItinClass Itinerary = itin;
string Constraints = "$src = $rt";
string BaseOpcode = instr_asm;
}
-class EXTR_W_TY1_R2_DESC_BASE<string instr_asm, InstrItinClass itin> {
+class EXTR_W_TY1_R2_DESC_BASE<string instr_asm> {
dag OutOperandList = (outs GPR32Opnd:$rt);
dag InOperandList = (ins ACC64DSPOpnd:$ac, GPR32Opnd:$shift_rs);
string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
- InstrItinClass Itinerary = itin;
string BaseOpcode = instr_asm;
}
-class EXTR_W_TY1_R1_DESC_BASE<string instr_asm, InstrItinClass itin> {
+class EXTR_W_TY1_R1_DESC_BASE<string instr_asm> {
dag OutOperandList = (outs GPR32Opnd:$rt);
dag InOperandList = (ins ACC64DSPOpnd:$ac, uimm5:$shift_rs);
string AsmString = !strconcat(instr_asm, "\t$rt, $ac, $shift_rs");
- InstrItinClass Itinerary = itin;
string BaseOpcode = instr_asm;
}
@@ -454,23 +438,19 @@ class MTHLIP_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
string BaseOpcode = instr_asm;
}
-class RDDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
- InstrItinClass itin> {
+class RDDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
dag OutOperandList = (outs GPR32Opnd:$rd);
dag InOperandList = (ins uimm10:$mask);
string AsmString = !strconcat(instr_asm, "\t$rd, $mask");
list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode timmZExt10:$mask))];
- InstrItinClass Itinerary = itin;
string BaseOpcode = instr_asm;
}
-class WRDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
- InstrItinClass itin> {
+class WRDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
dag OutOperandList = (outs);
dag InOperandList = (ins GPR32Opnd:$rs, uimm10:$mask);
string AsmString = !strconcat(instr_asm, "\t$rs, $mask");
list<dag> Pattern = [(OpNode GPR32Opnd:$rs, timmZExt10:$mask)];
- InstrItinClass Itinerary = itin;
string BaseOpcode = instr_asm;
}
@@ -484,46 +464,38 @@ class DPA_DESC_BASE<string instr_asm, SDPatternOperator OpNode, ValueType VT> {
string BaseOpcode = instr_asm;
}
-class MULT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
- InstrItinClass itin> {
+class MULT_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
dag OutOperandList = (outs ACC64DSPOpnd:$ac);
dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt);
string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
list<dag> Pattern = [(set ACC64DSPOpnd:$ac, (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt))];
- InstrItinClass Itinerary = itin;
bit isCommutable = 1;
string BaseOpcode = instr_asm;
}
-class MADD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
- InstrItinClass itin> {
+class MADD_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
dag OutOperandList = (outs ACC64DSPOpnd:$ac);
dag InOperandList = (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin);
string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
list<dag> Pattern = [(set ACC64DSPOpnd:$ac,
(OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))];
- InstrItinClass Itinerary = itin;
string Constraints = "$acin = $ac";
string BaseOpcode = instr_asm;
}
-class MFHI_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode,
- InstrItinClass itin> {
+class MFHI_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode> {
dag OutOperandList = (outs GPR32Opnd:$rd);
dag InOperandList = (ins RO:$ac);
string AsmString = !strconcat(instr_asm, "\t$rd, $ac");
list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode RO:$ac))];
- InstrItinClass Itinerary = itin;
string BaseOpcode = instr_asm;
bit isMoveReg = 1;
}
-class MTHI_DESC_BASE<string instr_asm, RegisterOperand RO,
- InstrItinClass itin> {
+class MTHI_DESC_BASE<string instr_asm, RegisterOperand RO> {
dag OutOperandList = (outs RO:$ac);
dag InOperandList = (ins GPR32Opnd:$rs);
string AsmString = !strconcat(instr_asm, "\t$rs, $ac");
- InstrItinClass Itinerary = itin;
string BaseOpcode = instr_asm;
bit isMoveReg = 1;
}
@@ -534,25 +506,21 @@ class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode> :
bit usesCustomInserter = 1;
}
-class BPOSGE32_DESC_BASE<string instr_asm, DAGOperand opnd,
- InstrItinClass itin> {
+class BPOSGE32_DESC_BASE<string instr_asm, DAGOperand opnd> {
dag OutOperandList = (outs);
dag InOperandList = (ins opnd:$offset);
string AsmString = !strconcat(instr_asm, "\t$offset");
- InstrItinClass Itinerary = itin;
bit isBranch = 1;
bit isTerminator = 1;
bit hasDelaySlot = 1;
string BaseOpcode = instr_asm;
}
-class INSV_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
- InstrItinClass itin> {
+class INSV_DESC_BASE<string instr_asm, SDPatternOperator OpNode> {
dag OutOperandList = (outs GPR32Opnd:$rt);
dag InOperandList = (ins GPR32Opnd:$src, GPR32Opnd:$rs);
string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
list<dag> Pattern = [(set GPR32Opnd:$rt, (OpNode GPR32Opnd:$src, GPR32Opnd:$rs))];
- InstrItinClass Itinerary = itin;
string Constraints = "$src = $rt";
string BaseOpcode = instr_asm;
}
@@ -562,214 +530,214 @@ class INSV_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
//===----------------------------------------------------------------------===//
// Addition/subtraction
-class ADDU_QB_DESC : ADDU_QB_DESC_BASE<"addu.qb", null_frag, NoItinerary,
+class ADDU_QB_DESC : ADDU_QB_DESC_BASE<"addu.qb", null_frag,
DSPROpnd, DSPROpnd>, IsCommutable,
Defs<[DSPOutFlag20]>;
class ADDU_S_QB_DESC : ADDU_QB_DESC_BASE<"addu_s.qb", int_mips_addu_s_qb,
- NoItinerary, DSPROpnd, DSPROpnd>,
+ DSPROpnd, DSPROpnd>,
IsCommutable, Defs<[DSPOutFlag20]>;
-class SUBU_QB_DESC : ADDU_QB_DESC_BASE<"subu.qb", null_frag, NoItinerary,
+class SUBU_QB_DESC : ADDU_QB_DESC_BASE<"subu.qb", null_frag,
DSPROpnd, DSPROpnd>,
Defs<[DSPOutFlag20]>;
class SUBU_S_QB_DESC : ADDU_QB_DESC_BASE<"subu_s.qb", int_mips_subu_s_qb,
- NoItinerary, DSPROpnd, DSPROpnd>,
+ DSPROpnd, DSPROpnd>,
Defs<[DSPOutFlag20]>;
-class ADDQ_PH_DESC : ADDU_QB_DESC_BASE<"addq.ph", null_frag, NoItinerary,
+class ADDQ_PH_DESC : ADDU_QB_DESC_BASE<"addq.ph", null_frag,
DSPROpnd, DSPROpnd>, IsCommutable,
Defs<[DSPOutFlag20]>;
class ADDQ_S_PH_DESC : ADDU_QB_DESC_BASE<"addq_s.ph", int_mips_addq_s_ph,
- NoItinerary, DSPROpnd, DSPROpnd>,
+ DSPROpnd, DSPROpnd>,
IsCommutable, Defs<[DSPOutFlag20]>;
-class SUBQ_PH_DESC : ADDU_QB_DESC_BASE<"subq.ph", null_frag, NoItinerary,
+class SUBQ_PH_DESC : ADDU_QB_DESC_BASE<"subq.ph", null_frag,
DSPROpnd, DSPROpnd>,
Defs<[DSPOutFlag20]>;
class SUBQ_S_PH_DESC : ADDU_QB_DESC_BASE<"subq_s.ph", int_mips_subq_s_ph,
- NoItinerary, DSPROpnd, DSPROpnd>,
+ DSPROpnd, DSPROpnd>,
Defs<[DSPOutFlag20]>;
class ADDQ_S_W_DESC : ADDU_QB_DESC_BASE<"addq_s.w", int_mips_addq_s_w,
- NoItinerary, GPR32Opnd, GPR32Opnd>,
+ GPR32Opnd, GPR32Opnd>,
IsCommutable, Defs<[DSPOutFlag20]>;
class SUBQ_S_W_DESC : ADDU_QB_DESC_BASE<"subq_s.w", int_mips_subq_s_w,
- NoItinerary, GPR32Opnd, GPR32Opnd>,
+ GPR32Opnd, GPR32Opnd>,
Defs<[DSPOutFlag20]>;
-class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", null_frag, NoItinerary,
+class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", null_frag,
GPR32Opnd, GPR32Opnd>, IsCommutable,
Defs<[DSPCarry]>;
-class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", null_frag, NoItinerary,
+class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", null_frag,
GPR32Opnd, GPR32Opnd>,
IsCommutable, Uses<[DSPCarry]>, Defs<[DSPOutFlag20]>;
-class MODSUB_DESC : ADDU_QB_DESC_BASE<"modsub", int_mips_modsub, NoItinerary,
+class MODSUB_DESC : ADDU_QB_DESC_BASE<"modsub", int_mips_modsub,
GPR32Opnd, GPR32Opnd>;
class RADDU_W_QB_DESC : RADDU_W_QB_DESC_BASE<"raddu.w.qb", int_mips_raddu_w_qb,
- NoItinerary, GPR32Opnd, DSPROpnd>;
+ GPR32Opnd, DSPROpnd>;
// Absolute value
class ABSQ_S_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.ph", int_mips_absq_s_ph,
- NoItinerary, DSPROpnd>,
+ DSPROpnd>,
Defs<[DSPOutFlag20]>;
class ABSQ_S_W_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.w", int_mips_absq_s_w,
- NoItinerary, GPR32Opnd>,
+ GPR32Opnd>,
Defs<[DSPOutFlag20]>;
// Precision reduce/expand
class PRECRQ_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.qb.ph",
int_mips_precrq_qb_ph,
- NoItinerary, DSPROpnd, DSPROpnd>;
+ DSPROpnd, DSPROpnd>;
class PRECRQ_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq.ph.w",
int_mips_precrq_ph_w,
- NoItinerary, DSPROpnd, GPR32Opnd>;
+ DSPROpnd, GPR32Opnd>;
class PRECRQ_RS_PH_W_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrq_rs.ph.w",
int_mips_precrq_rs_ph_w,
- NoItinerary, DSPROpnd,
+ DSPROpnd,
GPR32Opnd>,
Defs<[DSPOutFlag22]>;
class PRECRQU_S_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precrqu_s.qb.ph",
int_mips_precrqu_s_qb_ph,
- NoItinerary, DSPROpnd,
+ DSPROpnd,
DSPROpnd>,
Defs<[DSPOutFlag22]>;
class PRECEQ_W_PHL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phl",
int_mips_preceq_w_phl,
- NoItinerary, GPR32Opnd, DSPROpnd>;
+ GPR32Opnd, DSPROpnd>;
class PRECEQ_W_PHR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceq.w.phr",
int_mips_preceq_w_phr,
- NoItinerary, GPR32Opnd, DSPROpnd>;
+ GPR32Opnd, DSPROpnd>;
class PRECEQU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbl",
int_mips_precequ_ph_qbl,
- NoItinerary, DSPROpnd>;
+ DSPROpnd>;
class PRECEQU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbr",
int_mips_precequ_ph_qbr,
- NoItinerary, DSPROpnd>;
+ DSPROpnd>;
class PRECEQU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbla",
int_mips_precequ_ph_qbla,
- NoItinerary, DSPROpnd>;
+ DSPROpnd>;
class PRECEQU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"precequ.ph.qbra",
int_mips_precequ_ph_qbra,
- NoItinerary, DSPROpnd>;
+ DSPROpnd>;
class PRECEU_PH_QBL_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbl",
int_mips_preceu_ph_qbl,
- NoItinerary, DSPROpnd>;
+ DSPROpnd>;
class PRECEU_PH_QBR_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbr",
int_mips_preceu_ph_qbr,
- NoItinerary, DSPROpnd>;
+ DSPROpnd>;
class PRECEU_PH_QBLA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbla",
int_mips_preceu_ph_qbla,
- NoItinerary, DSPROpnd>;
+ DSPROpnd>;
class PRECEU_PH_QBRA_DESC : ABSQ_S_PH_R2_DESC_BASE<"preceu.ph.qbra",
int_mips_preceu_ph_qbra,
- NoItinerary, DSPROpnd>;
+ DSPROpnd>;
// Shift
class SHLL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shll.qb", null_frag, immZExt3,
- NoItinerary, DSPROpnd, uimm3>,
+ DSPROpnd, uimm3>,
Defs<[DSPOutFlag22]>;
class SHLLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shllv.qb", int_mips_shll_qb,
- NoItinerary, DSPROpnd>,
+ DSPROpnd>,
Defs<[DSPOutFlag22]>;
class SHRL_QB_DESC : SHLL_QB_R2_DESC_BASE<"shrl.qb", null_frag, immZExt3,
- NoItinerary, DSPROpnd, uimm3>;
+ DSPROpnd, uimm3>;
class SHRLV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.qb", int_mips_shrl_qb,
- NoItinerary, DSPROpnd>;
+ DSPROpnd>;
class SHLL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll.ph", null_frag, immZExt4,
- NoItinerary, DSPROpnd, uimm4>,
+ DSPROpnd, uimm4>,
Defs<[DSPOutFlag22]>;
class SHLLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv.ph", int_mips_shll_ph,
- NoItinerary, DSPROpnd>,
+ DSPROpnd>,
Defs<[DSPOutFlag22]>;
class SHLL_S_PH_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.ph", int_mips_shll_s_ph,
- immZExt4, NoItinerary, DSPROpnd,
+ immZExt4, DSPROpnd,
uimm4>,
Defs<[DSPOutFlag22]>;
class SHLLV_S_PH_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.ph", int_mips_shll_s_ph,
- NoItinerary, DSPROpnd>,
+ DSPROpnd>,
Defs<[DSPOutFlag22]>;
class SHRA_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra.ph", null_frag, immZExt4,
- NoItinerary, DSPROpnd, uimm4>;
+ DSPROpnd, uimm4>;
class SHRAV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav.ph", int_mips_shra_ph,
- NoItinerary, DSPROpnd>;
+ DSPROpnd>;
class SHRA_R_PH_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.ph", int_mips_shra_r_ph,
- immZExt4, NoItinerary, DSPROpnd,
+ immZExt4, DSPROpnd,
uimm4>;
class SHRAV_R_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.ph", int_mips_shra_r_ph,
- NoItinerary, DSPROpnd>;
+ DSPROpnd>;
class SHLL_S_W_DESC : SHLL_QB_R2_DESC_BASE<"shll_s.w", int_mips_shll_s_w,
- immZExt5, NoItinerary, GPR32Opnd,
+ immZExt5, GPR32Opnd,
uimm5>,
Defs<[DSPOutFlag22]>;
class SHLLV_S_W_DESC : SHLL_QB_R3_DESC_BASE<"shllv_s.w", int_mips_shll_s_w,
- NoItinerary, GPR32Opnd>,
+ GPR32Opnd>,
Defs<[DSPOutFlag22]>;
class SHRA_R_W_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.w", int_mips_shra_r_w,
- immZExt5, NoItinerary, GPR32Opnd,
+ immZExt5, GPR32Opnd,
uimm5>;
class SHRAV_R_W_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.w", int_mips_shra_r_w,
- NoItinerary, GPR32Opnd>;
+ GPR32Opnd>;
// Multiplication
class MULEU_S_PH_QBL_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbl",
int_mips_muleu_s_ph_qbl,
- NoItinerary, DSPROpnd, DSPROpnd>,
+ DSPROpnd, DSPROpnd>,
Defs<[DSPOutFlag21]>;
class MULEU_S_PH_QBR_DESC : ADDU_QB_DESC_BASE<"muleu_s.ph.qbr",
int_mips_muleu_s_ph_qbr,
- NoItinerary, DSPROpnd, DSPROpnd>,
+ DSPROpnd, DSPROpnd>,
Defs<[DSPOutFlag21]>;
class MULEQ_S_W_PHL_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phl",
int_mips_muleq_s_w_phl,
- NoItinerary, GPR32Opnd, DSPROpnd>,
+ GPR32Opnd, DSPROpnd>,
IsCommutable, Defs<[DSPOutFlag21]>;
class MULEQ_S_W_PHR_DESC : ADDU_QB_DESC_BASE<"muleq_s.w.phr",
int_mips_muleq_s_w_phr,
- NoItinerary, GPR32Opnd, DSPROpnd>,
+ GPR32Opnd, DSPROpnd>,
IsCommutable, Defs<[DSPOutFlag21]>;
class MULQ_RS_PH_DESC : ADDU_QB_DESC_BASE<"mulq_rs.ph", int_mips_mulq_rs_ph,
- NoItinerary, DSPROpnd, DSPROpnd>,
+ DSPROpnd, DSPROpnd>,
IsCommutable, Defs<[DSPOutFlag21]>;
class MULSAQ_S_W_PH_DESC : DPA_DESC_BASE<"mulsaq_s.w.ph",
@@ -789,10 +757,10 @@ class MAQ_SA_W_PHR_DESC : DPA_DESC_BASE<"maq_sa.w.phr", MipsMAQ_SA_W_PHR, v2i16>
Defs<[DSPOutFlag16_19]>;
// Move from/to hi/lo.
-class MFHI_DESC : MFHI_DESC_BASE<"mfhi", ACC64DSPOpnd, MipsMFHI, NoItinerary>;
-class MFLO_DESC : MFHI_DESC_BASE<"mflo", ACC64DSPOpnd, MipsMFLO, NoItinerary>;
-class MTHI_DESC : MTHI_DESC_BASE<"mthi", HI32DSPOpnd, NoItinerary>;
-class MTLO_DESC : MTHI_DESC_BASE<"mtlo", LO32DSPOpnd, NoItinerary>;
+class MFHI_DESC : MFHI_DESC_BASE<"mfhi", ACC64DSPOpnd, MipsMFHI>;
+class MFLO_DESC : MFHI_DESC_BASE<"mflo", ACC64DSPOpnd, MipsMFLO>;
+class MTHI_DESC : MTHI_DESC_BASE<"mthi", HI32DSPOpnd>;
+class MTLO_DESC : MTHI_DESC_BASE<"mtlo", LO32DSPOpnd>;
// Dot product with accumulate/subtract
class DPAU_H_QBL_DESC : DPA_DESC_BASE<"dpau.h.qbl", MipsDPAU_H_QBL, v4i8>;
@@ -815,122 +783,122 @@ class DPAQ_SA_L_W_DESC : DPA_DESC_BASE<"dpaq_sa.l.w", MipsDPAQ_SA_L_W, i32>,
class DPSQ_SA_L_W_DESC : DPA_DESC_BASE<"dpsq_sa.l.w", MipsDPSQ_SA_L_W, i32>,
Defs<[DSPOutFlag16_19]>;
-class MULT_DSP_DESC : MULT_DESC_BASE<"mult", MipsMult, NoItinerary>;
-class MULTU_DSP_DESC : MULT_DESC_BASE<"multu", MipsMultu, NoItinerary>;
-class MADD_DSP_DESC : MADD_DESC_BASE<"madd", MipsMAdd, NoItinerary>;
-class MADDU_DSP_DESC : MADD_DESC_BASE<"maddu", MipsMAddu, NoItinerary>;
-class MSUB_DSP_DESC : MADD_DESC_BASE<"msub", MipsMSub, NoItinerary>;
-class MSUBU_DSP_DESC : MADD_DESC_BASE<"msubu", MipsMSubu, NoItinerary>;
+class MULT_DSP_DESC : MULT_DESC_BASE<"mult", MipsMult>;
+class MULTU_DSP_DESC : MULT_DESC_BASE<"multu", MipsMultu>;
+class MADD_DSP_DESC : MADD_DESC_BASE<"madd", MipsMAdd>;
+class MADDU_DSP_DESC : MADD_DESC_BASE<"maddu", MipsMAddu>;
+class MSUB_DSP_DESC : MADD_DESC_BASE<"msub", MipsMSub>;
+class MSUBU_DSP_DESC : MADD_DESC_BASE<"msubu", MipsMSubu>;
// Comparison
class CMPU_EQ_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.eq.qb",
- int_mips_cmpu_eq_qb, NoItinerary,
+ int_mips_cmpu_eq_qb,
DSPROpnd>,
IsCommutable, Defs<[DSPCCond]>;
class CMPU_LT_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.lt.qb",
- int_mips_cmpu_lt_qb, NoItinerary,
+ int_mips_cmpu_lt_qb,
DSPROpnd>, Defs<[DSPCCond]>;
class CMPU_LE_QB_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmpu.le.qb",
- int_mips_cmpu_le_qb, NoItinerary,
+ int_mips_cmpu_le_qb,
DSPROpnd>, Defs<[DSPCCond]>;
class CMPGU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.eq.qb",
int_mips_cmpgu_eq_qb,
- NoItinerary, GPR32Opnd, DSPROpnd>,
+ GPR32Opnd, DSPROpnd>,
IsCommutable;
class CMPGU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.lt.qb",
int_mips_cmpgu_lt_qb,
- NoItinerary, GPR32Opnd, DSPROpnd>;
+ GPR32Opnd, DSPROpnd>;
class CMPGU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgu.le.qb",
int_mips_cmpgu_le_qb,
- NoItinerary, GPR32Opnd, DSPROpnd>;
+ GPR32Opnd, DSPROpnd>;
class CMP_EQ_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.eq.ph", int_mips_cmp_eq_ph,
- NoItinerary, DSPROpnd>,
+ DSPROpnd>,
IsCommutable, Defs<[DSPCCond]>;
class CMP_LT_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.lt.ph", int_mips_cmp_lt_ph,
- NoItinerary, DSPROpnd>,
+ DSPROpnd>,
Defs<[DSPCCond]>;
class CMP_LE_PH_DESC : CMP_EQ_QB_R2_DESC_BASE<"cmp.le.ph", int_mips_cmp_le_ph,
- NoItinerary, DSPROpnd>,
+ DSPROpnd>,
Defs<[DSPCCond]>;
// Misc
class BITREV_DESC : ABSQ_S_PH_R2_DESC_BASE<"bitrev", int_mips_bitrev,
- NoItinerary, GPR32Opnd>;
+ GPR32Opnd>;
class PACKRL_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"packrl.ph", int_mips_packrl_ph,
- NoItinerary, DSPROpnd, DSPROpnd>;
+ DSPROpnd, DSPROpnd>;
class REPL_QB_DESC : REPL_DESC_BASE<"repl.qb", int_mips_repl_qb, uimm8,
- immZExt8, NoItinerary, DSPROpnd>;
+ immZExt8, DSPROpnd>;
class REPL_PH_DESC : REPL_DESC_BASE<"repl.ph", int_mips_repl_ph, simm10,
- immSExt10, NoItinerary, DSPROpnd>;
+ immSExt10, DSPROpnd>;
class REPLV_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.qb", int_mips_repl_qb,
- NoItinerary, DSPROpnd, GPR32Opnd>;
+ DSPROpnd, GPR32Opnd>;
class REPLV_PH_DESC : ABSQ_S_PH_R2_DESC_BASE<"replv.ph", int_mips_repl_ph,
- NoItinerary, DSPROpnd, GPR32Opnd>;
+ DSPROpnd, GPR32Opnd>;
class PICK_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.qb", int_mips_pick_qb,
- NoItinerary, DSPROpnd, DSPROpnd>,
+ DSPROpnd, DSPROpnd>,
Uses<[DSPCCond]>;
class PICK_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"pick.ph", int_mips_pick_ph,
- NoItinerary, DSPROpnd, DSPROpnd>,
+ DSPROpnd, DSPROpnd>,
Uses<[DSPCCond]>;
-class LWX_DESC : LX_DESC_BASE<"lwx", int_mips_lwx, NoItinerary>;
+class LWX_DESC : LX_DESC_BASE<"lwx", int_mips_lwx>;
-class LHX_DESC : LX_DESC_BASE<"lhx", int_mips_lhx, NoItinerary>;
+class LHX_DESC : LX_DESC_BASE<"lhx", int_mips_lhx>;
-class LBUX_DESC : LX_DESC_BASE<"lbux", int_mips_lbux, NoItinerary>;
+class LBUX_DESC : LX_DESC_BASE<"lbux", int_mips_lbux>;
-class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", brtarget, NoItinerary>;
+class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", brtarget>;
// Extr
-class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", NoItinerary>,
+class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp">,
Uses<[DSPPos]>, Defs<[DSPEFI]>;
-class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv", NoItinerary>,
+class EXTPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpv">,
Uses<[DSPPos]>, Defs<[DSPEFI]>;
-class EXTPDP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extpdp", NoItinerary>,
+class EXTPDP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extpdp">,
Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;
-class EXTPDPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpdpv", NoItinerary>,
+class EXTPDPV_DESC : EXTR_W_TY1_R2_DESC_BASE<"extpdpv">,
Uses<[DSPPos]>, Defs<[DSPPos, DSPEFI]>;
-class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w", NoItinerary>,
+class EXTR_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr.w">,
Defs<[DSPOutFlag23]>;
-class EXTRV_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv.w", NoItinerary>,
+class EXTRV_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv.w">,
Defs<[DSPOutFlag23]>;
-class EXTR_R_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_r.w", NoItinerary>,
+class EXTR_R_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_r.w">,
Defs<[DSPOutFlag23]>;
-class EXTRV_R_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_r.w", NoItinerary>,
+class EXTRV_R_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_r.w">,
Defs<[DSPOutFlag23]>;
-class EXTR_RS_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_rs.w", NoItinerary>,
+class EXTR_RS_W_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_rs.w">,
Defs<[DSPOutFlag23]>;
-class EXTRV_RS_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_rs.w", NoItinerary>,
+class EXTRV_RS_W_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_rs.w">,
Defs<[DSPOutFlag23]>;
-class EXTR_S_H_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_s.h", NoItinerary>,
+class EXTR_S_H_DESC : EXTR_W_TY1_R1_DESC_BASE<"extr_s.h">,
Defs<[DSPOutFlag23]>;
-class EXTRV_S_H_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_s.h", NoItinerary>,
+class EXTRV_S_H_DESC : EXTR_W_TY1_R2_DESC_BASE<"extrv_s.h">,
Defs<[DSPOutFlag23]>;
class SHILO_DESC : SHILO_R1_DESC_BASE<"shilo", MipsSHILO>;
@@ -939,108 +907,108 @@ class SHILOV_DESC : SHILO_R2_DESC_BASE<"shilov", MipsSHILO>;
class MTHLIP_DESC : MTHLIP_DESC_BASE<"mthlip", MipsMTHLIP>, Defs<[DSPPos]>;
-class RDDSP_DESC : RDDSP_DESC_BASE<"rddsp", int_mips_rddsp, NoItinerary>;
+class RDDSP_DESC : RDDSP_DESC_BASE<"rddsp", int_mips_rddsp>;
-class WRDSP_DESC : WRDSP_DESC_BASE<"wrdsp", int_mips_wrdsp, NoItinerary>;
+class WRDSP_DESC : WRDSP_DESC_BASE<"wrdsp", int_mips_wrdsp>;
-class INSV_DESC : INSV_DESC_BASE<"insv", int_mips_insv, NoItinerary>,
+class INSV_DESC : INSV_DESC_BASE<"insv", int_mips_insv>,
Uses<[DSPPos, DSPSCount]>;
//===----------------------------------------------------------------------===//
// MIPS DSP Rev 2
// Addition/subtraction
-class ADDU_PH_DESC : ADDU_QB_DESC_BASE<"addu.ph", int_mips_addu_ph, NoItinerary,
+class ADDU_PH_DESC : ADDU_QB_DESC_BASE<"addu.ph", int_mips_addu_ph,
DSPROpnd, DSPROpnd>, IsCommutable,
Defs<[DSPOutFlag20]>;
class ADDU_S_PH_DESC : ADDU_QB_DESC_BASE<"addu_s.ph", int_mips_addu_s_ph,
- NoItinerary, DSPROpnd, DSPROpnd>,
+ DSPROpnd, DSPROpnd>,
IsCommutable, Defs<[DSPOutFlag20]>;
-class SUBU_PH_DESC : ADDU_QB_DESC_BASE<"subu.ph", int_mips_subu_ph, NoItinerary,
+class SUBU_PH_DESC : ADDU_QB_DESC_BASE<"subu.ph", int_mips_subu_ph,
DSPROpnd, DSPROpnd>,
Defs<[DSPOutFlag20]>;
class SUBU_S_PH_DESC : ADDU_QB_DESC_BASE<"subu_s.ph", int_mips_subu_s_ph,
- NoItinerary, DSPROpnd, DSPROpnd>,
+ DSPROpnd, DSPROpnd>,
Defs<[DSPOutFlag20]>;
class ADDUH_QB_DESC : ADDUH_QB_DESC_BASE<"adduh.qb", int_mips_adduh_qb,
- NoItinerary, DSPROpnd>, IsCommutable;
+ DSPROpnd>, IsCommutable;
class ADDUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"adduh_r.qb", int_mips_adduh_r_qb,
- NoItinerary, DSPROpnd>, IsCommutable;
+ DSPROpnd>, IsCommutable;
class SUBUH_QB_DESC : ADDUH_QB_DESC_BASE<"subuh.qb", int_mips_subuh_qb,
- NoItinerary, DSPROpnd>;
+ DSPROpnd>;
class SUBUH_R_QB_DESC : ADDUH_QB_DESC_BASE<"subuh_r.qb", int_mips_subuh_r_qb,
- NoItinerary, DSPROpnd>;
+ DSPROpnd>;
class ADDQH_PH_DESC : ADDUH_QB_DESC_BASE<"addqh.ph", int_mips_addqh_ph,
- NoItinerary, DSPROpnd>, IsCommutable;
+ DSPROpnd>, IsCommutable;
class ADDQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"addqh_r.ph", int_mips_addqh_r_ph,
- NoItinerary, DSPROpnd>, IsCommutable;
+ DSPROpnd>, IsCommutable;
class SUBQH_PH_DESC : ADDUH_QB_DESC_BASE<"subqh.ph", int_mips_subqh_ph,
- NoItinerary, DSPROpnd>;
+ DSPROpnd>;
class SUBQH_R_PH_DESC : ADDUH_QB_DESC_BASE<"subqh_r.ph", int_mips_subqh_r_ph,
- NoItinerary, DSPROpnd>;
+ DSPROpnd>;
class ADDQH_W_DESC : ADDUH_QB_DESC_BASE<"addqh.w", int_mips_addqh_w,
- NoItinerary, GPR32Opnd>, IsCommutable;
+ GPR32Opnd>, IsCommutable;
class ADDQH_R_W_DESC : ADDUH_QB_DESC_BASE<"addqh_r.w", int_mips_addqh_r_w,
- NoItinerary, GPR32Opnd>, IsCommutable;
+ GPR32Opnd>, IsCommutable;
class SUBQH_W_DESC : ADDUH_QB_DESC_BASE<"subqh.w", int_mips_subqh_w,
- NoItinerary, GPR32Opnd>;
+ GPR32Opnd>;
class SUBQH_R_W_DESC : ADDUH_QB_DESC_BASE<"subqh_r.w", int_mips_subqh_r_w,
- NoItinerary, GPR32Opnd>;
+ GPR32Opnd>;
// Comparison
class CMPGDU_EQ_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.eq.qb",
int_mips_cmpgdu_eq_qb,
- NoItinerary, GPR32Opnd, DSPROpnd>,
+ GPR32Opnd, DSPROpnd>,
IsCommutable, Defs<[DSPCCond]>;
class CMPGDU_LT_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.lt.qb",
int_mips_cmpgdu_lt_qb,
- NoItinerary, GPR32Opnd, DSPROpnd>,
+ GPR32Opnd, DSPROpnd>,
Defs<[DSPCCond]>;
class CMPGDU_LE_QB_DESC : CMP_EQ_QB_R3_DESC_BASE<"cmpgdu.le.qb",
int_mips_cmpgdu_le_qb,
- NoItinerary, GPR32Opnd, DSPROpnd>,
+ GPR32Opnd, DSPROpnd>,
Defs<[DSPCCond]>;
// Absolute
class ABSQ_S_QB_DESC : ABSQ_S_PH_R2_DESC_BASE<"absq_s.qb", int_mips_absq_s_qb,
- NoItinerary, DSPROpnd>,
+ DSPROpnd>,
Defs<[DSPOutFlag20]>;
// Multiplication
-class MUL_PH_DESC : ADDUH_QB_DESC_BASE<"mul.ph", null_frag, NoItinerary,
+class MUL_PH_DESC : ADDUH_QB_DESC_BASE<"mul.ph", null_frag,
DSPROpnd>, IsCommutable,
Defs<[DSPOutFlag21]>;
class MUL_S_PH_DESC : ADDUH_QB_DESC_BASE<"mul_s.ph", int_mips_mul_s_ph,
- NoItinerary, DSPROpnd>, IsCommutable,
+ DSPROpnd>, IsCommutable,
Defs<[DSPOutFlag21]>;
class MULQ_S_W_DESC : ADDUH_QB_DESC_BASE<"mulq_s.w", int_mips_mulq_s_w,
- NoItinerary, GPR32Opnd>, IsCommutable,
+ GPR32Opnd>, IsCommutable,
Defs<[DSPOutFlag21]>;
class MULQ_RS_W_DESC : ADDUH_QB_DESC_BASE<"mulq_rs.w", int_mips_mulq_rs_w,
- NoItinerary, GPR32Opnd>, IsCommutable,
+ GPR32Opnd>, IsCommutable,
Defs<[DSPOutFlag21]>;
class MULQ_S_PH_DESC : ADDU_QB_DESC_BASE<"mulq_s.ph", int_mips_mulq_s_ph,
- NoItinerary, DSPROpnd, DSPROpnd>,
+ DSPROpnd, DSPROpnd>,
IsCommutable, Defs<[DSPOutFlag21]>;
// Dot product with accumulate/subtract
@@ -1071,47 +1039,45 @@ class MULSA_W_PH_DESC : DPA_DESC_BASE<"mulsa.w.ph", MipsMULSA_W_PH, v2i16>;
// Precision reduce/expand
class PRECR_QB_PH_DESC : CMP_EQ_QB_R3_DESC_BASE<"precr.qb.ph",
int_mips_precr_qb_ph,
- NoItinerary, DSPROpnd, DSPROpnd>;
+ DSPROpnd, DSPROpnd>;
class PRECR_SRA_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra.ph.w",
int_mips_precr_sra_ph_w,
- NoItinerary, DSPROpnd,
+ DSPROpnd,
GPR32Opnd>;
class PRECR_SRA_R_PH_W_DESC : PRECR_SRA_PH_W_DESC_BASE<"precr_sra_r.ph.w",
int_mips_precr_sra_r_ph_w,
- NoItinerary, DSPROpnd,
+ DSPROpnd,
GPR32Opnd>;
// Shift
class SHRA_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra.qb", null_frag, immZExt3,
- NoItinerary, DSPROpnd, uimm3>;
+ DSPROpnd, uimm3>;
class SHRAV_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav.qb", int_mips_shra_qb,
- NoItinerary, DSPROpnd>;
+ DSPROpnd>;
class SHRA_R_QB_DESC : SHLL_QB_R2_DESC_BASE<"shra_r.qb", int_mips_shra_r_qb,
- immZExt3, NoItinerary, DSPROpnd,
+ immZExt3, DSPROpnd,
uimm3>;
class SHRAV_R_QB_DESC : SHLL_QB_R3_DESC_BASE<"shrav_r.qb", int_mips_shra_r_qb,
- NoItinerary, DSPROpnd>;
+ DSPROpnd>;
class SHRL_PH_DESC : SHLL_QB_R2_DESC_BASE<"shrl.ph", null_frag, immZExt4,
- NoItinerary, DSPROpnd, uimm4>;
+ DSPROpnd, uimm4>;
class SHRLV_PH_DESC : SHLL_QB_R3_DESC_BASE<"shrlv.ph", int_mips_shrl_ph,
- NoItinerary, DSPROpnd>;
+ DSPROpnd>;
// Misc
-class APPEND_DESC : APPEND_DESC_BASE<"append", int_mips_append, uimm5, timmZExt5,
- NoItinerary>;
+class APPEND_DESC : APPEND_DESC_BASE<"append", int_mips_append, uimm5, timmZExt5>;
-class BALIGN_DESC : APPEND_DESC_BASE<"balign", int_mips_balign, uimm2, timmZExt2,
- NoItinerary>;
+class BALIGN_DESC : APPEND_DESC_BASE<"balign", int_mips_balign, uimm2, timmZExt2>;
class PREPEND_DESC : APPEND_DESC_BASE<"prepend", int_mips_prepend, uimm5,
- timmZExt5, NoItinerary>;
+ timmZExt5>;
// Pseudos.
def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32>,
@@ -1298,8 +1264,8 @@ let isPseudo = 1, isCodeGenOnly = 1, hasNoSchedulingInfo = 1 in {
let DecoderNamespace = "MipsDSP", Arch = "dsp",
ASEPredicate = [HasDSP] in {
- def LWDSP : Load<"lw", DSPROpnd, null_frag, II_LW>, DspMMRel, LW_FM<0x23>;
- def SWDSP : Store<"sw", DSPROpnd, null_frag, II_SW>, DspMMRel, LW_FM<0x2b>;
+ def LWDSP : Load<"lw", DSPROpnd>, DspMMRel, LW_FM<0x23>;
+ def SWDSP : Store<"sw", DSPROpnd>, DspMMRel, LW_FM<0x2b>;
}
// Pseudo CMP and PICK instructions.
diff --git a/llvm/lib/Target/Mips/MipsEVAInstrFormats.td b/llvm/lib/Target/Mips/MipsEVAInstrFormats.td
index acec9bb03ca4b..ec786c56c744e 100644
--- a/llvm/lib/Target/Mips/MipsEVAInstrFormats.td
+++ b/llvm/lib/Target/Mips/MipsEVAInstrFormats.td
@@ -10,7 +10,7 @@
//
//===----------------------------------------------------------------------===//
-class MipsEVAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>,
+class MipsEVAInst : MipsInst<(outs), (ins), "", [], FrmOther>,
StdArch {
let DecoderNamespace = "Mips";
let EncodingPredicates = [HasStdEnc];
diff --git a/llvm/lib/Target/Mips/MipsEVAInstrInfo.td b/llvm/lib/Target/Mips/MipsEVAInstrInfo.td
index 1dd32543b7738..e8bb88c6955c6 100644
--- a/llvm/lib/Target/Mips/MipsEVAInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsEVAInstrInfo.td
@@ -50,8 +50,7 @@ class PREFE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_PREFE>;
//===----------------------------------------------------------------------===//
// Memory Load/Store EVA descriptions
-class LOAD_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- InstrItinClass itin = NoItinerary> {
+class LOAD_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
dag OutOperandList = (outs GPROpnd:$rt);
dag InOperandList = (ins mem_simm9:$addr);
string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
@@ -60,17 +59,15 @@ class LOAD_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
bit canFoldAsLoad = 1;
string BaseOpcode = instr_asm;
bit mayLoad = 1;
- InstrItinClass Itinerary = itin;
}
-class LBE_DESC : LOAD_EVA_DESC_BASE<"lbe", GPR32Opnd, II_LBE>;
-class LBuE_DESC : LOAD_EVA_DESC_BASE<"lbue", GPR32Opnd, II_LBUE>;
-class LHE_DESC : LOAD_EVA_DESC_BASE<"lhe", GPR32Opnd, II_LHE>;
-class LHuE_DESC : LOAD_EVA_DESC_BASE<"lhue", GPR32Opnd, II_LHUE>;
-class LWE_DESC : LOAD_EVA_DESC_BASE<"lwe", GPR32Opnd, II_LWE>;
+class LBE_DESC : LOAD_EVA_DESC_BASE<"lbe", GPR32Opnd>;
+class LBuE_DESC : LOAD_EVA_DESC_BASE<"lbue", GPR32Opnd>;
+class LHE_DESC : LOAD_EVA_DESC_BASE<"lhe", GPR32Opnd>;
+class LHuE_DESC : LOAD_EVA_DESC_BASE<"lhue", GPR32Opnd>;
+class LWE_DESC : LOAD_EVA_DESC_BASE<"lwe", GPR32Opnd>;
-class STORE_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- InstrItinClass itin> {
+class STORE_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
dag OutOperandList = (outs);
dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr);
string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
@@ -78,16 +75,14 @@ class STORE_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
string DecoderMethod = "DecodeMemEVA";
string BaseOpcode = instr_asm;
bit mayStore = 1;
- InstrItinClass Itinerary = itin;
}
-class SBE_DESC : STORE_EVA_DESC_BASE<"sbe", GPR32Opnd, II_SBE>;
-class SHE_DESC : STORE_EVA_DESC_BASE<"she", GPR32Opnd, II_SHE>;
-class SWE_DESC : STORE_EVA_DESC_BASE<"swe", GPR32Opnd, II_SWE>;
+class SBE_DESC : STORE_EVA_DESC_BASE<"sbe", GPR32Opnd>;
+class SHE_DESC : STORE_EVA_DESC_BASE<"she", GPR32Opnd>;
+class SWE_DESC : STORE_EVA_DESC_BASE<"swe", GPR32Opnd>;
// Load/Store Left/Right EVA descriptions
-class LOAD_LEFT_RIGHT_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- InstrItinClass itin = NoItinerary> {
+class LOAD_LEFT_RIGHT_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
dag OutOperandList = (outs GPROpnd:$rt);
dag InOperandList = (ins mem_simm9:$addr, GPROpnd:$src);
string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
@@ -96,33 +91,29 @@ class LOAD_LEFT_RIGHT_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
string BaseOpcode = instr_asm;
string Constraints = "$src = $rt";
bit canFoldAsLoad = 1;
- InstrItinClass Itinerary = itin;
bit mayLoad = 1;
bit mayStore = 0;
}
-class LWLE_DESC : LOAD_LEFT_RIGHT_EVA_DESC_BASE<"lwle", GPR32Opnd, II_LWLE>;
-class LWRE_DESC : LOAD_LEFT_RIGHT_EVA_DESC_BASE<"lwre", GPR32Opnd, II_LWRE>;
+class LWLE_DESC : LOAD_LEFT_RIGHT_EVA_DESC_BASE<"lwle", GPR32Opnd>;
+class LWRE_DESC : LOAD_LEFT_RIGHT_EVA_DESC_BASE<"lwre", GPR32Opnd>;
-class STORE_LEFT_RIGHT_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- InstrItinClass itin = NoItinerary> {
+class STORE_LEFT_RIGHT_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
dag OutOperandList = (outs);
dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr);
string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
list<dag> Pattern = [];
string DecoderMethod = "DecodeMemEVA";
string BaseOpcode = instr_asm;
- InstrItinClass Itinerary = itin;
bit mayLoad = 0;
bit mayStore = 1;
}
-class SWLE_DESC : STORE_LEFT_RIGHT_EVA_DESC_BASE<"swle", GPR32Opnd, II_SWLE>;
-class SWRE_DESC : STORE_LEFT_RIGHT_EVA_DESC_BASE<"swre", GPR32Opnd, II_SWRE>;
+class SWLE_DESC : STORE_LEFT_RIGHT_EVA_DESC_BASE<"swle", GPR32Opnd>;
+class SWRE_DESC : STORE_LEFT_RIGHT_EVA_DESC_BASE<"swre", GPR32Opnd>;
// Load-linked EVA, Store-conditional EVA descriptions
-class LLE_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- InstrItinClass itin = NoItinerary> {
+class LLE_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
dag OutOperandList = (outs GPROpnd:$rt);
dag InOperandList = (ins mem_simm9:$addr);
string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
@@ -130,13 +121,11 @@ class LLE_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
string BaseOpcode = instr_asm;
bit mayLoad = 1;
string DecoderMethod = "DecodeMemEVA";
- InstrItinClass Itinerary = itin;
}
-class LLE_DESC : LLE_DESC_BASE<"lle", GPR32Opnd, II_LLE>;
+class LLE_DESC : LLE_DESC_BASE<"lle", GPR32Opnd>;
-class SCE_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
- InstrItinClass itin = NoItinerary> {
+class SCE_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
dag OutOperandList = (outs GPROpnd:$dst);
dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr);
string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
@@ -145,24 +134,21 @@ class SCE_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
bit mayStore = 1;
string Constraints = "$rt = $dst";
string DecoderMethod = "DecodeMemEVA";
- InstrItinClass Itinerary = itin;
}
-class SCE_DESC : SCE_DESC_BASE<"sce", GPR32Opnd, II_SCE>;
+class SCE_DESC : SCE_DESC_BASE<"sce", GPR32Opnd>;
-class TLB_DESC_BASE<string instr_asm, InstrItinClass itin = NoItinerary> {
+class TLB_DESC_BASE<string instr_asm> {
dag OutOperandList = (outs);
dag InOperandList = (ins);
string AsmString = instr_asm;
list<dag> Pattern = [];
- InstrItinClass Itinerary = itin;
}
-class TLBINV_DESC : TLB_DESC_BASE<"tlbinv", II_TLBINV>;
-class TLBINVF_DESC : TLB_DESC_BASE<"tlbinvf", II_TLBINVF>;
+class TLBINV_DESC : TLB_DESC_BASE<"tlbinv">;
+class TLBINVF_DESC : TLB_DESC_BASE<"tlbinvf">;
-class CACHEE_DESC_BASE<string instr_asm, Operand MemOpnd,
- InstrItinClass itin = NoItinerary> {
+class CACHEE_DESC_BASE<string instr_asm, Operand MemOpnd> {
// CACHEE puts the "hint" immediate where the encoding would otherwise have "rt"
bits<5> hint;
bits<5> rt = hint;
@@ -173,11 +159,10 @@ class CACHEE_DESC_BASE<string instr_asm, Operand MemOpnd,
list<dag> Pattern = [];
string BaseOpcode = instr_asm;
string DecoderMethod = "DecodeCacheeOp_CacheOpR6";
- InstrItinClass Itinerary = itin;
}
-class CACHEE_DESC : CACHEE_DESC_BASE<"cachee", mem_simm9, II_CACHEE>;
-class PREFE_DESC : CACHEE_DESC_BASE<"prefe", mem_simm9, II_PREFE>;
+class CACHEE_DESC : CACHEE_DESC_BASE<"cachee", mem_simm9>;
+class PREFE_DESC : CACHEE_DESC_BASE<"prefe", mem_simm9>;
//===----------------------------------------------------------------------===//
//
diff --git a/llvm/lib/Target/Mips/MipsInstrFPU.td b/llvm/lib/Target/Mips/MipsInstrFPU.td
index e4370bbeacf44..36e22c7fecbb5 100644
--- a/llvm/lib/Target/Mips/MipsInstrFPU.td
+++ b/llvm/lib/Target/Mips/MipsInstrFPU.td
@@ -118,19 +118,19 @@ def fpimm0neg : PatLeaf<(fpimm), [{
//
// Only S32 and D32 are supported right now.
//===----------------------------------------------------------------------===//
-class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm,
+class ADDS_FT<string opstr, RegisterOperand RC, bit IsComm,
SDPatternOperator OpNode= null_frag> :
InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft),
!strconcat(opstr, "\t$fd, $fs, $ft"),
- [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr>,
+ [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], FrmFR, opstr>,
HARDFLOAT {
let isCommutable = IsComm;
}
-multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm,
+multiclass ADDS_M<string opstr, bit IsComm,
SDPatternOperator OpNode = null_frag> {
- def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>, FGR_32;
- def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, FGR_64 {
+ def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, IsComm, OpNode>, FGR_32;
+ def _D64 : ADDS_FT<opstr, FGR64Opnd, IsComm, OpNode>, FGR_64 {
string DecoderNamespace = "MipsFP64";
}
}
@@ -139,121 +139,119 @@ class ABSS_FT_PatFrag<SDPatternOperator OpNode>:
PatFrag<(ops node:$fs), (OpNode node:$fs),
[{ return Subtarget->inAbs2008Mode() || N->getFlags().hasNoNaNs(); }]>;
class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
- InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
+ SDPatternOperator OpNode= null_frag> :
InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
- [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
+ [(set DstRC:$fd, (OpNode SrcRC:$fs))], FrmFR, opstr>,
HARDFLOAT,
NeverHasSideEffects;
class CVT_PS_S_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
- InstrItinClass Itin, bit IsComm,
+ bit IsComm,
SDPatternOperator OpNode = null_frag> :
InstSE<(outs DstRC:$fd), (ins SrcRC:$fs, SrcRC:$ft),
!strconcat(opstr, "\t$fd, $fs, $ft"),
- [(set DstRC:$fd, (OpNode SrcRC:$fs, SrcRC:$ft))], Itin, FrmFR, opstr>,
+ [(set DstRC:$fd, (OpNode SrcRC:$fs, SrcRC:$ft))], FrmFR, opstr>,
HARDFLOAT {
let isCommutable = IsComm;
}
-let mayRaiseFPException = 1, Uses = [FCR31] in
-multiclass ABSS_M<string opstr, InstrItinClass Itin,
+multiclass ABSS_M<string opstr,
SDPatternOperator OpNode= null_frag> {
- def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
+ def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, OpNode>,
FGR_32;
- def _D64 : StdMMR6Rel, ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>,
+ def _D64 : StdMMR6Rel, ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, OpNode>,
FGR_64 {
string DecoderNamespace = "MipsFP64";
}
}
-multiclass ROUND_M<string opstr, InstrItinClass Itin> {
- def _D32 : MMRel, ABSS_FT<opstr, FGR32Opnd, AFGR64Opnd, Itin>, FGR_32;
- def _D64 : StdMMR6Rel, ABSS_FT<opstr, FGR32Opnd, FGR64Opnd, Itin>, FGR_64 {
+multiclass ROUND_M<string opstr> {
+ def _D32 : MMRel, ABSS_FT<opstr, FGR32Opnd, AFGR64Opnd>, FGR_32;
+ def _D64 : StdMMR6Rel, ABSS_FT<opstr, FGR32Opnd, FGR64Opnd>, FGR_64 {
let DecoderNamespace = "MipsFP64";
}
}
class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
- InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
+ SDPatternOperator OpNode= null_frag> :
InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
- [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, HARDFLOAT {
+ [(set DstRC:$rt, (OpNode SrcRC:$fs))], FrmFR, opstr>, HARDFLOAT {
let isMoveReg = 1;
}
class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
- InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
+ SDPatternOperator OpNode= null_frag> :
InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
- [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR, opstr>, HARDFLOAT {
+ [(set DstRC:$fs, (OpNode SrcRC:$rt))], FrmFR, opstr>, HARDFLOAT {
let isMoveReg = 1;
}
-class MTC1_64_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
- InstrItinClass Itin> :
+class MTC1_64_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC> :
InstSE<(outs DstRC:$fs), (ins DstRC:$fs_in, SrcRC:$rt),
- !strconcat(opstr, "\t$rt, $fs"), [], Itin, FrmFR, opstr>, HARDFLOAT {
+ !strconcat(opstr, "\t$rt, $fs"), [], FrmFR, opstr>, HARDFLOAT {
// $fs_in is part of a white lie to work around a widespread bug in the FPU
// implementation. See expandBuildPairF64 for details.
let Constraints = "$fs = $fs_in";
}
class LW_FT<string opstr, RegisterOperand RC, DAGOperand MO,
- InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
+ SDPatternOperator OpNode = null_frag> :
InstSE<(outs RC:$rt), (ins MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
- [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr>,
+ [(set RC:$rt, (OpNode addrDefault:$addr))], FrmFI, opstr>,
HARDFLOAT {
let DecoderMethod = "DecodeFMem";
let mayLoad = 1;
}
class SW_FT<string opstr, RegisterOperand RC, DAGOperand MO,
- InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
+ SDPatternOperator OpNode = null_frag> :
InstSE<(outs), (ins RC:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
- [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr>, HARDFLOAT {
+ [(OpNode RC:$rt, addrDefault:$addr)], FrmFI, opstr>, HARDFLOAT {
let DecoderMethod = "DecodeFMem";
let mayStore = 1;
}
-class MADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
+class MADDS_FT<string opstr, RegisterOperand RC,
SDPatternOperator OpNode = null_frag> :
InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
!strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
- [(set RC:$fd, (OpNode (any_fmul RC:$fs, RC:$ft), RC:$fr))], Itin,
+ [(set RC:$fd, (OpNode (any_fmul RC:$fs, RC:$ft), RC:$fr))],
FrmFR, opstr>, HARDFLOAT;
class NMADDS_FT_PatFrag<SDPatternOperator OpNode> :
PatFrag<(ops node:$fr, node:$fs, node:$ft),
(any_fsub fpimm0, (OpNode (any_fmul node:$fs, node:$ft), node:$fr)),
[{ return N->getFlags().hasNoNaNs(); }]>;
-class NMADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
+class NMADDS_FT<string opstr, RegisterOperand RC,
SDPatternOperator OpNode = null_frag> :
InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
!strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
[(set RC:$fd, (any_fsub fpimm0, (OpNode (any_fmul RC:$fs, RC:$ft), RC:$fr)))],
- Itin, FrmFR, opstr>, HARDFLOAT;
+ FrmFR, opstr>, HARDFLOAT;
class LWXC1_FT<string opstr, RegisterOperand DRC,
- InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
+ SDPatternOperator OpNode = null_frag> :
InstSE<(outs DRC:$fd), (ins PtrRC:$base, PtrRC:$index),
!strconcat(opstr, "\t$fd, ${index}(${base})"),
- [(set DRC:$fd, (OpNode (add iPTR:$base, iPTR:$index)))], Itin,
+ [(set DRC:$fd, (OpNode (add iPTR:$base, iPTR:$index)))],
FrmFI, opstr>, HARDFLOAT {
let AddedComplexity = 20;
}
class SWXC1_FT<string opstr, RegisterOperand DRC,
- InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
+ SDPatternOperator OpNode = null_frag> :
InstSE<(outs), (ins DRC:$fs, PtrRC:$base, PtrRC:$index),
!strconcat(opstr, "\t$fs, ${index}(${base})"),
- [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin,
+ [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))],
FrmFI, opstr>, HARDFLOAT {
let AddedComplexity = 20;
}
-class BC1F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin,
+class BC1F_FT<string opstr, DAGOperand opnd,
SDPatternOperator Op = null_frag> :
InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset),
!strconcat(opstr, "\t$fcc, $offset"),
- [(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin,
+ [(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)],
FrmFI, opstr>, HARDFLOAT {
let isBranch = 1;
let isTerminator = 1;
@@ -262,9 +260,9 @@ class BC1F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin,
let hasFCCRegOperand = 1;
}
-class BC1XL_FT<string opstr, DAGOperand opnd, InstrItinClass Itin> :
+class BC1XL_FT<string opstr, DAGOperand opnd> :
InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset),
- !strconcat(opstr, "\t$fcc, $offset"), [], Itin,
+ !strconcat(opstr, "\t$fcc, $offset"), [],
FrmFI, opstr>, HARDFLOAT {
let isBranch = 1;
let isTerminator = 1;
@@ -273,11 +271,11 @@ class BC1XL_FT<string opstr, DAGOperand opnd, InstrItinClass Itin> :
let hasFCCRegOperand = 1;
}
-class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin,
+class CEQS_FT<string typestr, RegisterClass RC,
SDPatternOperator OpNode = null_frag> :
InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond),
!strconcat("c.$cond.", typestr, "\t$fs, $ft"),
- [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR,
+ [(OpNode RC:$fs, RC:$ft, imm:$cond)], FrmFR,
!strconcat("c.$cond.", typestr)>, HARDFLOAT {
let Defs = [FCC0];
let isCodeGenOnly = 1;
@@ -289,96 +287,93 @@ class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin,
// duplicating the instruction definition for MIPS1 - MIPS3, we expand
// c.cond.ft if necessary, and reject it after constructing the
// instruction if the ISA doesn't support it.
-class C_COND_FT<string CondStr, string Typestr, RegisterOperand RC,
- InstrItinClass itin> :
+class C_COND_FT<string CondStr, string Typestr, RegisterOperand RC> :
InstSE<(outs FCCRegsOpnd:$fcc), (ins RC:$fs, RC:$ft),
- !strconcat("c.", CondStr, ".", Typestr, "\t$fcc, $fs, $ft"), [], itin,
+ !strconcat("c.", CondStr, ".", Typestr, "\t$fcc, $fs, $ft"), [],
FrmFR>, HARDFLOAT {
let isCompare = 1;
let hasFCCRegOperand = 1;
}
-multiclass C_COND_M<string TypeStr, RegisterOperand RC, bits<5> fmt,
- InstrItinClass itin> {
- def C_F_#NAME : MMRel, C_COND_FT<"f", TypeStr, RC, itin>,
+multiclass C_COND_M<string TypeStr, RegisterOperand RC, bits<5> fmt> {
+ def C_F_#NAME : MMRel, C_COND_FT<"f", TypeStr, RC>,
C_COND_FM<fmt, 0> {
let BaseOpcode = "c.f."#NAME;
let isCommutable = 1;
}
- def C_EQ_#NAME : MMRel, C_COND_FT<"eq", TypeStr, RC, itin>,
+ def C_EQ_#NAME : MMRel, C_COND_FT<"eq", TypeStr, RC>,
C_COND_FM<fmt, 2> {
let BaseOpcode = "c.eq."#NAME;
let isCommutable = 1;
}
- def C_OLT_#NAME : MMRel, C_COND_FT<"olt", TypeStr, RC, itin>,
+ def C_OLT_#NAME : MMRel, C_COND_FT<"olt", TypeStr, RC>,
C_COND_FM<fmt, 4> {
let BaseOpcode = "c.olt."#NAME;
}
- def C_OLE_#NAME : MMRel, C_COND_FT<"ole", TypeStr, RC, itin>,
+ def C_OLE_#NAME : MMRel, C_COND_FT<"ole", TypeStr, RC>,
C_COND_FM<fmt, 6> {
let BaseOpcode = "c.ole."#NAME;
}
}
-multiclass C_COND_NOTR5900_M<string TypeStr, RegisterOperand RC, bits<5> fmt,
- InstrItinClass itin> {
- def C_UN_#NAME : MMRel, C_COND_FT<"un", TypeStr, RC, itin>,
+multiclass C_COND_NOTR5900_M<string TypeStr, RegisterOperand RC, bits<5> fmt> {
+ def C_UN_#NAME : MMRel, C_COND_FT<"un", TypeStr, RC>,
C_COND_FM<fmt, 1> {
let BaseOpcode = "c.un."#NAME;
let isCommutable = 1;
}
- def C_UEQ_#NAME : MMRel, C_COND_FT<"ueq", TypeStr, RC, itin>,
+ def C_UEQ_#NAME : MMRel, C_COND_FT<"ueq", TypeStr, RC>,
C_COND_FM<fmt, 3> {
let BaseOpcode = "c.ueq."#NAME;
let isCommutable = 1;
}
- def C_ULT_#NAME : MMRel, C_COND_FT<"ult", TypeStr, RC, itin>,
+ def C_ULT_#NAME : MMRel, C_COND_FT<"ult", TypeStr, RC>,
C_COND_FM<fmt, 5> {
let BaseOpcode = "c.ult."#NAME;
}
- def C_ULE_#NAME : MMRel, C_COND_FT<"ule", TypeStr, RC, itin>,
+ def C_ULE_#NAME : MMRel, C_COND_FT<"ule", TypeStr, RC>,
C_COND_FM<fmt, 7> {
let BaseOpcode = "c.ule."#NAME;
}
let mayRaiseFPException = 1 in {
- def C_SF_#NAME : MMRel, C_COND_FT<"sf", TypeStr, RC, itin>,
+ def C_SF_#NAME : MMRel, C_COND_FT<"sf", TypeStr, RC>,
C_COND_FM<fmt, 8> {
let BaseOpcode = "c.sf."#NAME;
let isCommutable = 1;
let mayRaiseFPException = 1;
}
- def C_NGLE_#NAME : MMRel, C_COND_FT<"ngle", TypeStr, RC, itin>,
+ def C_NGLE_#NAME : MMRel, C_COND_FT<"ngle", TypeStr, RC>,
C_COND_FM<fmt, 9> {
let BaseOpcode = "c.ngle."#NAME;
let mayRaiseFPException = 1;
}
- def C_SEQ_#NAME : MMRel, C_COND_FT<"seq", TypeStr, RC, itin>,
+ def C_SEQ_#NAME : MMRel, C_COND_FT<"seq", TypeStr, RC>,
C_COND_FM<fmt, 10> {
let BaseOpcode = "c.seq."#NAME;
let isCommutable = 1;
let mayRaiseFPException = 1;
}
- def C_NGL_#NAME : MMRel, C_COND_FT<"ngl", TypeStr, RC, itin>,
+ def C_NGL_#NAME : MMRel, C_COND_FT<"ngl", TypeStr, RC>,
C_COND_FM<fmt, 11> {
let BaseOpcode = "c.ngl."#NAME;
let mayRaiseFPException = 1;
}
- def C_LT_#NAME : MMRel, C_COND_FT<"lt", TypeStr, RC, itin>,
+ def C_LT_#NAME : MMRel, C_COND_FT<"lt", TypeStr, RC>,
C_COND_FM<fmt, 12> {
let BaseOpcode = "c.lt."#NAME;
let mayRaiseFPException = 1;
}
- def C_NGE_#NAME : MMRel, C_COND_FT<"nge", TypeStr, RC, itin>,
+ def C_NGE_#NAME : MMRel, C_COND_FT<"nge", TypeStr, RC>,
C_COND_FM<fmt, 13> {
let BaseOpcode = "c.nge."#NAME;
let mayRaiseFPException = 1;
}
- def C_LE_#NAME : MMRel, C_COND_FT<"le", TypeStr, RC, itin>,
+ def C_LE_#NAME : MMRel, C_COND_FT<"le", TypeStr, RC>,
C_COND_FM<fmt, 14> {
let BaseOpcode = "c.le."#NAME;
let mayRaiseFPException = 1;
}
- def C_NGT_#NAME : MMRel, C_COND_FT<"ngt", TypeStr, RC, itin>,
+ def C_NGT_#NAME : MMRel, C_COND_FT<"ngt", TypeStr, RC>,
C_COND_FM<fmt, 15> {
let BaseOpcode = "c.ngt."#NAME;
let mayRaiseFPException = 1;
@@ -387,17 +382,17 @@ multiclass C_COND_NOTR5900_M<string TypeStr, RegisterOperand RC, bits<5> fmt,
}
let AdditionalPredicates = [NotInMicroMips] in {
-defm S : C_COND_M<"s", FGR32Opnd, 16, II_C_CC_S>, ISA_MIPS1_NOT_32R6_64R6;
-defm S : C_COND_NOTR5900_M<"s", FGR32Opnd, 16, II_C_CC_S>,
+defm S : C_COND_M<"s", FGR32Opnd, 16>, ISA_MIPS1_NOT_32R6_64R6;
+defm S : C_COND_NOTR5900_M<"s", FGR32Opnd, 16>,
ISA_MIPS1_NOT_32R6_64R6_R5900;
-defm D32 : C_COND_M<"d", AFGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6,
+defm D32 : C_COND_M<"d", AFGR64Opnd, 17>, ISA_MIPS1_NOT_32R6_64R6,
FGR_32;
-defm D32 : C_COND_NOTR5900_M<"d", AFGR64Opnd, 17, II_C_CC_D>,
+defm D32 : C_COND_NOTR5900_M<"d", AFGR64Opnd, 17>,
ISA_MIPS1_NOT_32R6_64R6, FGR_32;
let DecoderNamespace = "MipsFP64" in {
-defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6,
+defm D64 : C_COND_M<"d", FGR64Opnd, 17>, ISA_MIPS1_NOT_32R6_64R6,
FGR_64;
-defm D64 : C_COND_NOTR5900_M<"d", FGR64Opnd, 17, II_C_CC_D>,
+defm D64 : C_COND_NOTR5900_M<"d", FGR64Opnd, 17>,
ISA_MIPS1_NOT_32R6_64R6, FGR_64;
}
}
@@ -405,147 +400,139 @@ defm D64 : C_COND_NOTR5900_M<"d", FGR64Opnd, 17, II_C_CC_D>,
// Floating Point Instructions
//===----------------------------------------------------------------------===//
let AdditionalPredicates = [NotInMicroMips], mayRaiseFPException = 1 in {
- def ROUND_W_S : MMRel,
- StdMMR6Rel,
- ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>,
- ABSS_FM<0xc, 16>,
- ISA_MIPS2_NOT_R5900;
- defm ROUND_W : ROUND_M<"round.w.d", II_ROUND>, ABSS_FM<0xc, 17>, ISA_MIPS2;
- def TRUNC_W_S : MMRel,
- StdMMR6Rel,
- ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>,
- ABSS_FM<0xd, 16>,
- ISA_MIPS2_NOT_R5900;
- def CEIL_W_S : MMRel,
- StdMMR6Rel,
- ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>,
- ABSS_FM<0xe, 16>,
- ISA_MIPS2_NOT_R5900;
- def FLOOR_W_S : MMRel,
- StdMMR6Rel,
- ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>,
- ABSS_FM<0xf, 16>,
- ISA_MIPS2_NOT_R5900;
-
- defm TRUNC_W : ROUND_M<"trunc.w.d", II_TRUNC>, ABSS_FM<0xd, 17>, ISA_MIPS2;
- defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2;
- defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2;
+ def ROUND_W_S : MMRel, StdMMR6Rel,
+ ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd>,
+ ABSS_FM<0xc, 16>, ISA_MIPS2_NOT_R5900;
+ defm ROUND_W : ROUND_M<"round.w.d">, ABSS_FM<0xc, 17>, ISA_MIPS2;
+ def TRUNC_W_S : MMRel, StdMMR6Rel,
+ ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd>,
+ ABSS_FM<0xd, 16>, ISA_MIPS2_NOT_R5900;
+ def CEIL_W_S : MMRel, StdMMR6Rel,
+ ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd>,
+ ABSS_FM<0xe, 16>, ISA_MIPS2_NOT_R5900;
+ def FLOOR_W_S : MMRel, StdMMR6Rel,
+ ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd>,
+ ABSS_FM<0xf, 16>, ISA_MIPS2_NOT_R5900;
+
+ defm TRUNC_W : ROUND_M<"trunc.w.d">, ABSS_FM<0xd, 17>, ISA_MIPS2;
+ defm CEIL_W : ROUND_M<"ceil.w.d">, ABSS_FM<0xe, 17>, ISA_MIPS2;
+ defm FLOOR_W : ROUND_M<"floor.w.d">, ABSS_FM<0xf, 17>, ISA_MIPS2;
let Uses = [FCR31] in {
- def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>, // fp
+ def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd>, // fp
ABSS_FM<0x24, 16>, ISA_MIPS1;
- defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>, ISA_MIPS1;
+ defm CVT_W : ROUND_M<"cvt.w.d">, ABSS_FM<0x24, 17>, ISA_MIPS1;
}
}
let AdditionalPredicates = [NotInMicroMips], mayRaiseFPException = 1, Uses = [FCR31] in {
- def RECIP_S : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd, II_RECIP_S>,
+ def RECIP_S : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd>,
ABSS_FM<0b010101, 0x10>, INSN_MIPS4_32R2;
- def RECIP_D32 : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd, II_RECIP_D>,
+ def RECIP_D32 : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd>,
ABSS_FM<0b010101, 0x11>, INSN_MIPS4_32R2, FGR_32 {
let BaseOpcode = "RECIP_D32";
}
let DecoderNamespace = "MipsFP64" in
- def RECIP_D64 : MMRel, ABSS_FT<"recip.d", FGR64Opnd, FGR64Opnd,
- II_RECIP_D>, ABSS_FM<0b010101, 0x11>,
+ def RECIP_D64 : MMRel, ABSS_FT<"recip.d", FGR64Opnd, FGR64Opnd>,
+ ABSS_FM<0b010101, 0x11>,
INSN_MIPS4_32R2, FGR_64;
- def RSQRT_S : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd, II_RSQRT_S>,
+ def RSQRT_S : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd>,
ABSS_FM<0b010110, 0x10>, INSN_MIPS4_32R2;
- def RSQRT_D32 : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd, II_RSQRT_D>,
+ def RSQRT_D32 : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd>,
ABSS_FM<0b010110, 0x11>, INSN_MIPS4_32R2, FGR_32 {
let BaseOpcode = "RSQRT_D32";
}
let DecoderNamespace = "MipsFP64" in
- def RSQRT_D64 : MMRel, ABSS_FT<"rsqrt.d", FGR64Opnd, FGR64Opnd,
- II_RSQRT_D>, ABSS_FM<0b010110, 0x11>,
+ def RSQRT_D64 : MMRel, ABSS_FT<"rsqrt.d", FGR64Opnd, FGR64Opnd>,
+ ABSS_FM<0b010110, 0x11>,
INSN_MIPS4_32R2, FGR_64;
}
let DecoderNamespace = "MipsFP64", mayRaiseFPException = 1 in {
let AdditionalPredicates = [NotInMicroMips] in {
- def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>,
+ def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd>,
ABSS_FM<0x8, 16>, ISA_MIPS2, FGR_64;
- def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, II_ROUND>,
+ def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd>,
ABSS_FM<0x8, 17>, INSN_MIPS3_32, FGR_64;
- def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, II_TRUNC>,
+ def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd>,
ABSS_FM<0x9, 16>, ISA_MIPS2, FGR_64;
- def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd, II_TRUNC>,
+ def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd>,
ABSS_FM<0x9, 17>, INSN_MIPS3_32, FGR_64;
- def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64Opnd, FGR32Opnd, II_CEIL>,
+ def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64Opnd, FGR32Opnd>,
ABSS_FM<0xa, 16>, ISA_MIPS2, FGR_64;
- def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64Opnd, FGR64Opnd, II_CEIL>,
+ def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64Opnd, FGR64Opnd>,
ABSS_FM<0xa, 17>, INSN_MIPS3_32, FGR_64;
- def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64Opnd, FGR32Opnd, II_FLOOR>,
+ def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64Opnd, FGR32Opnd>,
ABSS_FM<0xb, 16>, ISA_MIPS2, FGR_64;
- def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64Opnd, FGR64Opnd, II_FLOOR>,
+ def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64Opnd, FGR64Opnd>,
ABSS_FM<0xb, 17>, INSN_MIPS3_32, FGR_64;
}
}
let AdditionalPredicates = [NotInMicroMips], mayRaiseFPException = 1, Uses = [FCR31] in{
- def CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
+ def CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd>,
ABSS_FM<0x20, 20>, ISA_MIPS1;
- def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
+ def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd>,
ABSS_FM<0x25, 16>, INSN_MIPS3_32R2;
- def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
+ def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd>,
ABSS_FM<0x25, 17>, INSN_MIPS3_32R2;
}
let AdditionalPredicates = [NotInMicroMips], mayRaiseFPException = 1, Uses = [FCR31] in {
- def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
+ def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd>,
ABSS_FM<0x20, 17>, ISA_MIPS1, FGR_32;
- def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>,
+ def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd>,
ABSS_FM<0x21, 16>, ISA_MIPS1, FGR_32;
- def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>,
+ def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd>,
ABSS_FM<0x21, 20>, ISA_MIPS1, FGR_32;
}
let DecoderNamespace = "MipsFP64", AdditionalPredicates = [NotInMicroMips] in {
let mayRaiseFPException = 1, Uses = [FCR31] in {
- def FADD_PS64 : ADDS_FT<"add.ps", FGR64Opnd, II_ADD_PS, 0>,
+ def FADD_PS64 : ADDS_FT<"add.ps", FGR64Opnd, 0>,
ADDS_FM<0x0, 22>,
ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
- def FMUL_PS64 : ADDS_FT<"mul.ps", FGR64Opnd, II_MUL_PS, 0>,
+ def FMUL_PS64 : ADDS_FT<"mul.ps", FGR64Opnd, 0>,
ADDS_FM<0x2, 22>,
ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
- def FSUB_PS64 : ADDS_FT<"sub.ps", FGR64Opnd, II_SUB_PS, 0>,
+ def FSUB_PS64 : ADDS_FT<"sub.ps", FGR64Opnd, 0>,
ADDS_FM<0x1, 22>,
ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
- def CVT_PS_S64 : CVT_PS_S_FT<"cvt.ps.s", FGR64Opnd, FGR32Opnd, II_CVT, 0>,
+ def CVT_PS_S64 : CVT_PS_S_FT<"cvt.ps.s", FGR64Opnd, FGR32Opnd, 0>,
ADDS_FM<0x26, 16>,
ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
}
- def PLL_PS64 : ADDS_FT<"pll.ps", FGR64Opnd, II_CVT, 0>,
+ def PLL_PS64 : ADDS_FT<"pll.ps", FGR64Opnd, 0>,
ADDS_FM<0x2C, 22>,
ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
- def PLU_PS64 : ADDS_FT<"plu.ps", FGR64Opnd, II_CVT, 0>,
+ def PLU_PS64 : ADDS_FT<"plu.ps", FGR64Opnd, 0>,
ADDS_FM<0x2D, 22>,
ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
- def PUL_PS64 : ADDS_FT<"pul.ps", FGR64Opnd, II_CVT, 0>,
+ def PUL_PS64 : ADDS_FT<"pul.ps", FGR64Opnd, 0>,
ADDS_FM<0x2E, 22>,
ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
- def PUU_PS64 : ADDS_FT<"puu.ps", FGR64Opnd, II_CVT, 0>,
+ def PUU_PS64 : ADDS_FT<"puu.ps", FGR64Opnd, 0>,
ADDS_FM<0x2F, 22>,
ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
- def CVT_S_PU64 : ABSS_FT<"cvt.s.pu", FGR32Opnd, FGR64Opnd, II_CVT>,
+ def CVT_S_PU64 : ABSS_FT<"cvt.s.pu", FGR32Opnd, FGR64Opnd>,
ABSS_FM<0x20, 22>,
ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
- def CVT_S_PL64 : ABSS_FT<"cvt.s.pl", FGR32Opnd, FGR64Opnd, II_CVT>,
+ def CVT_S_PL64 : ABSS_FT<"cvt.s.pl", FGR32Opnd, FGR64Opnd>,
ABSS_FM<0x28, 22>,
ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
}
let DecoderNamespace = "MipsFP64", mayRaiseFPException = 1, Uses = [FCR31] in {
let AdditionalPredicates = [HasMips3D] in {
- def ADDR_PS64 : ADDS_FT<"addr.ps", FGR64Opnd, II_ADDR_PS, 0>,
+ def ADDR_PS64 : ADDS_FT<"addr.ps", FGR64Opnd, 0>,
ADDS_FM<0x18, 22>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
- def MULR_PS64 : ADDS_FT<"mulr.ps", FGR64Opnd, II_MULR_PS, 0>,
+ def MULR_PS64 : ADDS_FT<"mulr.ps", FGR64Opnd, 0>,
ADDS_FM<0x1a, 22>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
- def CVT_PS_PW64 : ABSS_FT<"cvt.ps.pw", FGR64Opnd, FGR64Opnd, II_CVT>,
+ def CVT_PS_PW64 : ABSS_FT<"cvt.ps.pw", FGR64Opnd, FGR64Opnd>,
ABSS_FM<0x26, 20>,
ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
- def CVT_PW_PS64 : ABSS_FT<"cvt.pw.ps", FGR64Opnd, FGR64Opnd, II_CVT>,
+ def CVT_PW_PS64 : ABSS_FT<"cvt.pw.ps", FGR64Opnd, FGR64Opnd>,
ABSS_FM<0x24, 22>,
ISA_MIPS32R2_NOT_32R6_64R6, FGR_64;
}
@@ -553,33 +540,33 @@ let DecoderNamespace = "MipsFP64", mayRaiseFPException = 1, Uses = [FCR31] in {
let DecoderNamespace = "MipsFP64", mayRaiseFPException = 1, Uses = [FCR31] in {
let AdditionalPredicates = [NotInMicroMips] in {
- def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>,
+ def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd>,
ABSS_FM<0x20, 21>, INSN_MIPS3_32R2, FGR_64;
- def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>,
+ def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd>,
ABSS_FM<0x20, 17>, ISA_MIPS1, FGR_64;
- def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>,
+ def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd>,
ABSS_FM<0x21, 20>, ISA_MIPS1, FGR_64;
- def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>,
+ def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd>,
ABSS_FM<0x21, 16>, ISA_MIPS1, FGR_64;
- def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, II_CVT>,
+ def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd>,
ABSS_FM<0x21, 21>, INSN_MIPS3_32R2, FGR_64;
}
}
let isPseudo = 1, isCodeGenOnly = 1 in {
- def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd, II_CVT>;
+ def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd>;
let Predicates = [IsNotSingleFloat] in {
- def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd, II_CVT>;
- def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>;
- def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd, II_CVT>;
- def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>;
+ def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd>;
+ def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd>;
+ def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd>;
+ def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd>;
}
}
let AdditionalPredicates = [NotInMicroMips] in {
- def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS>,
+ def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, fabs>,
ABSS_FM<0x5, 16>, ISA_MIPS1;
- defm FABS : ABSS_M<"abs.d", II_ABS>, ABSS_FM<0x5, 17>, ISA_MIPS1;
+ defm FABS : ABSS_M<"abs.d", fabs>, ABSS_FM<0x5, 17>, ISA_MIPS1;
}
let Predicates = FABS_S.Predicates in
def : Pat<(ABSS_FT_PatFrag<fabs> FGR32Opnd:$fs), (FABS_S FGR32Opnd:$fs)>;
@@ -588,16 +575,16 @@ def : Pat<(ABSS_FT_PatFrag<fabs> AFGR64Opnd:$fs), (FABS_D32 AFGR64Opnd:$fs)>;
let Predicates = FABS_D64.Predicates in
def : Pat<(ABSS_FT_PatFrag<fabs> FGR64Opnd:$fs), (FABS_D64 FGR64Opnd:$fs)>;
-def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>,
+def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, fneg>,
ABSS_FM<0x7, 16>, ISA_MIPS1;
let AdditionalPredicates = [NotInMicroMips] in {
- defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>, ISA_MIPS1;
+ defm FNEG : ABSS_M<"neg.d", fneg>, ABSS_FM<0x7, 17>, ISA_MIPS1;
}
let AdditionalPredicates = [NotInMicroMips], mayRaiseFPException = 1, Uses = [FCR31] in {
def FSQRT_S : MMRel, StdMMR6Rel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd,
- II_SQRT_S, any_fsqrt>, ABSS_FM<0x4, 16>, ISA_MIPS2;
- defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, any_fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2;
+ any_fsqrt>, ABSS_FM<0x4, 16>, ISA_MIPS2;
+ defm FSQRT : ABSS_M<"sqrt.d", any_fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2;
}
// The odd-numbered registers are only referenced when doing loads,
@@ -607,173 +594,173 @@ let AdditionalPredicates = [NotInMicroMips], mayRaiseFPException = 1, Uses = [FC
/// Move Control Registers From/To CPU Registers
let AdditionalPredicates = [NotInMicroMips] in {
- def CFC1 : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, MFC1_FM<2>,
+ def CFC1 : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd>, MFC1_FM<2>,
ISA_MIPS1;
- def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>,
+ def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd>, MFC1_FM<6>,
ISA_MIPS1;
- def MFC1 : MMRel, StdMMR6Rel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1,
+ def MFC1 : MMRel, StdMMR6Rel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd,
bitconvert>, MFC1_FM<0>, ISA_MIPS1;
- def MFC1_D64 : MFC1_FT<"mfc1", GPR32Opnd, FGR64Opnd, II_MFC1>, MFC1_FM<0>,
+ def MFC1_D64 : MFC1_FT<"mfc1", GPR32Opnd, FGR64Opnd>, MFC1_FM<0>,
ISA_MIPS1, FGR_64 {
let DecoderNamespace = "MipsFP64";
}
- def MTC1 : MMRel, StdMMR6Rel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1,
+ def MTC1 : MMRel, StdMMR6Rel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd,
bitconvert>, MFC1_FM<4>, ISA_MIPS1;
- def MTC1_D64 : MTC1_FT<"mtc1", FGR64Opnd, GPR32Opnd, II_MTC1>, MFC1_FM<4>,
+ def MTC1_D64 : MTC1_FT<"mtc1", FGR64Opnd, GPR32Opnd>, MFC1_FM<4>,
ISA_MIPS1, FGR_64 {
let DecoderNamespace = "MipsFP64";
}
- def MFHC1_D32 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
+ def MFHC1_D32 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd>,
MFC1_FM<3>, ISA_MIPS32R2, FGR_32;
- def MFHC1_D64 : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>,
+ def MFHC1_D64 : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd>,
MFC1_FM<3>, ISA_MIPS32R2, FGR_64 {
let DecoderNamespace = "MipsFP64";
}
def MTHC1_D32 : MMRel, StdMMR6Rel,
- MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
+ MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd>,
MFC1_FM<7>, ISA_MIPS32R2, FGR_32;
- def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>,
+ def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd>,
MFC1_FM<7>, ISA_MIPS32R2, FGR_64 {
let DecoderNamespace = "MipsFP64";
}
let AdditionalPredicates = [IsNotSingleFloat] in {
- def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1, bitconvert>,
+ def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, bitconvert>,
MFC1_FM<5>,
ISA_MIPS3;
- def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1, bitconvert>,
+ def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, bitconvert>,
MFC1_FM<1>,
ISA_MIPS3;
}
let isMoveReg = 1 in {
- def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,
+ def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd>,
ABSS_FM<0x6, 16>, ISA_MIPS1;
- defm FMOV : ABSS_M<"mov.d", II_MOV_D>, ABSS_FM<0x6, 17>, ISA_MIPS1;
+ defm FMOV : ABSS_M<"mov.d">, ABSS_FM<0x6, 17>, ISA_MIPS1;
} // isMoveReg
}
/// Floating Point Memory Instructions
let AdditionalPredicates = [NotInMicroMips] in {
- def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, mem_simm16, II_LWC1, load>,
+ def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, mem_simm16, load>,
LW_FM<0x31>, ISA_MIPS1;
- def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, mem_simm16, II_SWC1, store>,
+ def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, mem_simm16, store>,
LW_FM<0x39>, ISA_MIPS1;
}
let DecoderNamespace = "MipsFP64", AdditionalPredicates = [NotInMicroMips] in {
- def LDC164 : StdMMR6Rel, LW_FT<"ldc1", FGR64Opnd, mem_simm16, II_LDC1, load>,
+ def LDC164 : StdMMR6Rel, LW_FT<"ldc1", FGR64Opnd, mem_simm16, load>,
LW_FM<0x35>, ISA_MIPS2, FGR_64 {
let BaseOpcode = "LDC164";
}
- def SDC164 : StdMMR6Rel, SW_FT<"sdc1", FGR64Opnd, mem_simm16, II_SDC1, store>,
+ def SDC164 : StdMMR6Rel, SW_FT<"sdc1", FGR64Opnd, mem_simm16, store>,
LW_FM<0x3d>, ISA_MIPS2, FGR_64;
}
let AdditionalPredicates = [NotInMicroMips] in {
- def LDC1 : MMRel, StdMMR6Rel, LW_FT<"ldc1", AFGR64Opnd, mem_simm16, II_LDC1,
+ def LDC1 : MMRel, StdMMR6Rel, LW_FT<"ldc1", AFGR64Opnd, mem_simm16,
load>, LW_FM<0x35>, ISA_MIPS2, FGR_32 {
let BaseOpcode = "LDC132";
}
- def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, mem_simm16, II_SDC1, store>,
+ def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, mem_simm16, store>,
LW_FM<0x3d>, ISA_MIPS2, FGR_32;
}
// Indexed loads and stores.
// Base register + offset register addressing mode (indicated by "x" in the
// instruction mnemonic).
-def LWXC1 : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM<0>,
+def LWXC1 : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, load>, LWXC1_FM<0>,
INSN_MIPS4_32R2_NOT_32R6_64R6;
-def SWXC1 : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, SWXC1_FM<8>,
+def SWXC1 : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, store>, SWXC1_FM<8>,
INSN_MIPS4_32R2_NOT_32R6_64R6;
let AdditionalPredicates = [NotInMicroMips] in {
- def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>,
+ def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, load>, LWXC1_FM<1>,
INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
- def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>,
+ def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, store>, SWXC1_FM<9>,
INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
}
let DecoderNamespace="MipsFP64" in {
- def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>,
+ def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, load>, LWXC1_FM<1>,
INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
- def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>,
+ def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, store>, SWXC1_FM<9>,
INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
}
// Load/store doubleword indexed unaligned.
// FIXME: This instruction should not be defined for FGR_32.
let AdditionalPredicates = [NotInMicroMips] in {
- def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
+ def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd>, LWXC1_FM<0x5>,
INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32;
- def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,
+ def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd>, SWXC1_FM<0xd>,
INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32;
}
let AdditionalPredicates = [NotInMicroMips],
DecoderNamespace="MipsFP64" in {
- def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
+ def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd>, LWXC1_FM<0x5>,
INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;
- def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,
+ def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd>, SWXC1_FM<0xd>,
INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;
}
/// Floating-point Arithmetic
let AdditionalPredicates = [NotInMicroMips], mayRaiseFPException = 1, Uses = [FCR31] in {
- def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, any_fadd>,
+ def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, 1, any_fadd>,
ADDS_FM<0x00, 16>, ISA_MIPS1;
- defm FADD : ADDS_M<"add.d", II_ADD_D, 1, any_fadd>, ADDS_FM<0x00, 17>,
+ defm FADD : ADDS_M<"add.d", 1, any_fadd>, ADDS_FM<0x00, 17>,
ISA_MIPS1;
- def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, any_fdiv>,
+ def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, 0, any_fdiv>,
ADDS_FM<0x03, 16>, ISA_MIPS1;
- defm FDIV : ADDS_M<"div.d", II_DIV_D, 0, any_fdiv>, ADDS_FM<0x03, 17>,
+ defm FDIV : ADDS_M<"div.d", 0, any_fdiv>, ADDS_FM<0x03, 17>,
ISA_MIPS1;
- def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, any_fmul>,
+ def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, 1, any_fmul>,
ADDS_FM<0x02, 16>, ISA_MIPS1;
- defm FMUL : ADDS_M<"mul.d", II_MUL_D, 1, any_fmul>, ADDS_FM<0x02, 17>,
+ defm FMUL : ADDS_M<"mul.d", 1, any_fmul>, ADDS_FM<0x02, 17>,
ISA_MIPS1;
- def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, any_fsub>,
+ def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, 0, any_fsub>,
ADDS_FM<0x01, 16>, ISA_MIPS1;
- defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, any_fsub>, ADDS_FM<0x01, 17>,
+ defm FSUB : ADDS_M<"sub.d", 0, any_fsub>, ADDS_FM<0x01, 17>,
ISA_MIPS1;
}
let AdditionalPredicates = [NotInMicroMips, HasMadd4], mayRaiseFPException = 1, Uses = [FCR31] in {
- def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, any_fadd>,
+ def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, any_fadd>,
MADDS_FM<4, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
- def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, any_fsub>,
+ def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, any_fsub>,
MADDS_FM<5, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
- def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, any_fadd>,
+ def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, any_fadd>,
MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
- def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, any_fsub>,
+ def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, any_fsub>,
MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
let DecoderNamespace = "MipsFP64" in {
- def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, any_fadd>,
+ def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, any_fadd>,
MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
- def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, any_fsub>,
+ def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, any_fsub>,
MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
}
}
let AdditionalPredicates = [HasMadd4, NotInMicroMips], mayRaiseFPException = 1, Uses = [FCR31] in {
- def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S>,
+ def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd>,
MADDS_FM<6, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
- def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S>,
+ def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd>,
MADDS_FM<7, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
- def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D>,
+ def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd>,
MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
- def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D>,
+ def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd>,
MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
let DecoderNamespace = "MipsFP64" in {
- def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D>,
+ def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd>,
MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
- def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, II_NMSUB_D>,
+ def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd>,
MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
}
}
@@ -804,17 +791,17 @@ def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
let AdditionalPredicates = [NotInMicroMips] in {
- def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, II_BC1F, MIPS_BRANCH_F>,
+ def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, MIPS_BRANCH_F>,
BC1F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6;
- def BC1FL : MMRel, BC1XL_FT<"bc1fl", brtarget, II_BC1FL>,
+ def BC1FL : MMRel, BC1XL_FT<"bc1fl", brtarget>,
BC1F_FM<1, 0>, ISA_MIPS2_NOT_32R6_64R6;
- def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, II_BC1T, MIPS_BRANCH_T>,
+ def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, MIPS_BRANCH_T>,
BC1F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6;
- def BC1TL : MMRel, BC1XL_FT<"bc1tl", brtarget, II_BC1TL>,
+ def BC1TL : MMRel, BC1XL_FT<"bc1tl", brtarget>,
BC1F_FM<1, 1>, ISA_MIPS2_NOT_32R6_64R6;
/// Floating Point Compare
- def FCMP_S32 : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, CEQS_FM<16>,
+ def FCMP_S32 : MMRel, CEQS_FT<"s", FGR32, MipsFPCmp>, CEQS_FM<16>,
ISA_MIPS1_NOT_32R6_64R6 {
// FIXME: This is a required to work around the fact that these instructions
@@ -822,7 +809,7 @@ let AdditionalPredicates = [NotInMicroMips] in {
// fcc register set is used directly.
bits<3> fcc = 0;
}
- def FCMP_D32 : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>,
+ def FCMP_D32 : MMRel, CEQS_FT<"d", AFGR64, MipsFPCmp>, CEQS_FM<17>,
ISA_MIPS1_NOT_32R6_64R6, FGR_32 {
// FIXME: This is a required to work around the fact that these instructions
// only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the
@@ -831,7 +818,7 @@ let AdditionalPredicates = [NotInMicroMips] in {
}
}
let DecoderNamespace = "MipsFP64" in
-def FCMP_D64 : CEQS_FT<"d", FGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>,
+def FCMP_D64 : CEQS_FT<"d", FGR64, MipsFPCmp>, CEQS_FM<17>,
ISA_MIPS1_NOT_32R6_64R6, FGR_64 {
// FIXME: This is a required to work around the fact that thiese instructions
// only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the
@@ -847,8 +834,7 @@ def FCMP_D64 : CEQS_FT<"d", FGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>,
// allocation.
class BuildPairF64Base<RegisterOperand RO> :
PseudoSE<(outs RO:$dst), (ins GPR32Opnd:$lo, GPR32Opnd:$hi),
- [(set RO:$dst, (MipsBuildPairF64 GPR32Opnd:$lo, GPR32Opnd:$hi))],
- II_MTC1>;
+ [(set RO:$dst, (MipsBuildPairF64 GPR32Opnd:$lo, GPR32Opnd:$hi))]>;
def BuildPairF64 : BuildPairF64Base<AFGR64Opnd>, FGR_32, HARDFLOAT;
def BuildPairF64_64 : BuildPairF64Base<FGR64Opnd>, FGR_64, HARDFLOAT;
@@ -861,8 +847,7 @@ def BuildPairF64_64 : BuildPairF64Base<FGR64Opnd>, FGR_64, HARDFLOAT;
// asserts otherwise.
class ExtractElementF64Base<RegisterOperand RO> :
PseudoSE<(outs GPR32Opnd:$dst), (ins RO:$src, i32imm:$n),
- [(set GPR32Opnd:$dst, (MipsExtractElementF64 RO:$src, imm:$n))],
- II_MFC1>;
+ [(set GPR32Opnd:$dst, (MipsExtractElementF64 RO:$src, imm:$n))]>;
def ExtractElementF64 : ExtractElementF64Base<AFGR64Opnd>, FGR_32, HARDFLOAT;
def ExtractElementF64_64 : ExtractElementF64Base<FGR64Opnd>, FGR_64, HARDFLOAT;
diff --git a/llvm/lib/Target/Mips/MipsInstrFormats.td b/llvm/lib/Target/Mips/MipsInstrFormats.td
index 992b3ae11a178..5240550130d3c 100644
--- a/llvm/lib/Target/Mips/MipsInstrFormats.td
+++ b/llvm/lib/Target/Mips/MipsInstrFormats.td
@@ -69,7 +69,7 @@ class StdArch {
// Generic Mips Format
class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
- InstrItinClass itin, Format f>: Instruction, PredicateControl
+ Format f>: Instruction, PredicateControl
{
field bits<32> Inst;
Format Form = f;
@@ -88,7 +88,7 @@ class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
let AsmString = asmstr;
let Pattern = pattern;
- let Itinerary = itin;
+
//
// Attributes specific to Mips instructions...
@@ -111,25 +111,23 @@ class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
// Mips32/64 Instruction Format
class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
- InstrItinClass itin, Format f, string opstr = ""> :
- MipsInst<outs, ins, asmstr, pattern, itin, f> {
+ Format f, string opstr = ""> :
+ MipsInst<outs, ins, asmstr, pattern, f> {
let EncodingPredicates = [NotInMips16Mode];
string BaseOpcode = opstr;
string Arch;
}
// Mips Pseudo Instructions Format
-class MipsPseudo<dag outs, dag ins, list<dag> pattern,
- InstrItinClass itin = IIPseudo> :
- MipsInst<outs, ins, "", pattern, itin, Pseudo> {
+class MipsPseudo<dag outs, dag ins, list<dag> pattern> :
+ MipsInst<outs, ins, "", pattern, Pseudo> {
let isCodeGenOnly = 1;
let isPseudo = 1;
}
// Mips32/64 Pseudo Instruction Format
-class PseudoSE<dag outs, dag ins, list<dag> pattern,
- InstrItinClass itin = IIPseudo> :
- MipsPseudo<outs, ins, pattern, itin> {
+class PseudoSE<dag outs, dag ins, list<dag> pattern> :
+ MipsPseudo<outs, ins, pattern> {
let EncodingPredicates = [NotInMips16Mode];
}
@@ -137,7 +135,7 @@ class PseudoSE<dag outs, dag ins, list<dag> pattern,
// These are aliases that require C++ handling to convert to the target
// instruction, while InstAliases can be handled directly by tblgen.
class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>:
- MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> {
+ MipsInst<outs, ins, asmstr, [], Pseudo> {
let isPseudo = 1;
let hasNoSchedulingInfo = 1;
let Pattern = [];
@@ -147,8 +145,8 @@ class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>:
//===----------------------------------------------------------------------===//
class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
- list<dag> pattern, InstrItinClass itin>:
- InstSE<outs, ins, asmstr, pattern, itin, FrmR>
+ list<dag> pattern>:
+ InstSE<outs, ins, asmstr, pattern, FrmR>
{
bits<5> rd;
bits<5> rs;
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td
index 76bfe31534161..8953e8b99af78 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.td
@@ -1358,11 +1358,10 @@ def addrimm10lsl3 : ComplexPattern<iPTR, 2, "selectIntAddrSImm10Lsl3",
// Arithmetic and logical instructions with 3 register operands.
class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
- InstrItinClass Itin = NoItinerary,
SDPatternOperator OpNode = null_frag>:
InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
!strconcat(opstr, "\t$rd, $rs, $rt"),
- [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
+ [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], FrmR, opstr> {
let isCommutable = isComm;
let isReMaterializable = 1;
let TwoOperandAliasConstraint = "$rd = $rs";
@@ -1370,21 +1369,20 @@ class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
// Arithmetic and logical instructions with 2 register operands.
class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
- InstrItinClass Itin = NoItinerary,
SDPatternOperator imm_type = null_frag,
SDPatternOperator OpNode = null_frag> :
InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
!strconcat(opstr, "\t$rt, $rs, $imm16"),
[(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
- Itin, FrmI, opstr> {
+ FrmI, opstr> {
let isReMaterializable = 1;
let TwoOperandAliasConstraint = "$rs = $rt";
}
// Arithmetic Multiply ADD/SUB
-class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
+class MArithR<string opstr, bit isComm = 0> :
InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
- !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
+ !strconcat(opstr, "\t$rs, $rt"), [], FrmR, opstr> {
let Defs = [HI0, LO0];
let Uses = [HI0, LO0];
let isCommutable = isComm;
@@ -1394,32 +1392,32 @@ class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
class LogicNOR<string opstr, RegisterOperand RO>:
InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
!strconcat(opstr, "\t$rd, $rs, $rt"),
- [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
+ [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], FrmR, opstr> {
let isCommutable = 1;
}
// Shifts
class shift_rotate_imm<string opstr, Operand ImmOpnd,
- RegisterOperand RO, InstrItinClass itin,
+ RegisterOperand RO,
SDPatternOperator OpNode = null_frag,
SDPatternOperator PF = null_frag> :
InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
!strconcat(opstr, "\t$rd, $rt, $shamt"),
- [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
+ [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], FrmR, opstr> {
let TwoOperandAliasConstraint = "$rt = $rd";
}
-class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
+class shift_rotate_reg<string opstr, RegisterOperand RO,
SDPatternOperator OpNode = null_frag>:
InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
!strconcat(opstr, "\t$rd, $rt, $rs"),
- [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
+ [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], FrmR,
opstr>;
// Load Upper Immediate
class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
- [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
+ [], FrmI, opstr>, IsAsCheapAsAMove {
let hasSideEffects = 0;
let isReMaterializable = 1;
}
@@ -1427,10 +1425,9 @@ class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
// Memory Load/Store
class LoadMemory<string opstr, DAGOperand RO, DAGOperand MO,
SDPatternOperator OpNode = null_frag,
- InstrItinClass Itin = NoItinerary,
ComplexPattern Addr = addr> :
InstSE<(outs RO:$rt), (ins MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
- [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
+ [(set RO:$rt, (OpNode Addr:$addr))], FrmI, opstr> {
let DecoderMethod = "DecodeMem";
let canFoldAsLoad = 1;
string BaseOpcode = opstr;
@@ -1438,76 +1435,73 @@ class LoadMemory<string opstr, DAGOperand RO, DAGOperand MO,
}
class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
- InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
- LoadMemory<opstr, RO, mem, OpNode, Itin, Addr>;
+ ComplexPattern Addr = addr> :
+ LoadMemory<opstr, RO, mem, OpNode, Addr>;
class StoreMemory<string opstr, DAGOperand RO, DAGOperand MO,
SDPatternOperator OpNode = null_frag,
- InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
+ ComplexPattern Addr = addr> :
InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
- [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
+ [(OpNode RO:$rt, Addr:$addr)], FrmI, opstr> {
let DecoderMethod = "DecodeMem";
string BaseOpcode = opstr;
let mayStore = 1;
}
class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
- InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr,
- DAGOperand MO = mem> :
- StoreMemory<opstr, RO, MO, OpNode, Itin, Addr>;
+ ComplexPattern Addr = addr, DAGOperand MO = mem> :
+ StoreMemory<opstr, RO, MO, OpNode, Addr>;
// Load/Store Left/Right
let canFoldAsLoad = 1 in
-class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
- InstrItinClass Itin> :
+class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO> :
InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
!strconcat(opstr, "\t$rt, $addr"),
- [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
+ [(set RO:$rt, (OpNode addr:$addr, RO:$src))], FrmI> {
let DecoderMethod = "DecodeMem";
string Constraints = "$src = $rt";
let BaseOpcode = opstr;
}
-class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
- InstrItinClass Itin> :
+class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO> :
InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
- [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
+ [(OpNode RO:$rt, addr:$addr)], FrmI> {
let DecoderMethod = "DecodeMem";
let BaseOpcode = opstr;
}
// COP2 Load/Store
-class LW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
+class LW_FT2<string opstr, RegisterOperand RC,
SDPatternOperator OpNode= null_frag> :
InstSE<(outs RC:$rt), (ins mem_simm16:$addr),
!strconcat(opstr, "\t$rt, $addr"),
- [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
+ [(set RC:$rt, (OpNode addrDefault:$addr))], FrmFI, opstr> {
let DecoderMethod = "DecodeFMem2";
let mayLoad = 1;
}
-class SW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
+class SW_FT2<string opstr, RegisterOperand RC,
SDPatternOperator OpNode= null_frag> :
InstSE<(outs), (ins RC:$rt, mem_simm16:$addr),
!strconcat(opstr, "\t$rt, $addr"),
- [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
+ [(OpNode RC:$rt, addrDefault:$addr)], FrmFI, opstr> {
let DecoderMethod = "DecodeFMem2";
let mayStore = 1;
}
// COP3 Load/Store
-class LW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
+class LW_FT3<string opstr, RegisterOperand RC,
SDPatternOperator OpNode= null_frag> :
InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
- [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
+ [(set RC:$rt, (OpNode addrDefault:$addr))], FrmFI, opstr> {
let DecoderMethod = "DecodeFMem3";
let mayLoad = 1;
}
-class SW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
+class SW_FT3<string opstr, RegisterOperand RC,
SDPatternOperator OpNode= null_frag> :
InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
- [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
+ [(OpNode RC:$rt, addrDefault:$addr)], FrmFI, opstr> {
let DecoderMethod = "DecodeFMem3";
let mayStore = 1;
}
@@ -1517,7 +1511,7 @@ class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
RegisterOperand RO> :
InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
!strconcat(opstr, "\t$rs, $rt, $offset"),
- [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], II_BCC,
+ [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)],
FrmI, opstr> {
let isBranch = 1;
let isTerminator = 1;
@@ -1528,7 +1522,7 @@ class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
class CBranchLikely<string opstr, DAGOperand opnd, RegisterOperand RO> :
InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
- !strconcat(opstr, "\t$rs, $rt, $offset"), [], II_BCC, FrmI, opstr> {
+ !strconcat(opstr, "\t$rs, $rt, $offset"), [], FrmI, opstr> {
let isBranch = 1;
let isTerminator = 1;
let hasDelaySlot = 1;
@@ -1540,7 +1534,7 @@ class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
RegisterOperand RO> :
InstSE<(outs), (ins RO:$rs, opnd:$offset),
!strconcat(opstr, "\t$rs, $offset"),
- [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], II_BCCZ,
+ [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)],
FrmI, opstr> {
let isBranch = 1;
let isTerminator = 1;
@@ -1551,7 +1545,7 @@ class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
class CBranchZeroLikely<string opstr, DAGOperand opnd, RegisterOperand RO> :
InstSE<(outs), (ins RO:$rs, opnd:$offset),
- !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZ, FrmI, opstr> {
+ !strconcat(opstr, "\t$rs, $offset"), [], FrmI, opstr> {
let isBranch = 1;
let isTerminator = 1;
let hasDelaySlot = 1;
@@ -1564,20 +1558,20 @@ class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
!strconcat(opstr, "\t$rd, $rs, $rt"),
[(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
- II_SLT_SLTU, FrmR, opstr>;
+ FrmR, opstr>;
class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
RegisterOperand RO>:
InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
!strconcat(opstr, "\t$rt, $rs, $imm16"),
[(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
- II_SLTI_SLTIU, FrmI, opstr>;
+ FrmI, opstr>;
// Jump
class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
SDPatternOperator targetoperator, string bopstr> :
InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
- [(operator targetoperator:$target)], II_J, FrmJ, bopstr> {
+ [(operator targetoperator:$target)], FrmJ, bopstr> {
let isTerminator=1;
let isBarrier=1;
let hasDelaySlot = 1;
@@ -1588,7 +1582,7 @@ class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
// Unconditional branch
class UncondBranch<Instruction BEQInst, DAGOperand opnd> :
- PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], II_B>,
+ PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)]>,
PseudoInstExpansion<(BEQInst ZERO, ZERO, opnd:$offset)> {
let isBranch = 1;
let isTerminator = 1;
@@ -1603,7 +1597,7 @@ class UncondBranch<Instruction BEQInst, DAGOperand opnd> :
let isTerminator=1, isBarrier=1, hasDelaySlot = 1, isCTI = 1 in
class JumpFR<string opstr, RegisterOperand RO,
SDPatternOperator operator = null_frag>:
- InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], II_JR,
+ InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)],
FrmR, opstr>;
// Indirect branch
@@ -1616,27 +1610,27 @@ class IndirectBranch<string opstr, RegisterOperand RO> : JumpFR<opstr, RO> {
let isCall=1, hasDelaySlot=1, isCTI=1, Defs = [RA] in {
class JumpLink<string opstr, DAGOperand opnd> :
InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
- [(MipsJmpLink tglobaladdr:$target)], II_JAL, FrmJ, opstr> {
+ [(MipsJmpLink tglobaladdr:$target)], FrmJ, opstr> {
let DecoderMethod = "DecodeJumpTarget";
}
class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
Register RetReg, RegisterOperand ResRO = RO>:
- PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], II_JALR>,
+ PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)]>,
PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)> {
let hasPostISelHook = 1;
}
class JumpLinkReg<string opstr, RegisterOperand RO>:
InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
- [], II_JALR, FrmR, opstr> {
+ [], FrmR, opstr> {
let hasPostISelHook = 1;
}
class BGEZAL_FT<string opstr, DAGOperand opnd,
RegisterOperand RO> :
InstSE<(outs), (ins RO:$rs, opnd:$offset),
- !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZAL, FrmI, opstr> {
+ !strconcat(opstr, "\t$rs, $offset"), [], FrmI, opstr> {
let hasDelaySlot = 1;
}
@@ -1645,18 +1639,18 @@ let isCall=1, hasDelaySlot=1, isCTI=1, Defs = [RA] in {
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
hasExtraSrcRegAllocReq = 1, isCTI = 1, Defs = [AT] in {
class TailCall<Instruction JumpInst, DAGOperand Opnd> :
- PseudoSE<(outs), (ins calltarget:$target), [], II_J>,
+ PseudoSE<(outs), (ins calltarget:$target), []>,
PseudoInstExpansion<(JumpInst Opnd:$target)>;
class TailCallReg<Instruction JumpInst, RegisterOperand RO> :
- PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>,
+ PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)]>,
PseudoInstExpansion<(JumpInst RO:$rs)> {
let hasPostISelHook = 1;
}
}
class BAL_BR_Pseudo<Instruction RealInst, DAGOperand opnd> :
- PseudoSE<(outs), (ins opnd:$offset), [], II_BCCZAL>,
+ PseudoSE<(outs), (ins opnd:$offset), []>,
PseudoInstExpansion<(RealInst ZERO, opnd:$offset)> {
let isBranch = 1;
let isTerminator = 1;
@@ -1668,61 +1662,58 @@ class BAL_BR_Pseudo<Instruction RealInst, DAGOperand opnd> :
let isCTI = 1 in {
// Syscall
-class SYS_FT<string opstr, Operand ImmOp, InstrItinClass itin = NoItinerary> :
+class SYS_FT<string opstr, Operand ImmOp> :
InstSE<(outs), (ins ImmOp:$code_),
- !strconcat(opstr, "\t$code_"), [], itin, FrmI, opstr>;
+ !strconcat(opstr, "\t$code_"), [], FrmI, opstr>;
// Break
class BRK_FT<string opstr> :
InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
- !strconcat(opstr, "\t$code_1, $code_2"), [], II_BREAK,
+ !strconcat(opstr, "\t$code_1, $code_2"), [],
FrmOther, opstr>;
// (D)Eret
-class ER_FT<string opstr, InstrItinClass itin = NoItinerary> :
+class ER_FT<string opstr> :
InstSE<(outs), (ins),
- opstr, [], itin, FrmOther, opstr>;
+ opstr, [], FrmOther, opstr>;
// Wait
class WAIT_FT<string opstr> :
- InstSE<(outs), (ins), opstr, [], II_WAIT, FrmOther, opstr>;
+ InstSE<(outs), (ins), opstr, [], FrmOther, opstr>;
}
// Interrupts
-class DEI_FT<string opstr, RegisterOperand RO,
- InstrItinClass itin = NoItinerary> :
+class DEI_FT<string opstr, RegisterOperand RO> :
InstSE<(outs RO:$rt), (ins),
- !strconcat(opstr, "\t$rt"), [], itin, FrmOther, opstr>;
+ !strconcat(opstr, "\t$rt"), [], FrmOther, opstr>;
// Sync
let hasSideEffects = 1 in
class SYNC_FT<string opstr> :
InstSE<(outs), (ins uimm5:$stype), "sync $stype",
- [(MipsSync timmZExt5:$stype)], II_SYNC, FrmOther, opstr>;
+ [(MipsSync timmZExt5:$stype)], FrmOther, opstr>;
class SYNCI_FT<string opstr, DAGOperand MO> :
InstSE<(outs), (ins MO:$addr), !strconcat(opstr, "\t$addr"), [],
- II_SYNCI, FrmOther, opstr> {
+ FrmOther, opstr> {
let hasSideEffects = 1;
let DecoderMethod = "DecodeSyncI";
}
let hasSideEffects = 1, isCTI = 1 in {
-class TEQ_FT<string opstr, RegisterOperand RO, Operand ImmOp,
- InstrItinClass itin = NoItinerary> :
+class TEQ_FT<string opstr, RegisterOperand RO, Operand ImmOp> :
InstSE<(outs), (ins RO:$rs, RO:$rt, ImmOp:$code_),
- !strconcat(opstr, "\t$rs, $rt, $code_"), [], itin, FrmI, opstr>;
+ !strconcat(opstr, "\t$rs, $rt, $code_"), [], FrmI, opstr>;
-class TEQI_FT<string opstr, RegisterOperand RO,
- InstrItinClass itin = NoItinerary> :
+class TEQI_FT<string opstr, RegisterOperand RO> :
InstSE<(outs), (ins RO:$rs, simm16:$imm16),
- !strconcat(opstr, "\t$rs, $imm16"), [], itin, FrmOther, opstr>;
+ !strconcat(opstr, "\t$rs, $imm16"), [], FrmOther, opstr>;
}
// Mul, Div
-class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
+class Mult<string opstr, RegisterOperand RO,
list<Register> DefRegs> :
InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
- itin, FrmR, opstr> {
+ FrmR, opstr> {
let isCommutable = 1;
let Defs = DefRegs;
let hasSideEffects = 0;
@@ -1731,11 +1722,11 @@ class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
// Pseudo multiply/divide instruction with explicit accumulator register
// operands.
class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
- SDPatternOperator OpNode, InstrItinClass Itin,
+ SDPatternOperator OpNode,
bit IsComm = 1, bit HasSideEffects = 0,
bit UsesCustomInserter = 0> :
PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
- [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
+ [(set R0:$ac, (OpNode R1:$rs, R1:$rt))]>,
PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
let isCommutable = IsComm;
let hasSideEffects = HasSideEffects;
@@ -1744,31 +1735,29 @@ class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
// Pseudo multiply add/sub instruction with explicit accumulator register
// operands.
-class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
- InstrItinClass itin>
+class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode>
: PseudoSE<(outs ACC64:$ac),
(ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
[(set ACC64:$ac,
- (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
- itin>,
+ (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))]>,
PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
string Constraints = "$acin = $ac";
}
-class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
+class Div<string opstr, RegisterOperand RO,
list<Register> DefRegs> :
InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
- [], itin, FrmR, opstr> {
+ [], FrmR, opstr> {
let Defs = DefRegs;
}
// Move from Hi/Lo
class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
: PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
- [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
+ [(set DstRC:$rd, (OpNode SrcRC:$hilo))]>;
class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
- InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
+ InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [],
FrmR, opstr> {
let Uses = [UseReg];
let hasSideEffects = 0;
@@ -1777,11 +1766,10 @@ class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
: PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
- [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
- II_MTHI_MTLO>;
+ [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))]>;
class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
- InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
+ InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [],
FrmR, opstr> {
let Defs = DefRegs;
let hasSideEffects = 0;
@@ -1790,7 +1778,7 @@ class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
class EffectiveAddress<string opstr, RegisterOperand RO> :
InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
- [(set RO:$rt, addr:$addr)], II_ADDIU, FrmI,
+ [(set RO:$rt, addr:$addr)], FrmI,
!strconcat(opstr, "_lea")> {
let isCodeGenOnly = 1;
let hasNoSchedulingInfo = 1;
@@ -1798,26 +1786,22 @@ class EffectiveAddress<string opstr, RegisterOperand RO> :
}
// Count Leading Ones/Zeros in Word
-class CountLeading0<string opstr, RegisterOperand RO,
- InstrItinClass itin = NoItinerary>:
+class CountLeading0<string opstr, RegisterOperand RO>:
InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
- [(set RO:$rd, (ctlz RO:$rs))], itin, FrmR, opstr>;
+ [(set RO:$rd, (ctlz RO:$rs))], FrmR, opstr>;
-class CountLeading1<string opstr, RegisterOperand RO,
- InstrItinClass itin = NoItinerary>:
+class CountLeading1<string opstr, RegisterOperand RO>:
InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
- [(set RO:$rd, (ctlz (not RO:$rs)))], itin, FrmR, opstr>;
+ [(set RO:$rd, (ctlz (not RO:$rs)))], FrmR, opstr>;
// Sign Extend in Register.
-class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
- InstrItinClass itin> :
+class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO> :
InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
- [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>;
+ [(set RO:$rd, (sext_inreg RO:$rt, vt))], FrmR, opstr>;
// Subword Swap
-class SubwordSwap<string opstr, RegisterOperand RO,
- InstrItinClass itin = NoItinerary>:
- InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], itin,
+class SubwordSwap<string opstr, RegisterOperand RO>:
+ InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
FrmR, opstr> {
let hasSideEffects = 0;
}
@@ -1825,7 +1809,7 @@ class SubwordSwap<string opstr, RegisterOperand RO,
// Read Hardware
class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
InstSE<(outs CPURegOperand:$rt), (ins RO:$rd, uimm8:$sel),
- "rdhwr\t$rt, $rd, $sel", [], II_RDHWR, FrmR, "rdhwr">;
+ "rdhwr\t$rt, $rd, $sel", [], FrmR, "rdhwr">;
// Ext and Ins
class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
@@ -1833,7 +1817,7 @@ class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
SDPatternOperator Op = null_frag> :
InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size),
!strconcat(opstr, "\t$rt, $rs, $pos, $size"),
- [(set RO:$rt, (Op RO:$rs, PosImm:$pos, SizeImm:$size))], II_EXT,
+ [(set RO:$rt, (Op RO:$rs, PosImm:$pos, SizeImm:$size))],
FrmR, opstr>;
// 'ins' and its 64 bit variants are matched by C++ code.
@@ -1843,7 +1827,7 @@ class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
!strconcat(opstr, "\t$rt, $rs, $pos, $size"),
[(set RO:$rt, (null_frag RO:$rs, PosImm:$pos, SizeImm:$size,
RO:$src))],
- II_INS, FrmR, opstr> {
+ FrmR, opstr> {
let Constraints = "$src = $rt";
}
@@ -1894,35 +1878,33 @@ class AtomicCmpSwapSubwordPostRA<RegisterClass RC> :
class LLBase<string opstr, RegisterOperand RO, DAGOperand MO = mem> :
InstSE<(outs RO:$rt), (ins MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
- [], II_LL, FrmI, opstr> {
+ [], FrmI, opstr> {
let DecoderMethod = "DecodeMem";
let mayLoad = 1;
}
class SCBase<string opstr, RegisterOperand RO> :
InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
- !strconcat(opstr, "\t$rt, $addr"), [], II_SC, FrmI> {
+ !strconcat(opstr, "\t$rt, $addr"), [], FrmI> {
let DecoderMethod = "DecodeMem";
let mayStore = 1;
let Constraints = "$rt = $dst";
}
-class MFC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD,
- InstrItinClass itin> :
+class MFC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD> :
InstSE<(outs RO:$rt), (ins RD:$rd, uimm3:$sel),
- !strconcat(asmstr, "\t$rt, $rd, $sel"), [], itin, FrmFR> {
+ !strconcat(asmstr, "\t$rt, $rd, $sel"), [], FrmFR> {
let BaseOpcode = asmstr;
}
-class MTC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD,
- InstrItinClass itin> :
+class MTC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD> :
InstSE<(outs RO:$rd), (ins RD:$rt, uimm3:$sel),
- !strconcat(asmstr, "\t$rt, $rd, $sel"), [], itin, FrmFR> {
+ !strconcat(asmstr, "\t$rt, $rd, $sel"), [], FrmFR> {
let BaseOpcode = asmstr;
}
class TrapBase<Instruction RealInst>
- : PseudoSE<(outs), (ins), [(trap)], II_TRAP>,
+ : PseudoSE<(outs), (ins), [(trap)]>,
PseudoInstExpansion<(RealInst 0, 0)> {
let mayStore = 0;
let mayLoad = 0;
@@ -2075,19 +2057,19 @@ def LONG_BRANCH_ADDiu2Op : PseudoSE<(outs GPR32Opnd:$dst),
/// Arithmetic Instructions (ALU Immediate)
let AdditionalPredicates = [NotInMicroMips] in {
def ADDiu : MMRel, StdMMR6Rel, ArithLogicI<"addiu", simm16_relaxed, GPR32Opnd,
- II_ADDIU, imm32SExt16, add>,
+ imm32SExt16, add>,
ADDI_FM<0x9>, IsAsCheapAsAMove, ISA_MIPS1;
def ANDi : MMRel, StdMMR6Rel,
- ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, imm32ZExt16, and>,
+ ArithLogicI<"andi", uimm16, GPR32Opnd, imm32ZExt16, and>,
ADDI_FM<0xc>, ISA_MIPS1;
def ORi : MMRel, StdMMR6Rel,
- ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, imm32ZExt16, or>,
+ ArithLogicI<"ori", uimm16, GPR32Opnd, imm32ZExt16, or>,
ADDI_FM<0xd>, ISA_MIPS1;
def XORi : MMRel, StdMMR6Rel,
- ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, imm32ZExt16, xor>,
+ ArithLogicI<"xori", uimm16, GPR32Opnd, imm32ZExt16, xor>,
ADDI_FM<0xe>, ISA_MIPS1;
- def ADDi : MMRel, ArithLogicI<"addi", simm16_relaxed, GPR32Opnd, II_ADDI>,
+ def ADDi : MMRel, ArithLogicI<"addi", simm16_relaxed, GPR32Opnd>,
ADDI_FM<0x8>, ISA_MIPS1_NOT_32R6_64R6;
def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
SLTI_FM<0xa>, ISA_MIPS1;
@@ -2098,29 +2080,29 @@ let AdditionalPredicates = [NotInMicroMips] in {
ISA_MIPS1;
/// Arithmetic Instructions (3-Operand, R-Type)
- def ADDu : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
+ def ADDu : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, add>,
ADD_FM<0, 0x21>, ISA_MIPS1;
- def SUBu : MMRel, StdMMR6Rel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
+ def SUBu : MMRel, StdMMR6Rel, ArithLogicR<"subu", GPR32Opnd, 0, sub>,
ADD_FM<0, 0x23>, ISA_MIPS1;
let Defs = [HI0, LO0] in
- def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
+ def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, mul>,
ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
- def ADD : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd, 1, II_ADD>,
+ def ADD : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd, 1>,
ADD_FM<0, 0x20>, ISA_MIPS1;
- def SUB : MMRel, StdMMR6Rel, ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>,
+ def SUB : MMRel, StdMMR6Rel, ArithLogicR<"sub", GPR32Opnd, 0>,
ADD_FM<0, 0x22>, ISA_MIPS1;
def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>,
ISA_MIPS1;
def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>,
ISA_MIPS1;
- def AND : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
+ def AND : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, and>,
ADD_FM<0, 0x24>, ISA_MIPS1;
- def OR : MMRel, StdMMR6Rel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
+ def OR : MMRel, StdMMR6Rel, ArithLogicR<"or", GPR32Opnd, 1, or>,
ADD_FM<0, 0x25>, ISA_MIPS1;
- def XOR : MMRel, StdMMR6Rel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
+ def XOR : MMRel, StdMMR6Rel, ArithLogicR<"xor", GPR32Opnd, 1, xor>,
ADD_FM<0, 0x26>, ISA_MIPS1;
def NOR : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>,
ISA_MIPS1;
@@ -2128,84 +2110,84 @@ let AdditionalPredicates = [NotInMicroMips] in {
let AdditionalPredicates = [NotInMicroMips] in {
/// Shift Instructions
- def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, mshl_32,
+ def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, mshl_32,
immZExt5>, SRA_FM<0, 0>, ISA_MIPS1;
- def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, msrl_32,
+ def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, msrl_32,
immZExt5>, SRA_FM<2, 0>, ISA_MIPS1;
- def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, msra_32,
+ def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, msra_32,
immZExt5>, SRA_FM<3, 0>, ISA_MIPS1;
- def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, mshl_32>,
+ def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, mshl_32>,
SRLV_FM<4, 0>, ISA_MIPS1;
- def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, msrl_32>,
+ def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, msrl_32>,
SRLV_FM<6, 0>, ISA_MIPS1;
- def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, msra_32>,
+ def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, msra_32>,
SRLV_FM<7, 0>, ISA_MIPS1;
// Rotate Instructions
- def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
+ def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, rotr,
immZExt5>,
SRA_FM<2, 1>, ISA_MIPS32R2;
- def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
+ def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, rotr>,
SRLV_FM<6, 1>, ISA_MIPS32R2;
}
/// Load and Store Instructions
/// aligned
let AdditionalPredicates = [NotInMicroMips] in {
- def LB : LoadMemory<"lb", GPR32Opnd, mem_simmptr, sextloadi8, II_LB>, MMRel,
+ def LB : LoadMemory<"lb", GPR32Opnd, mem_simmptr, sextloadi8>, MMRel,
LW_FM<0x20>, ISA_MIPS1;
- def LBu : LoadMemory<"lbu", GPR32Opnd, mem_simmptr, zextloadi8, II_LBU,
+ def LBu : LoadMemory<"lbu", GPR32Opnd, mem_simmptr, zextloadi8,
addrDefault>, MMRel, LW_FM<0x24>, ISA_MIPS1;
- def LH : LoadMemory<"lh", GPR32Opnd, mem_simmptr, sextloadi16, II_LH,
+ def LH : LoadMemory<"lh", GPR32Opnd, mem_simmptr, sextloadi16,
addrDefault>, MMRel, LW_FM<0x21>, ISA_MIPS1;
- def LHu : LoadMemory<"lhu", GPR32Opnd, mem_simmptr, zextloadi16, II_LHU>,
+ def LHu : LoadMemory<"lhu", GPR32Opnd, mem_simmptr, zextloadi16>,
MMRel, LW_FM<0x25>, ISA_MIPS1;
- def LW : StdMMR6Rel, Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
+ def LW : StdMMR6Rel, Load<"lw", GPR32Opnd, load, addrDefault>, MMRel,
LW_FM<0x23>, ISA_MIPS1;
- def SB : StdMMR6Rel, Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel,
+ def SB : StdMMR6Rel, Store<"sb", GPR32Opnd, truncstorei8>, MMRel,
LW_FM<0x28>, ISA_MIPS1;
- def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>,
+ def SH : Store<"sh", GPR32Opnd, truncstorei16>, MMRel, LW_FM<0x29>,
ISA_MIPS1;
- def SW : StdMMR6Rel, Store<"sw", GPR32Opnd, store, II_SW>,
+ def SW : StdMMR6Rel, Store<"sw", GPR32Opnd, store>,
MMRel, LW_FM<0x2b>, ISA_MIPS1;
}
/// load/store left/right
let AdditionalPredicates = [NotInMicroMips] in {
-def LWL : MMRel, LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>,
+def LWL : MMRel, LoadLeftRight<"lwl", MipsLWL, GPR32Opnd>, LW_FM<0x22>,
ISA_MIPS1_NOT_32R6_64R6;
-def LWR : MMRel, LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>,
+def LWR : MMRel, LoadLeftRight<"lwr", MipsLWR, GPR32Opnd>, LW_FM<0x26>,
ISA_MIPS1_NOT_32R6_64R6;
-def SWL : MMRel, StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>,
+def SWL : MMRel, StoreLeftRight<"swl", MipsSWL, GPR32Opnd>, LW_FM<0x2a>,
ISA_MIPS1_NOT_32R6_64R6;
-def SWR : MMRel, StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>,
+def SWR : MMRel, StoreLeftRight<"swr", MipsSWR, GPR32Opnd>, LW_FM<0x2e>,
ISA_MIPS1_NOT_32R6_64R6;
// COP2 Memory Instructions
-def LWC2 : StdMMR6Rel, LW_FT2<"lwc2", COP2Opnd, II_LWC2, load>, LW_FM<0x32>,
+def LWC2 : StdMMR6Rel, LW_FT2<"lwc2", COP2Opnd, load>, LW_FM<0x32>,
ISA_MIPS1_NOT_32R6_64R6;
-def SWC2 : StdMMR6Rel, SW_FT2<"swc2", COP2Opnd, II_SWC2, store>,
+def SWC2 : StdMMR6Rel, SW_FT2<"swc2", COP2Opnd, store>,
LW_FM<0x3a>, ISA_MIPS1_NOT_32R6_64R6;
-def LDC2 : StdMMR6Rel, LW_FT2<"ldc2", COP2Opnd, II_LDC2, load>, LW_FM<0x36>,
+def LDC2 : StdMMR6Rel, LW_FT2<"ldc2", COP2Opnd, load>, LW_FM<0x36>,
ISA_MIPS2_NOT_32R6_64R6;
-def SDC2 : StdMMR6Rel, SW_FT2<"sdc2", COP2Opnd, II_SDC2, store>,
+def SDC2 : StdMMR6Rel, SW_FT2<"sdc2", COP2Opnd, store>,
LW_FM<0x3e>, ISA_MIPS2_NOT_32R6_64R6;
// COP3 Memory Instructions
let DecoderNamespace = "COP3_" in {
- def LWC3 : LW_FT3<"lwc3", COP3Opnd, II_LWC3, load>,
+ def LWC3 : LW_FT3<"lwc3", COP3Opnd, load>,
LW_FM<0x33>,
ISA_MIPS1_NOT_32R6_64R6_R5900,
NOT_ASE_CNMIPS;
- def SWC3 : SW_FT3<"swc3", COP3Opnd, II_SWC3, store>,
+ def SWC3 : SW_FT3<"swc3", COP3Opnd, store>,
LW_FM<0x3b>,
ISA_MIPS1_NOT_32R6_64R6_R5900,
NOT_ASE_CNMIPS;
- def LDC3 : LW_FT3<"ldc3", COP3Opnd, II_LDC3, load>,
+ def LDC3 : LW_FT3<"ldc3", COP3Opnd, load>,
LW_FM<0x37>,
ISA_MIPS2_NOT_R5900,
NOT_ASE_CNMIPS;
- def SDC3 : SW_FT3<"sdc3", COP3Opnd, II_SDC3, store>,
+ def SDC3 : SW_FT3<"sdc3", COP3Opnd, store>,
LW_FM<0x3f>,
ISA_MIPS2_NOT_R5900,
NOT_ASE_CNMIPS;
@@ -2217,49 +2199,49 @@ let DecoderNamespace = "COP3_" in {
}
let AdditionalPredicates = [NotInMicroMips] in {
- def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd, uimm10, II_TEQ>, TEQ_FM<0x34>,
+ def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd, uimm10>, TEQ_FM<0x34>,
ISA_MIPS2;
- def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd, uimm10, II_TGE>, TEQ_FM<0x30>,
+ def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd, uimm10>, TEQ_FM<0x30>,
ISA_MIPS2;
- def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd, uimm10, II_TGEU>, TEQ_FM<0x31>,
+ def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd, uimm10>, TEQ_FM<0x31>,
ISA_MIPS2;
- def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd, uimm10, II_TLT>, TEQ_FM<0x32>,
+ def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd, uimm10>, TEQ_FM<0x32>,
ISA_MIPS2;
- def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd, uimm10, II_TLTU>, TEQ_FM<0x33>,
+ def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd, uimm10>, TEQ_FM<0x33>,
ISA_MIPS2;
- def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd, uimm10, II_TNE>, TEQ_FM<0x36>,
+ def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd, uimm10>, TEQ_FM<0x36>,
ISA_MIPS2;
- def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd, II_TEQI>, TEQI_FM<0xc>,
+ def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>,
ISA_MIPS2_NOT_32R6_64R6;
- def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd, II_TGEI>, TEQI_FM<0x8>,
+ def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>,
ISA_MIPS2_NOT_32R6_64R6;
- def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd, II_TGEIU>, TEQI_FM<0x9>,
+ def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>,
ISA_MIPS2_NOT_32R6_64R6;
- def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd, II_TLTI>, TEQI_FM<0xa>,
+ def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>,
ISA_MIPS2_NOT_32R6_64R6;
- def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd, II_TTLTIU>, TEQI_FM<0xb>,
+ def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>,
ISA_MIPS2_NOT_32R6_64R6;
- def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd, II_TNEI>, TEQI_FM<0xe>,
+ def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>,
ISA_MIPS2_NOT_32R6_64R6;
}
let AdditionalPredicates = [NotInMicroMips] in {
def BREAK : MMRel, StdMMR6Rel, BRK_FT<"break">, BRK_FM<0xd>, ISA_MIPS1;
- def SYSCALL : MMRel, SYS_FT<"syscall", uimm20, II_SYSCALL>, SYS_FM<0xc>,
+ def SYSCALL : MMRel, SYS_FT<"syscall", uimm20>, SYS_FM<0xc>,
ISA_MIPS1;
def TRAP : TrapBase<BREAK>, ISA_MIPS1;
- def SDBBP : MMRel, SYS_FT<"sdbbp", uimm20, II_SDBBP>, SDBBP_FM,
+ def SDBBP : MMRel, SYS_FT<"sdbbp", uimm20>, SDBBP_FM,
ISA_MIPS32_NOT_32R6_64R6;
- def ERET : MMRel, ER_FT<"eret", II_ERET>, ER_FM<0x18, 0x0>, INSN_MIPS3_32;
- def ERETNC : MMRel, ER_FT<"eretnc", II_ERETNC>, ER_FM<0x18, 0x1>,
+ def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18, 0x0>, INSN_MIPS3_32;
+ def ERETNC : MMRel, ER_FT<"eretnc">, ER_FM<0x18, 0x1>,
ISA_MIPS32R5;
- def DERET : MMRel, ER_FT<"deret", II_DERET>, ER_FM<0x1f, 0x0>, ISA_MIPS32;
+ def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f, 0x0>, ISA_MIPS32;
- def EI : MMRel, StdMMR6Rel, DEI_FT<"ei", GPR32Opnd, II_EI>, EI_FM<1>,
+ def EI : MMRel, StdMMR6Rel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>,
ISA_MIPS32R2;
- def DI : MMRel, StdMMR6Rel, DEI_FT<"di", GPR32Opnd, II_DI>, EI_FM<0>,
+ def DI : MMRel, StdMMR6Rel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>,
ISA_MIPS32R2;
def WAIT : MMRel, StdMMR6Rel, WAIT_FT<"wait">, WAIT_FM, INSN_MIPS3_32;
@@ -2342,8 +2324,7 @@ let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,
// Indirect branches are matched as PseudoIndirectBranch/PseudoIndirectBranch64
// then are expanded to JR, JR64, JALR, or JALR64 depending on the ISA.
class PseudoIndirectBranchBase<Instruction JumpInst, RegisterOperand RO> :
- MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)],
- II_IndirectBranchPseudo>,
+ MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)]>,
PseudoInstExpansion<(JumpInst RO:$rs)> {
let isTerminator=1;
let isBarrier=1;
@@ -2363,7 +2344,7 @@ let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,
// MipsAsmPrinter expands this into JR, JR64, JALR, or JALR64 depending on the
// ISA.
class PseudoReturnBase<RegisterOperand RO> : MipsPseudo<(outs), (ins RO:$rs),
- [], II_ReturnPseudo> {
+ []> {
let isTerminator = 1;
let isBarrier = 1;
let hasDelaySlot = 1;
@@ -2400,13 +2381,13 @@ let Uses = [V0, V1], isTerminator = 1, isReturn = 1,
/// Multiply and Divide Instructions.
let AdditionalPredicates = [NotInMicroMips] in {
- def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
+ def MULT : MMRel, Mult<"mult", GPR32Opnd, [HI0, LO0]>,
MULT_FM<0, 0x18>, ISA_MIPS1_NOT_32R6_64R6;
- def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
+ def MULTu : MMRel, Mult<"multu", GPR32Opnd, [HI0, LO0]>,
MULT_FM<0, 0x19>, ISA_MIPS1_NOT_32R6_64R6;
- def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
+ def SDIV : MMRel, Div<"div", GPR32Opnd, [HI0, LO0]>,
MULT_FM<0, 0x1a>, ISA_MIPS1_NOT_32R6_64R6;
- def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
+ def UDIV : MMRel, Div<"divu", GPR32Opnd, [HI0, LO0]>,
MULT_FM<0, 0x1b>, ISA_MIPS1_NOT_32R6_64R6;
def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>,
ISA_MIPS1_NOT_32R6_64R6;
@@ -2418,19 +2399,19 @@ let AdditionalPredicates = [NotInMicroMips] in {
ISA_MIPS1_NOT_32R6_64R6;
/// Sign Ext In Register Instructions.
- def SEB : MMRel, StdMMR6Rel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
+ def SEB : MMRel, StdMMR6Rel, SignExtInReg<"seb", i8, GPR32Opnd>,
SEB_FM<0x10, 0x20>, ISA_MIPS32R2;
- def SEH : MMRel, StdMMR6Rel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
+ def SEH : MMRel, StdMMR6Rel, SignExtInReg<"seh", i16, GPR32Opnd>,
SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
/// Count Leading
- def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd, II_CLZ>, CLO_FM<0x20>,
+ def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>,
ISA_MIPS32_NOT_32R6_64R6;
- def CLO : MMRel, CountLeading1<"clo", GPR32Opnd, II_CLO>, CLO_FM<0x21>,
+ def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>,
ISA_MIPS32_NOT_32R6_64R6;
/// Word Swap Bytes Within Halfwords
- def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>, SEB_FM<2, 0x20>,
+ def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>,
ISA_MIPS32R2;
/// No operation.
@@ -2446,38 +2427,38 @@ let AdditionalPredicates = [NotInMicroMips] in {
ISA_MIPS1;
// MADD*/MSUB*
- def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,
+ def MADD : MMRel, MArithR<"madd", 1>, MULT_FM<0x1c, 0>,
ISA_MIPS32_NOT_32R6_64R6;
- def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>,
+ def MADDU : MMRel, MArithR<"maddu", 1>, MULT_FM<0x1c, 1>,
ISA_MIPS32_NOT_32R6_64R6;
- def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>,
+ def MSUB : MMRel, MArithR<"msub">, MULT_FM<0x1c, 4>,
ISA_MIPS32_NOT_32R6_64R6;
- def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>,
+ def MSUBU : MMRel, MArithR<"msubu">, MULT_FM<0x1c, 5>,
ISA_MIPS32_NOT_32R6_64R6;
}
let AdditionalPredicates = [NotDSP] in {
-def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>,
+def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult>,
ISA_MIPS1_NOT_32R6_64R6;
-def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>,
+def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu>,
ISA_MIPS1_NOT_32R6_64R6;
def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>, ISA_MIPS1_NOT_32R6_64R6;
def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>, ISA_MIPS1_NOT_32R6_64R6;
def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>, ISA_MIPS1_NOT_32R6_64R6;
-def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,
+def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd>,
ISA_MIPS32_NOT_32R6_64R6;
-def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>,
+def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>,
ISA_MIPS32_NOT_32R6_64R6;
-def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>,
+def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub>,
ISA_MIPS32_NOT_32R6_64R6;
-def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>,
+def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu>,
ISA_MIPS32_NOT_32R6_64R6;
}
let AdditionalPredicates = [NotInMicroMips] in {
- def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
+ def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem,
0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
- def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
+ def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU,
0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
def RDHWR : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM, ISA_MIPS1;
// TODO: Add '0 < pos+size <= 32' constraint check to ext instruction
@@ -2491,25 +2472,25 @@ let AdditionalPredicates = [NotInMicroMips] in {
}
/// Move Control Registers From/To CPU Registers
let AdditionalPredicates = [NotInMicroMips] in {
- def MTC0 : MTC3OP<"mtc0", COP0Opnd, GPR32Opnd, II_MTC0>,
+ def MTC0 : MTC3OP<"mtc0", COP0Opnd, GPR32Opnd>,
MFC3OP_FM<0x10, 4, 0>, ISA_MIPS1;
- def MFC0 : MFC3OP<"mfc0", GPR32Opnd, COP0Opnd, II_MFC0>,
+ def MFC0 : MFC3OP<"mfc0", GPR32Opnd, COP0Opnd>,
MFC3OP_FM<0x10, 0, 0>, ISA_MIPS1;
- def MFC2 : MFC3OP<"mfc2", GPR32Opnd, COP2Opnd, II_MFC2>,
+ def MFC2 : MFC3OP<"mfc2", GPR32Opnd, COP2Opnd>,
MFC3OP_FM<0x12, 0, 0>, ISA_MIPS1;
- def MTC2 : MTC3OP<"mtc2", COP2Opnd, GPR32Opnd, II_MTC2>,
+ def MTC2 : MTC3OP<"mtc2", COP2Opnd, GPR32Opnd>,
MFC3OP_FM<0x12, 4, 0>, ISA_MIPS1;
}
-class Barrier<string asmstr, InstrItinClass itin = NoItinerary> :
- InstSE<(outs), (ins), asmstr, [], itin, FrmOther, asmstr>;
+class Barrier<string asmstr> :
+ InstSE<(outs), (ins), asmstr, [], FrmOther, asmstr>;
let AdditionalPredicates = [NotInMicroMips] in {
- def SSNOP : MMRel, StdMMR6Rel, Barrier<"ssnop", II_SSNOP>, BARRIER_FM<1>,
+ def SSNOP : MMRel, StdMMR6Rel, Barrier<"ssnop">, BARRIER_FM<1>,
ISA_MIPS1;
- def EHB : MMRel, Barrier<"ehb", II_EHB>, BARRIER_FM<3>, ISA_MIPS1;
+ def EHB : MMRel, Barrier<"ehb">, BARRIER_FM<3>, ISA_MIPS1;
let isCTI = 1 in
- def PAUSE : MMRel, StdMMR6Rel, Barrier<"pause", II_PAUSE>, BARRIER_FM<5>,
+ def PAUSE : MMRel, StdMMR6Rel, Barrier<"pause">, BARRIER_FM<5>,
ISA_MIPS32R2;
}
@@ -2533,7 +2514,7 @@ class JALR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
}
class JR_HB_DESC<RegisterOperand RO> :
- InstSE<(outs), (ins), "", [], II_JR_HB, FrmJ>, JR_HB_DESC_BASE<"jr.hb", RO> {
+ InstSE<(outs), (ins), "", [], FrmJ>, JR_HB_DESC_BASE<"jr.hb", RO> {
let isBranch=1;
let isIndirectBranch=1;
let hasDelaySlot=1;
@@ -2543,7 +2524,7 @@ class JR_HB_DESC<RegisterOperand RO> :
}
class JALR_HB_DESC<RegisterOperand RO> :
- InstSE<(outs), (ins), "", [], II_JALR_HB, FrmJ>, JALR_HB_DESC_BASE<"jalr.hb",
+ InstSE<(outs), (ins), "", [], FrmJ>, JALR_HB_DESC_BASE<"jalr.hb",
RO> {
let isIndirectBranch=1;
let hasDelaySlot=1;
@@ -2567,26 +2548,25 @@ let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,
ISA_MIPS32R2_NOT_32R6_64R6;
}
-class TLB<string asmstr, InstrItinClass itin = NoItinerary> :
- InstSE<(outs), (ins), asmstr, [], itin, FrmOther, asmstr>;
+class TLB<string asmstr> :
+ InstSE<(outs), (ins), asmstr, [], FrmOther, asmstr>;
let AdditionalPredicates = [NotInMicroMips] in {
- def TLBP : MMRel, TLB<"tlbp", II_TLBP>, COP0_TLB_FM<0x08>, ISA_MIPS1;
- def TLBR : MMRel, TLB<"tlbr", II_TLBR>, COP0_TLB_FM<0x01>, ISA_MIPS1;
- def TLBWI : MMRel, TLB<"tlbwi", II_TLBWI>, COP0_TLB_FM<0x02>, ISA_MIPS1;
- def TLBWR : MMRel, TLB<"tlbwr", II_TLBWR>, COP0_TLB_FM<0x06>, ISA_MIPS1;
+ def TLBP : MMRel, TLB<"tlbp">, COP0_TLB_FM<0x08>, ISA_MIPS1;
+ def TLBR : MMRel, TLB<"tlbr">, COP0_TLB_FM<0x01>, ISA_MIPS1;
+ def TLBWI : MMRel, TLB<"tlbwi">, COP0_TLB_FM<0x02>, ISA_MIPS1;
+ def TLBWR : MMRel, TLB<"tlbwr">, COP0_TLB_FM<0x06>, ISA_MIPS1;
}
-class CacheOp<string instr_asm, Operand MemOpnd,
- InstrItinClass itin = NoItinerary> :
+class CacheOp<string instr_asm, Operand MemOpnd> :
InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint),
- !strconcat(instr_asm, "\t$hint, $addr"), [], itin, FrmOther,
+ !strconcat(instr_asm, "\t$hint, $addr"), [], FrmOther,
instr_asm> {
let DecoderMethod = "DecodeCacheOp";
}
let AdditionalPredicates = [NotInMicroMips] in {
- def CACHE : MMRel, CacheOp<"cache", mem, II_CACHE>, CACHEOP_FM<0b101111>,
+ def CACHE : MMRel, CacheOp<"cache", mem>, CACHEOP_FM<0b101111>,
INSN_MIPS3_32_NOT_32R6_64R6;
- def PREF : MMRel, CacheOp<"pref", mem, II_PREF>, CACHEOP_FM<0b110011>,
+ def PREF : MMRel, CacheOp<"pref", mem>, CACHEOP_FM<0b110011>,
INSN_MIPS3_32_NOT_32R6_64R6;
}
// FIXME: We are missing the prefx instruction.
@@ -2689,30 +2669,30 @@ def MULOUMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rd, GPR32Opnd:$rs,
// Virtualization ASE
class HYPCALL_FT<string opstr> :
InstSE<(outs), (ins uimm10:$code_),
- !strconcat(opstr, "\t$code_"), [], II_HYPCALL, FrmOther, opstr> {
+ !strconcat(opstr, "\t$code_"), [], FrmOther, opstr> {
let BaseOpcode = opstr;
}
let AdditionalPredicates = [NotInMicroMips] in {
- def MFGC0 : MMRel, MFC3OP<"mfgc0", GPR32Opnd, COP0Opnd, II_MFGC0>,
+ def MFGC0 : MMRel, MFC3OP<"mfgc0", GPR32Opnd, COP0Opnd>,
MFC3OP_FM<0x10, 3, 0>, ISA_MIPS32R5, ASE_VIRT;
- def MTGC0 : MMRel, MTC3OP<"mtgc0", COP0Opnd, GPR32Opnd, II_MTGC0>,
+ def MTGC0 : MMRel, MTC3OP<"mtgc0", COP0Opnd, GPR32Opnd>,
MFC3OP_FM<0x10, 3, 2>, ISA_MIPS32R5, ASE_VIRT;
- def MFHGC0 : MMRel, MFC3OP<"mfhgc0", GPR32Opnd, COP0Opnd, II_MFHGC0>,
+ def MFHGC0 : MMRel, MFC3OP<"mfhgc0", GPR32Opnd, COP0Opnd>,
MFC3OP_FM<0x10, 3, 4>, ISA_MIPS32R5, ASE_VIRT;
- def MTHGC0 : MMRel, MTC3OP<"mthgc0", COP0Opnd, GPR32Opnd, II_MTHGC0>,
+ def MTHGC0 : MMRel, MTC3OP<"mthgc0", COP0Opnd, GPR32Opnd>,
MFC3OP_FM<0x10, 3, 6>, ISA_MIPS32R5, ASE_VIRT;
- def TLBGINV : MMRel, TLB<"tlbginv", II_TLBGINV>, COP0_TLB_FM<0b001011>,
+ def TLBGINV : MMRel, TLB<"tlbginv">, COP0_TLB_FM<0b001011>,
ISA_MIPS32R5, ASE_VIRT;
- def TLBGINVF : MMRel, TLB<"tlbginvf", II_TLBGINVF>, COP0_TLB_FM<0b001100>,
+ def TLBGINVF : MMRel, TLB<"tlbginvf">, COP0_TLB_FM<0b001100>,
ISA_MIPS32R5, ASE_VIRT;
- def TLBGP : MMRel, TLB<"tlbgp", II_TLBGP>, COP0_TLB_FM<0b010000>,
+ def TLBGP : MMRel, TLB<"tlbgp">, COP0_TLB_FM<0b010000>,
ISA_MIPS32R5, ASE_VIRT;
- def TLBGR : MMRel, TLB<"tlbgr", II_TLBGR>, COP0_TLB_FM<0b001001>,
+ def TLBGR : MMRel, TLB<"tlbgr">, COP0_TLB_FM<0b001001>,
ISA_MIPS32R5, ASE_VIRT;
- def TLBGWI : MMRel, TLB<"tlbgwi", II_TLBGWI>, COP0_TLB_FM<0b001010>,
+ def TLBGWI : MMRel, TLB<"tlbgwi">, COP0_TLB_FM<0b001010>,
ISA_MIPS32R5, ASE_VIRT;
- def TLBGWR : MMRel, TLB<"tlbgwr", II_TLBGWR>, COP0_TLB_FM<0b001110>,
+ def TLBGWR : MMRel, TLB<"tlbgwr">, COP0_TLB_FM<0b001110>,
ISA_MIPS32R5, ASE_VIRT;
def HYPCALL : MMRel, HYPCALL_FT<"hypcall">,
HYPCALL_FM<0b101000>, ISA_MIPS32R5, ASE_VIRT;
diff --git a/llvm/lib/Target/Mips/MipsMSAInstrFormats.td b/llvm/lib/Target/Mips/MipsMSAInstrFormats.td
index 2bfc92c85e965..c4ffb27f679c3 100644
--- a/llvm/lib/Target/Mips/MipsMSAInstrFormats.td
+++ b/llvm/lib/Target/Mips/MipsMSAInstrFormats.td
@@ -6,7 +6,7 @@
//
//===----------------------------------------------------------------------===//
-class MSAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>,
+class MSAInst : MipsInst<(outs), (ins), "", [], FrmOther>,
ASE_MSA {
let EncodingPredicates = [HasStdEnc];
let Inst{31-26} = 0b011110;
@@ -20,9 +20,8 @@ class MSASpecial : MSAInst {
let Inst{31-26} = 0b000000;
}
-class MSAPseudo<dag outs, dag ins, list<dag> pattern,
- InstrItinClass itin = IIPseudo>:
- MipsPseudo<outs, ins, pattern, itin> {
+class MSAPseudo<dag outs, dag ins, list<dag> pattern>:
+ MipsPseudo<outs, ins, pattern> {
let EncodingPredicates = [HasStdEnc];
let ASEPredicate = [HasMSA];
}
diff --git a/llvm/lib/Target/Mips/MipsMSAInstrInfo.td b/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
index bf1d8933f0e0c..5c28069055f16 100644
--- a/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
@@ -1059,63 +1059,52 @@ class XORI_B_ENC : MSA_I8_FMT<0b11, 0b000000>;
// Instruction desc.
class MSA_BIT_B_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
ComplexPattern Imm, RegisterOperand ROWD,
- RegisterOperand ROWS = ROWD,
- InstrItinClass itin = NoItinerary> {
+ RegisterOperand ROWS = ROWD> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWS:$ws, vsplat_uimm3:$m);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
- InstrItinClass Itinerary = itin;
}
class MSA_BIT_H_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
ComplexPattern Imm, RegisterOperand ROWD,
- RegisterOperand ROWS = ROWD,
- InstrItinClass itin = NoItinerary> {
+ RegisterOperand ROWS = ROWD> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWS:$ws, vsplat_uimm4:$m);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
- InstrItinClass Itinerary = itin;
}
class MSA_BIT_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
ComplexPattern Imm, RegisterOperand ROWD,
- RegisterOperand ROWS = ROWD,
- InstrItinClass itin = NoItinerary> {
+ RegisterOperand ROWS = ROWD> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWS:$ws, vsplat_uimm5:$m);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
- InstrItinClass Itinerary = itin;
}
class MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
ComplexPattern Imm, RegisterOperand ROWD,
- RegisterOperand ROWS = ROWD,
- InstrItinClass itin = NoItinerary> {
+ RegisterOperand ROWS = ROWD> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWS:$ws, vsplat_uimm6:$m);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
- InstrItinClass Itinerary = itin;
}
class MSA_BIT_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD,
- RegisterOperand ROWS = ROWD,
- InstrItinClass itin = NoItinerary> {
+ RegisterOperand ROWS = ROWD> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWS:$ws, ImmOp:$m);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
- InstrItinClass Itinerary = itin;
}
class MSA_BIT_BINSXI_DESC_BASE<string instr_asm, ValueType Ty,
SplatComplexPattern Mask, RegisterOperand ROWD,
- RegisterOperand ROWS = ROWD,
- InstrItinClass itin = NoItinerary> {
+ RegisterOperand ROWS = ROWD> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, Mask.OpClass:$m);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
@@ -1125,55 +1114,46 @@ class MSA_BIT_BINSXI_DESC_BASE<string instr_asm, ValueType Ty,
// (BSEL_V cond, if_clear, if_set)
list<dag> Pattern = [(set ROWD:$wd, (vselect (Ty Mask:$m), (Ty ROWD:$ws),
ROWS:$wd_in))];
- InstrItinClass Itinerary = itin;
string Constraints = "$wd = $wd_in";
}
class MSA_BIT_BINSLI_DESC_BASE<string instr_asm, ValueType Ty,
SplatComplexPattern ImmOp, RegisterOperand ROWD,
- RegisterOperand ROWS = ROWD,
- InstrItinClass itin = NoItinerary> :
- MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, ImmOp, ROWD, ROWS, itin>;
+ RegisterOperand ROWS = ROWD> :
+ MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, ImmOp, ROWD, ROWS>;
class MSA_BIT_BINSRI_DESC_BASE<string instr_asm, ValueType Ty,
SplatComplexPattern ImmOp, RegisterOperand ROWD,
- RegisterOperand ROWS = ROWD,
- InstrItinClass itin = NoItinerary> :
- MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, ImmOp, ROWD, ROWS, itin>;
+ RegisterOperand ROWS = ROWD> :
+ MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, ImmOp, ROWD, ROWS>;
class MSA_BIT_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
SplatComplexPattern SplatImm,
- RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
- InstrItinClass itin = NoItinerary> {
+ RegisterOperand ROWD, RegisterOperand ROWS = ROWD> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$m);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$m))];
- InstrItinClass Itinerary = itin;
}
class MSA_COPY_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
ValueType VecTy, Operand ImmOp, ImmLeaf Imm,
- RegisterOperand ROD, RegisterOperand ROWS,
- InstrItinClass itin = NoItinerary> {
+ RegisterOperand ROD, RegisterOperand ROWS> {
dag OutOperandList = (outs ROD:$rd);
dag InOperandList = (ins ROWS:$ws, ImmOp:$n);
string AsmString = !strconcat(instr_asm, "\t$rd, $ws[$n]");
list<dag> Pattern = [(set ROD:$rd, (OpNode (VecTy ROWS:$ws), Imm:$n))];
- InstrItinClass Itinerary = itin;
}
class MSA_ELM_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
RegisterOperand ROWD, RegisterOperand ROWS,
- Operand ImmOp, ImmLeaf Imm,
- InstrItinClass itin = NoItinerary> {
+ Operand ImmOp, ImmLeaf Imm> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ImmOp:$n);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]");
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
Imm:$n))];
string Constraints = "$wd = $wd_in";
- InstrItinClass Itinerary = itin;
}
class MSA_COPY_PSEUDO_BASE<SDPatternOperator OpNode, ValueType VecTy,
@@ -1187,38 +1167,31 @@ class MSA_COPY_PSEUDO_BASE<SDPatternOperator OpNode, ValueType VecTy,
class MSA_I5_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
SplatComplexPattern SplatImm, RegisterOperand ROWD,
- RegisterOperand ROWS = ROWD,
- InstrItinClass itin = NoItinerary> {
+ RegisterOperand ROWS = ROWD> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$imm);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $imm");
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$imm))];
- InstrItinClass Itinerary = itin;
}
class MSA_I8_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
SplatComplexPattern SplatImm, RegisterOperand ROWD,
- RegisterOperand ROWS = ROWD,
- InstrItinClass itin = NoItinerary> {
+ RegisterOperand ROWS = ROWD> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$u8);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$u8))];
- InstrItinClass Itinerary = itin;
}
class MSA_I8_SHF_DESC_BASE<string instr_asm, RegisterOperand ROWD,
- RegisterOperand ROWS = ROWD,
- InstrItinClass itin = NoItinerary> {
+ RegisterOperand ROWS = ROWD> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWS:$ws, uimm8:$u8);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
list<dag> Pattern = [(set ROWD:$wd, (MipsSHF timmZExt8:$u8, ROWS:$ws))];
- InstrItinClass Itinerary = itin;
}
-class MSA_I10_LDI_DESC_BASE<string instr_asm, RegisterOperand ROWD,
- InstrItinClass itin = NoItinerary> {
+class MSA_I10_LDI_DESC_BASE<string instr_asm, RegisterOperand ROWD> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins vsplat_simm10:$s10);
string AsmString = !strconcat(instr_asm, "\t$wd, $s10");
@@ -1226,28 +1199,23 @@ class MSA_I10_LDI_DESC_BASE<string instr_asm, RegisterOperand ROWD,
list<dag> Pattern = [];
bit hasSideEffects = 0;
bit isReMaterializable = 1;
- InstrItinClass Itinerary = itin;
}
class MSA_2R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
- RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
- InstrItinClass itin = NoItinerary> {
+ RegisterOperand ROWD, RegisterOperand ROWS = ROWD> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWS:$ws);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws");
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))];
- InstrItinClass Itinerary = itin;
}
class MSA_2R_FILL_DESC_BASE<string instr_asm, ValueType VT,
SDPatternOperator OpNode, RegisterOperand ROWD,
- RegisterOperand ROS = ROWD,
- InstrItinClass itin = NoItinerary> {
+ RegisterOperand ROS = ROWD> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROS:$rs);
string AsmString = !strconcat(instr_asm, "\t$wd, $rs");
list<dag> Pattern = [(set ROWD:$wd, (VT (OpNode ROS:$rs)))];
- InstrItinClass Itinerary = itin;
}
class MSA_2R_FILL_PSEUDO_BASE<SDPatternOperator OpNode,
@@ -1258,105 +1226,88 @@ class MSA_2R_FILL_PSEUDO_BASE<SDPatternOperator OpNode,
}
class MSA_2RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
- RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
- InstrItinClass itin = NoItinerary> {
+ RegisterOperand ROWD, RegisterOperand ROWS = ROWD> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWS:$ws);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws");
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))];
- InstrItinClass Itinerary = itin;
}
class MSA_3R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
- RegisterOperand ROWT = ROWD,
- InstrItinClass itin = NoItinerary> {
+ RegisterOperand ROWT = ROWD> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWS:$ws, ROWT:$wt);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))];
- InstrItinClass Itinerary = itin;
}
class MSA_3R_BINSX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
- RegisterOperand ROWT = ROWD,
- InstrItinClass itin = NoItinerary> {
+ RegisterOperand ROWT = ROWD> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
ROWT:$wt))];
string Constraints = "$wd = $wd_in";
- InstrItinClass Itinerary = itin;
}
class MSA_3R_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
- RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
- InstrItinClass itin = NoItinerary> {
+ RegisterOperand ROWD, RegisterOperand ROWS = ROWD> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWS:$ws, GPR32Opnd:$rt);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]");
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, GPR32Opnd:$rt))];
- InstrItinClass Itinerary = itin;
}
class MSA_3R_VSHF_DESC_BASE<string instr_asm, RegisterOperand ROWD,
RegisterOperand ROWS = ROWD,
- RegisterOperand ROWT = ROWD,
- InstrItinClass itin = NoItinerary> {
+ RegisterOperand ROWT = ROWD> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF ROWD:$wd_in, ROWS:$ws,
ROWT:$wt))];
string Constraints = "$wd = $wd_in";
- InstrItinClass Itinerary = itin;
}
class MSA_3R_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
- RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
- InstrItinClass itin = NoItinerary> {
+ RegisterOperand ROWD, RegisterOperand ROWS = ROWD> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, GPR32Opnd:$rt);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]");
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
GPR32Opnd:$rt))];
- InstrItinClass Itinerary = itin;
string Constraints = "$wd = $wd_in";
}
class MSA_3R_4R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
- RegisterOperand ROWT = ROWD,
- InstrItinClass itin = NoItinerary> {
+ RegisterOperand ROWT = ROWD> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
ROWT:$wt))];
- InstrItinClass Itinerary = itin;
string Constraints = "$wd = $wd_in";
}
class MSA_3RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
- RegisterOperand ROWT = ROWD,
- InstrItinClass itin = NoItinerary> :
- MSA_3R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>;
+ RegisterOperand ROWT = ROWD> :
+ MSA_3R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT>;
class MSA_3RF_4RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
- RegisterOperand ROWT = ROWD,
- InstrItinClass itin = NoItinerary> :
- MSA_3R_4R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>;
+ RegisterOperand ROWT = ROWD> :
+ MSA_3R_4R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT>;
class MSA_CBRANCH_DESC_BASE<string instr_asm, RegisterOperand ROWD> {
dag OutOperandList = (outs);
dag InOperandList = (ins ROWD:$wt, brtarget:$offset);
string AsmString = !strconcat(instr_asm, "\t$wt, $offset");
list<dag> Pattern = [];
- InstrItinClass Itinerary = NoItinerary;
bit isBranch = 1;
bit isTerminator = 1;
bit hasDelaySlot = 1;
@@ -1365,13 +1316,11 @@ class MSA_CBRANCH_DESC_BASE<string instr_asm, RegisterOperand ROWD> {
class MSA_INSERT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD,
- RegisterOperand ROS,
- InstrItinClass itin = NoItinerary> {
+ RegisterOperand ROS> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWD:$wd_in, ROS:$rs, ImmOp:$n);
string AsmString = !strconcat(instr_asm, "\t$wd[$n], $rs");
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROS:$rs, Imm:$n))];
- InstrItinClass Itinerary = itin;
string Constraints = "$wd = $wd_in";
}
@@ -1397,8 +1346,7 @@ class MSA_INSERT_VIDX_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty,
class MSA_INSVE_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD,
- RegisterOperand ROWS = ROWD,
- InstrItinClass itin = NoItinerary> {
+ RegisterOperand ROWS = ROWD> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWD:$wd_in, ImmOp:$n, ROWS:$ws, uimmz:$n2);
string AsmString = !strconcat(instr_asm, "\t$wd[$n], $ws[$n2]");
@@ -1406,31 +1354,26 @@ class MSA_INSVE_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
Imm:$n,
ROWS:$ws,
immz:$n2))];
- InstrItinClass Itinerary = itin;
string Constraints = "$wd = $wd_in";
}
class MSA_VEC_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
- RegisterOperand ROWT = ROWD,
- InstrItinClass itin = NoItinerary> {
+ RegisterOperand ROWT = ROWD> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWS:$ws, ROWT:$wt);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))];
- InstrItinClass Itinerary = itin;
}
class MSA_ELM_SPLAT_DESC_BASE<string instr_asm, SplatComplexPattern SplatImm,
RegisterOperand ROWD,
- RegisterOperand ROWS = ROWD,
- InstrItinClass itin = NoItinerary> {
+ RegisterOperand ROWS = ROWD> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$n);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]");
list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF SplatImm:$n, ROWS:$ws,
ROWS:$ws))];
- InstrItinClass Itinerary = itin;
}
class MSA_VEC_PSEUDO_BASE<SDPatternOperator OpNode, RegisterOperand ROWD,
@@ -1609,7 +1552,6 @@ class BMNZ_V_DESC {
list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt,
MSA128BOpnd:$ws,
MSA128BOpnd:$wd_in))];
- InstrItinClass Itinerary = NoItinerary;
string Constraints = "$wd = $wd_in";
}
@@ -1621,7 +1563,6 @@ class BMNZI_B_DESC {
list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8,
MSA128BOpnd:$ws,
MSA128BOpnd:$wd_in))];
- InstrItinClass Itinerary = NoItinerary;
string Constraints = "$wd = $wd_in";
}
@@ -1633,7 +1574,6 @@ class BMZ_V_DESC {
list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt,
MSA128BOpnd:$wd_in,
MSA128BOpnd:$ws))];
- InstrItinClass Itinerary = NoItinerary;
string Constraints = "$wd = $wd_in";
}
@@ -1645,7 +1585,6 @@ class BMZI_B_DESC {
list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8,
MSA128BOpnd:$wd_in,
MSA128BOpnd:$ws))];
- InstrItinClass Itinerary = NoItinerary;
string Constraints = "$wd = $wd_in";
}
@@ -1682,7 +1621,6 @@ class BSEL_V_DESC {
list<dag> Pattern = [(set MSA128BOpnd:$wd,
(vselect MSA128BOpnd:$wd_in, MSA128BOpnd:$wt,
MSA128BOpnd:$ws))];
- InstrItinClass Itinerary = NoItinerary;
string Constraints = "$wd = $wd_in";
}
@@ -1698,7 +1636,6 @@ class BSELI_B_DESC {
list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wd_in,
vsplati8_uimm8:$u8,
MSA128BOpnd:$ws))];
- InstrItinClass Itinerary = NoItinerary;
string Constraints = "$wd = $wd_in";
}
@@ -1745,7 +1682,6 @@ class CFCMSA_DESC {
dag OutOperandList = (outs GPR32Opnd:$rd);
dag InOperandList = (ins MSA128CROpnd:$cs);
string AsmString = "cfcmsa\t$rd, $cs";
- InstrItinClass Itinerary = NoItinerary;
bit hasSideEffects = 1;
bit isMoveReg = 1;
}
@@ -1840,7 +1776,6 @@ class CTCMSA_DESC {
dag OutOperandList = (outs);
dag InOperandList = (ins MSA128CROpnd:$cd, GPR32Opnd:$rs);
string AsmString = "ctcmsa\t$cd, $rs";
- InstrItinClass Itinerary = NoItinerary;
bit hasSideEffects = 1;
bit isMoveReg = 1;
}
@@ -2252,13 +2187,11 @@ class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", insve_v2i64, uimm1, timmZExt
class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
ValueType TyNode, RegisterOperand ROWD,
- Operand MemOpnd, ComplexPattern Addr = addrimm10,
- InstrItinClass itin = NoItinerary> {
+ Operand MemOpnd, ComplexPattern Addr = addrimm10> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins MemOpnd:$addr);
string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
list<dag> Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addr)))];
- InstrItinClass Itinerary = itin;
string DecoderMethod = "DecodeMSA128Mem";
}
@@ -2285,19 +2218,17 @@ class MSA_LOAD_PSEUDO_BASE<SDPatternOperator intrinsic, RegisterOperand RO> :
def LDR_D : MSA_LOAD_PSEUDO_BASE<int_mips_ldr_d, MSA128DOpnd>;
def LDR_W : MSA_LOAD_PSEUDO_BASE<int_mips_ldr_w, MSA128WOpnd>;
-class LSA_DESC_BASE<string instr_asm, RegisterOperand RORD,
- InstrItinClass itin = NoItinerary> {
+class LSA_DESC_BASE<string instr_asm, RegisterOperand RORD> {
dag OutOperandList = (outs RORD:$rd);
dag InOperandList = (ins RORD:$rs, RORD:$rt, uimm2_plus1:$sa);
string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $sa");
list<dag> Pattern = [(set RORD:$rd, (add RORD:$rt,
(shl RORD:$rs,
immZExt2Lsa:$sa)))];
- InstrItinClass Itinerary = itin;
}
-class LSA_DESC : LSA_DESC_BASE<"lsa", GPR32Opnd, II_LSA>;
-class DLSA_DESC : LSA_DESC_BASE<"dlsa", GPR64Opnd, II_DLSA>;
+class LSA_DESC : LSA_DESC_BASE<"lsa", GPR32Opnd>;
+class DLSA_DESC : LSA_DESC_BASE<"dlsa", GPR64Opnd>;
class MADD_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.h", int_mips_madd_q_h,
MSA128HOpnd>;
@@ -2395,7 +2326,6 @@ class MOVE_V_DESC {
dag InOperandList = (ins MSA128BOpnd:$ws);
string AsmString = "move.v\t$wd, $ws";
list<dag> Pattern = [];
- InstrItinClass Itinerary = NoItinerary;
bit isMoveReg = 1;
}
@@ -2599,13 +2529,11 @@ class SRLRI_D_DESC : MSA_BIT_X_DESC_BASE<"srlri.d", int_mips_srlri_d, uimm6,
class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
ValueType TyNode, RegisterOperand ROWD,
- Operand MemOpnd, ComplexPattern Addr = addrimm10,
- InstrItinClass itin = NoItinerary> {
+ Operand MemOpnd, ComplexPattern Addr = addrimm10> {
dag OutOperandList = (outs);
dag InOperandList = (ins ROWD:$wd, MemOpnd:$addr);
string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
list<dag> Pattern = [(OpNode (TyNode ROWD:$wd), Addr:$addr)];
- InstrItinClass Itinerary = itin;
string DecoderMethod = "DecodeMSA128Mem";
}
@@ -3531,13 +3459,11 @@ def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addrimm10lsl3:$addr),
(ST_D MSA128D:$ws, addrimm10lsl3:$addr)>;
class MSA_FABS_PSEUDO_DESC_BASE<RegisterOperand ROWD,
- RegisterOperand ROWS = ROWD,
- InstrItinClass itin = NoItinerary> :
+ RegisterOperand ROWS = ROWD> :
MSAPseudo<(outs ROWD:$wd),
(ins ROWS:$ws),
- [(set ROWD:$wd, (fabs ROWS:$ws))]> {
- InstrItinClass Itinerary = itin;
-}
+ [(set ROWD:$wd, (fabs ROWS:$ws))]>;
+
def FABS_W : MSA_FABS_PSEUDO_DESC_BASE<MSA128WOpnd>,
PseudoInstExpansion<(FMAX_A_W MSA128WOpnd:$wd, MSA128WOpnd:$ws,
MSA128WOpnd:$ws)>;
diff --git a/llvm/lib/Target/Mips/MipsMTInstrFormats.td b/llvm/lib/Target/Mips/MipsMTInstrFormats.td
index 22c290b1c114b..1f4086a857b26 100644
--- a/llvm/lib/Target/Mips/MipsMTInstrFormats.td
+++ b/llvm/lib/Target/Mips/MipsMTInstrFormats.td
@@ -14,7 +14,7 @@
//
//===----------------------------------------------------------------------===//
-class MipsMTInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
+class MipsMTInst : MipsInst<(outs), (ins), "", [], FrmOther> {
let DecoderNamespace = "Mips";
let EncodingPredicates = [HasStdEnc];
}
diff --git a/llvm/lib/Target/Mips/MipsMTInstrInfo.td b/llvm/lib/Target/Mips/MipsMTInstrInfo.td
index 95fe065616a06..4cb609df0639b 100644
--- a/llvm/lib/Target/Mips/MipsMTInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsMTInstrInfo.td
@@ -41,12 +41,11 @@ class MTTR_ENC : COP0_MFTTR_MT<FIELD5_MTTR>;
// MIPS MT Instruction Descriptions
//===----------------------------------------------------------------------===//
-class MT_1R_DESC_BASE<string instr_asm, InstrItinClass Itin = NoItinerary> {
+class MT_1R_DESC_BASE<string instr_asm> {
dag OutOperandList = (outs GPR32Opnd:$rt);
dag InOperandList = (ins);
string AsmString = !strconcat(instr_asm, "\t$rt");
list<dag> Pattern = [];
- InstrItinClass Itinerary = Itin;
}
class MFTR_DESC {
@@ -54,7 +53,6 @@ class MFTR_DESC {
dag InOperandList = (ins GPR32Opnd:$rt, uimm1:$u, uimm3:$sel, uimm1:$h);
string AsmString = "mftr\t$rd, $rt, $u, $sel, $h";
list<dag> Pattern = [];
- InstrItinClass Itinerary = II_MFTR;
}
class MTTR_DESC {
@@ -62,7 +60,6 @@ class MTTR_DESC {
dag InOperandList = (ins GPR32Opnd:$rt, uimm1:$u, uimm3:$sel, uimm1:$h);
string AsmString = "mttr\t$rt, $rd, $u, $sel, $h";
list<dag> Pattern = [];
- InstrItinClass Itinerary = II_MTTR;
}
class FORK_DESC {
@@ -70,7 +67,6 @@ class FORK_DESC {
dag InOperandList = (ins GPR32Opnd:$rt);
string AsmString = "fork\t$rd, $rs, $rt";
list<dag> Pattern = [];
- InstrItinClass Itinerary = II_FORK;
}
class YIELD_DESC {
@@ -78,16 +74,15 @@ class YIELD_DESC {
dag InOperandList = (ins GPR32Opnd:$rs);
string AsmString = "yield\t$rd, $rs";
list<dag> Pattern = [];
- InstrItinClass Itinerary = II_YIELD;
}
-class DMT_DESC : MT_1R_DESC_BASE<"dmt", II_DMT>;
+class DMT_DESC : MT_1R_DESC_BASE<"dmt">;
-class EMT_DESC : MT_1R_DESC_BASE<"emt", II_EMT>;
+class EMT_DESC : MT_1R_DESC_BASE<"emt">;
-class DVPE_DESC : MT_1R_DESC_BASE<"dvpe", II_DVPE>;
+class DVPE_DESC : MT_1R_DESC_BASE<"dvpe">;
-class EVPE_DESC : MT_1R_DESC_BASE<"evpe", II_EVPE>;
+class EVPE_DESC : MT_1R_DESC_BASE<"evpe">;
//===----------------------------------------------------------------------===//
// MIPS MT Instruction Definitions
diff --git a/llvm/lib/Target/Mips/MipsSchedule.td b/llvm/lib/Target/Mips/MipsSchedule.td
deleted file mode 100644
index 3a5b3fe3b34bc..0000000000000
--- a/llvm/lib/Target/Mips/MipsSchedule.td
+++ /dev/null
@@ -1,742 +0,0 @@
-//===-- MipsSchedule.td - Mips Scheduling Definitions ------*- tablegen -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// Functional units across Mips chips sets. Based on GCC/Mips backend files.
-//===----------------------------------------------------------------------===//
-def ALU : FuncUnit;
-def IMULDIV : FuncUnit;
-
-//===----------------------------------------------------------------------===//
-// Instruction Itinerary classes used for Mips
-//===----------------------------------------------------------------------===//
-// IIM16Alu is a placeholder class for most MIPS16 instructions.
-def IIM16Alu : InstrItinClass;
-def IIPseudo : InstrItinClass;
-
-def II_ABS : InstrItinClass;
-def II_ADDI : InstrItinClass;
-def II_ADDIU : InstrItinClass;
-def II_ADDIUPC : InstrItinClass;
-def II_ADD : InstrItinClass;
-def II_ADDU : InstrItinClass;
-def II_ADD_D : InstrItinClass;
-def II_ADD_PS : InstrItinClass;
-def II_ADD_S : InstrItinClass;
-def II_ADDR_PS : InstrItinClass;
-def II_ALIGN : InstrItinClass;
-def II_AND : InstrItinClass;
-def II_ANDI : InstrItinClass;
-def II_ALUIPC : InstrItinClass;
-def II_AUI : InstrItinClass;
-def II_AUIPC : InstrItinClass;
-def II_B : InstrItinClass;
-def II_BADDU : InstrItinClass;
-def II_BBIT : InstrItinClass; // bbit[01], bbit[01]32
-def II_BALC : InstrItinClass;
-def II_BC : InstrItinClass;
-def II_BC1F : InstrItinClass;
-def II_BC1FL : InstrItinClass;
-def II_BC1T : InstrItinClass;
-def II_BC1TL : InstrItinClass;
-def II_BC1CCZ : InstrItinClass;
-def II_BC2CCZ : InstrItinClass;
-def II_BCC : InstrItinClass; // beq and bne
-def II_BCCZ : InstrItinClass; // b[gl][et]z
-def II_BCCC : InstrItinClass; // b<cc>c
-def II_BCCZAL : InstrItinClass; // bgezal and bltzal
-def II_BCCZALS : InstrItinClass; // bgezals and bltzals
-def II_BCCZC : InstrItinClass; // beqzc, bnezc
-def II_BITSWAP : InstrItinClass;
-def II_CEIL : InstrItinClass;
-def II_CFC1 : InstrItinClass;
-def II_CFC2 : InstrItinClass;
-def II_CLO : InstrItinClass;
-def II_CLZ : InstrItinClass;
-def II_CRC32B : InstrItinClass;
-def II_CRC32CB : InstrItinClass;
-def II_CRC32CD : InstrItinClass;
-def II_CRC32CH : InstrItinClass;
-def II_CRC32CW : InstrItinClass;
-def II_CRC32D : InstrItinClass;
-def II_CRC32H : InstrItinClass;
-def II_CRC32W : InstrItinClass;
-def II_CTC1 : InstrItinClass;
-def II_CTC2 : InstrItinClass;
-def II_CVT : InstrItinClass;
-def II_C_CC_D : InstrItinClass; // Any c.<cc>.d instruction
-def II_C_CC_S : InstrItinClass; // Any c.<cc>.s instruction
-def II_CMP_CC_D : InstrItinClass; // Any cmp.<cc>.d instruction
-def II_CMP_CC_S : InstrItinClass; // Any cmp.<cc>.s instruction
-def II_CLASS_D : InstrItinClass;
-def II_CLASS_S : InstrItinClass;
-def II_DADDIU : InstrItinClass;
-def II_DADDU : InstrItinClass;
-def II_DADDI : InstrItinClass;
-def II_DADD : InstrItinClass;
-def II_DAHI : InstrItinClass;
-def II_DATI : InstrItinClass;
-def II_DAUI : InstrItinClass;
-def II_DALIGN : InstrItinClass;
-def II_DBITSWAP : InstrItinClass;
-def II_DCLO : InstrItinClass;
-def II_DCLZ : InstrItinClass;
-def II_DDIV : InstrItinClass;
-def II_DDIVU : InstrItinClass;
-def II_DIV : InstrItinClass;
-def II_DIVU : InstrItinClass;
-def II_DIV_D : InstrItinClass;
-def II_DIV_S : InstrItinClass;
-def II_DMFC0 : InstrItinClass;
-def II_DMFGC0 : InstrItinClass;
-def II_DMT : InstrItinClass;
-def II_DMTC0 : InstrItinClass;
-def II_DMTGC0 : InstrItinClass;
-def II_DMFC1 : InstrItinClass;
-def II_DMTC1 : InstrItinClass;
-def II_DMOD : InstrItinClass;
-def II_DMODU : InstrItinClass;
-def II_DMUH : InstrItinClass;
-def II_DMUHU : InstrItinClass;
-def II_DMFC2 : InstrItinClass;
-def II_DMTC2 : InstrItinClass;
-def II_DMUL : InstrItinClass;
-def II_DMULU : InstrItinClass;
-def II_DMULT : InstrItinClass;
-def II_DMULTU : InstrItinClass;
-def II_DROTR : InstrItinClass;
-def II_DROTR32 : InstrItinClass;
-def II_DROTRV : InstrItinClass;
-def II_DSLL : InstrItinClass;
-def II_DSLL32 : InstrItinClass;
-def II_DSLLV : InstrItinClass;
-def II_DSRA : InstrItinClass;
-def II_DSRA32 : InstrItinClass;
-def II_DSRAV : InstrItinClass;
-def II_DSRL : InstrItinClass;
-def II_DSRL32 : InstrItinClass;
-def II_DSRLV : InstrItinClass;
-def II_DSBH : InstrItinClass;
-def II_DSHD : InstrItinClass;
-def II_DSUBU : InstrItinClass;
-def II_DSUB : InstrItinClass;
-def II_DVPE : InstrItinClass;
-def II_EMT : InstrItinClass;
-def II_EVPE : InstrItinClass;
-def II_EXT : InstrItinClass; // Any EXT instruction
-def II_FLOOR : InstrItinClass;
-def II_FORK : InstrItinClass;
-def II_GINVI : InstrItinClass;
-def II_GINVT : InstrItinClass;
-def II_HYPCALL : InstrItinClass;
-def II_INS : InstrItinClass; // Any INS instruction
-def II_IndirectBranchPseudo : InstrItinClass; // Indirect branch pseudo.
-def II_J : InstrItinClass;
-def II_JAL : InstrItinClass;
-def II_JALR : InstrItinClass;
-def II_JALR_HB : InstrItinClass;
-def II_JALRC : InstrItinClass;
-def II_JALRS : InstrItinClass;
-def II_JALS : InstrItinClass;
-def II_JIC : InstrItinClass;
-def II_JIALC : InstrItinClass;
-def II_JR : InstrItinClass;
-def II_JR_HB : InstrItinClass;
-def II_JRADDIUSP : InstrItinClass;
-def II_JRC : InstrItinClass;
-def II_ReturnPseudo : InstrItinClass; // Return pseudo.
-def II_ERET : InstrItinClass;
-def II_DERET : InstrItinClass;
-def II_ERETNC : InstrItinClass;
-def II_EHB : InstrItinClass;
-def II_SDBBP : InstrItinClass;
-def II_SIGRIE : InstrItinClass;
-def II_SSNOP : InstrItinClass;
-def II_SYSCALL : InstrItinClass;
-def II_PAUSE : InstrItinClass;
-def II_WAIT : InstrItinClass;
-def II_EI : InstrItinClass;
-def II_DI : InstrItinClass;
-def II_TEQ : InstrItinClass;
-def II_TEQI : InstrItinClass;
-def II_TGE : InstrItinClass;
-def II_TGEI : InstrItinClass;
-def II_TGEIU : InstrItinClass;
-def II_TGEU : InstrItinClass;
-def II_TNE : InstrItinClass;
-def II_TNEI : InstrItinClass;
-def II_TLT : InstrItinClass;
-def II_TLTI : InstrItinClass;
-def II_TLTU : InstrItinClass;
-def II_TTLTIU : InstrItinClass;
-def II_TLBP : InstrItinClass;
-def II_TLBR : InstrItinClass;
-def II_TLBWI : InstrItinClass;
-def II_TLBWR : InstrItinClass;
-def II_TRAP : InstrItinClass;
-def II_BREAK : InstrItinClass;
-def II_SYNC : InstrItinClass;
-def II_SYNCI : InstrItinClass;
-def II_LB : InstrItinClass;
-def II_LBE : InstrItinClass;
-def II_LBU : InstrItinClass;
-def II_LBUE : InstrItinClass;
-def II_LD : InstrItinClass;
-def II_LDC1 : InstrItinClass;
-def II_LDC2 : InstrItinClass;
-def II_LDC3 : InstrItinClass;
-def II_LDL : InstrItinClass;
-def II_LDR : InstrItinClass;
-def II_LDPC : InstrItinClass;
-def II_LDXC1 : InstrItinClass;
-def II_LH : InstrItinClass;
-def II_LHE : InstrItinClass;
-def II_LHU : InstrItinClass;
-def II_LHUE : InstrItinClass;
-def II_LL : InstrItinClass;
-def II_LI : InstrItinClass;
-def II_LLD : InstrItinClass;
-def II_LUI : InstrItinClass;
-def II_LUXC1 : InstrItinClass;
-def II_LW : InstrItinClass;
-def II_LWE : InstrItinClass;
-def II_LWC1 : InstrItinClass;
-def II_LWC2 : InstrItinClass;
-def II_LWC3 : InstrItinClass;
-def II_LWM : InstrItinClass;
-def II_LWL : InstrItinClass;
-def II_LWLE : InstrItinClass;
-def II_LWPC : InstrItinClass;
-def II_LWP : InstrItinClass;
-def II_LWR : InstrItinClass;
-def II_LWRE : InstrItinClass;
-def II_LWU : InstrItinClass;
-def II_LWUPC : InstrItinClass;
-def II_LWXC1 : InstrItinClass;
-def II_LWXS : InstrItinClass;
-def II_LSA : InstrItinClass;
-def II_DLSA : InstrItinClass;
-def II_MADD : InstrItinClass;
-def II_MADDU : InstrItinClass;
-def II_MADD_D : InstrItinClass;
-def II_MADD_S : InstrItinClass;
-def II_MADDF_D : InstrItinClass;
-def II_MADDF_S : InstrItinClass;
-def II_MAX_D : InstrItinClass;
-def II_MAX_S : InstrItinClass;
-def II_MAXA_D : InstrItinClass;
-def II_MAXA_S : InstrItinClass;
-def II_MIN_D : InstrItinClass;
-def II_MIN_S : InstrItinClass;
-def II_MINA_D : InstrItinClass;
-def II_MINA_S : InstrItinClass;
-def II_MFC0 : InstrItinClass;
-def II_MFHC0 : InstrItinClass;
-def II_MFC1 : InstrItinClass;
-def II_MFHC1 : InstrItinClass;
-def II_MFC2 : InstrItinClass;
-def II_MFGC0 : InstrItinClass;
-def II_MFHGC0 : InstrItinClass;
-def II_MFHI_MFLO : InstrItinClass; // mfhi and mflo
-def II_MFTR : InstrItinClass;
-def II_MOD : InstrItinClass;
-def II_MODU : InstrItinClass;
-def II_MOVE : InstrItinClass;
-def II_MOVF : InstrItinClass;
-def II_MOVF_D : InstrItinClass;
-def II_MOVF_S : InstrItinClass;
-def II_MOVN : InstrItinClass;
-def II_MOVN_D : InstrItinClass;
-def II_MOVN_S : InstrItinClass;
-def II_MOVT : InstrItinClass;
-def II_MOVT_D : InstrItinClass;
-def II_MOVT_S : InstrItinClass;
-def II_MOVZ : InstrItinClass;
-def II_MOVZ_D : InstrItinClass;
-def II_MOVZ_S : InstrItinClass;
-def II_MOV_D : InstrItinClass;
-def II_MOV_S : InstrItinClass;
-def II_MSUB : InstrItinClass;
-def II_MSUBU : InstrItinClass;
-def II_MSUB_D : InstrItinClass;
-def II_MSUB_S : InstrItinClass;
-def II_MSUBF_D : InstrItinClass;
-def II_MSUBF_S : InstrItinClass;
-def II_MTC0 : InstrItinClass;
-def II_MTHC0 : InstrItinClass;
-def II_MTC1 : InstrItinClass;
-def II_MTHC1 : InstrItinClass;
-def II_MTC2 : InstrItinClass;
-def II_MTGC0 : InstrItinClass;
-def II_MTHGC0 : InstrItinClass;
-def II_MTHI_MTLO : InstrItinClass; // mthi and mtlo
-def II_MTTR : InstrItinClass;
-def II_MUL : InstrItinClass;
-def II_MUH : InstrItinClass;
-def II_MUHU : InstrItinClass;
-def II_MULU : InstrItinClass;
-def II_MUL_PS : InstrItinClass;
-def II_MULR_PS : InstrItinClass;
-def II_MULT : InstrItinClass;
-def II_MULTU : InstrItinClass;
-def II_MUL_D : InstrItinClass;
-def II_MUL_S : InstrItinClass;
-def II_NEG : InstrItinClass;
-def II_NMADD_D : InstrItinClass;
-def II_NMADD_S : InstrItinClass;
-def II_NMSUB_D : InstrItinClass;
-def II_NMSUB_S : InstrItinClass;
-def II_NOR : InstrItinClass;
-def II_NOT : InstrItinClass;
-def II_OR : InstrItinClass;
-def II_ORI : InstrItinClass;
-def II_POP : InstrItinClass;
-def II_RDHWR : InstrItinClass;
-def II_RESTORE : InstrItinClass;
-def II_RECIP_S : InstrItinClass;
-def II_RECIP_D : InstrItinClass;
-def II_RINT_S : InstrItinClass;
-def II_RINT_D : InstrItinClass;
-def II_ROTR : InstrItinClass;
-def II_ROTRV : InstrItinClass;
-def II_ROUND : InstrItinClass;
-def II_RSQRT_S : InstrItinClass;
-def II_RSQRT_D : InstrItinClass;
-def II_SAVE : InstrItinClass;
-def II_SC : InstrItinClass;
-def II_SCD : InstrItinClass;
-def II_SB : InstrItinClass;
-def II_SBE : InstrItinClass;
-def II_SD : InstrItinClass;
-def II_SDC1 : InstrItinClass;
-def II_SDC2 : InstrItinClass;
-def II_SDC3 : InstrItinClass;
-def II_SDL : InstrItinClass;
-def II_SDR : InstrItinClass;
-def II_SDXC1 : InstrItinClass;
-def II_SEB : InstrItinClass;
-def II_SEH : InstrItinClass;
-def II_SELCCZ : InstrItinClass;
-def II_SELCCZ_D : InstrItinClass;
-def II_SELCCZ_S : InstrItinClass;
-def II_SEQ_SNE : InstrItinClass; // seq and sne
-def II_SEQI_SNEI : InstrItinClass; // seqi and snei
-def II_SH : InstrItinClass;
-def II_SHE : InstrItinClass;
-def II_SLL : InstrItinClass;
-def II_SLLV : InstrItinClass;
-def II_SLTI_SLTIU : InstrItinClass; // slti and sltiu
-def II_SLT_SLTU : InstrItinClass; // slt and sltu
-def II_SQRT_D : InstrItinClass;
-def II_SQRT_S : InstrItinClass;
-def II_SEL_D : InstrItinClass;
-def II_SEL_S : InstrItinClass;
-def II_SRA : InstrItinClass;
-def II_SRAV : InstrItinClass;
-def II_SRL : InstrItinClass;
-def II_SRLV : InstrItinClass;
-def II_SUB : InstrItinClass;
-def II_SUBU : InstrItinClass;
-def II_SUB_D : InstrItinClass;
-def II_SUB_PS : InstrItinClass;
-def II_SUB_S : InstrItinClass;
-def II_SUXC1 : InstrItinClass;
-def II_SW : InstrItinClass;
-def II_SWE : InstrItinClass;
-def II_SWC1 : InstrItinClass;
-def II_SWC2 : InstrItinClass;
-def II_SWC3 : InstrItinClass;
-def II_SWL : InstrItinClass;
-def II_SWLE : InstrItinClass;
-def II_SWM : InstrItinClass;
-def II_SWP : InstrItinClass;
-def II_SWR : InstrItinClass;
-def II_SWRE : InstrItinClass;
-def II_SWXC1 : InstrItinClass;
-def II_TRUNC : InstrItinClass;
-def II_WSBH : InstrItinClass;
-def II_XOR : InstrItinClass;
-def II_XORI : InstrItinClass;
-def II_CACHE : InstrItinClass;
-def II_PREF : InstrItinClass;
-def II_CACHEE : InstrItinClass;
-def II_PREFE : InstrItinClass;
-def II_LLE : InstrItinClass;
-def II_SCE : InstrItinClass;
-def II_TLBGINV : InstrItinClass;
-def II_TLBGINVF : InstrItinClass;
-def II_TLBGP : InstrItinClass;
-def II_TLBGR : InstrItinClass;
-def II_TLBGWI : InstrItinClass;
-def II_TLBGWR : InstrItinClass;
-def II_TLBINV : InstrItinClass;
-def II_TLBINVF : InstrItinClass;
-def II_WRPGPR : InstrItinClass;
-def II_RDPGPR : InstrItinClass;
-def II_DVP : InstrItinClass;
-def II_EVP : InstrItinClass;
-def II_YIELD : InstrItinClass;
-
-//===----------------------------------------------------------------------===//
-// Mips Generic instruction itineraries.
-//===----------------------------------------------------------------------===//
-def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
- InstrItinData<IIM16Alu , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_ADDI , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_ADDIU , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_ADDIUPC , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_ADD , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_ADDU , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_AUI , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_AND , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_ALUIPC , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_AUIPC , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_ALIGN , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_BADDU , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_BITSWAP , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SLL , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SRA , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SRL , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_ROTR , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SLLV , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SRAV , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SRLV , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_ROTRV , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_CLO , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_CLZ , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_DADDIU , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_DADDU , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_DADDI , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_DADD , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_DALIGN , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_DAHI , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_DATI , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_DAUI , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_DBITSWAP , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_DCLO , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_DCLZ , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_DMOD , [InstrStage<17, [IMULDIV]>]>,
- InstrItinData<II_DMODU , [InstrStage<17, [IMULDIV]>]>,
- InstrItinData<II_DMT , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_DSLL , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_DSLL32 , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_DSRL , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_DSRL32 , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_DSRA , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_DSRA32 , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_DSLLV , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_DSRLV , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_DSRAV , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_DSUBU , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_DSUB , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_DROTR , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_DROTR32 , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_DROTRV , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_DSBH , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_DSHD , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_DCLO , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_DCLZ , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_DVPE , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_EMT , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_EVPE , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_EXT , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_FORK , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_INS , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_LUI , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_MOVE , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_MOVF , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_MOVN , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_MOVN_S , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_MOVN_D , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_MOVT , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_MOVZ , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_NOR , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_NOT , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_OR , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_POP , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_RDHWR , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SUB , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SUBU , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_XOR , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_ANDI , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_ORI , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_XORI , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_LB , [InstrStage<3, [ALU]>]>,
- InstrItinData<II_LBE , [InstrStage<3, [ALU]>]>,
- InstrItinData<II_LBU , [InstrStage<3, [ALU]>]>,
- InstrItinData<II_LBUE , [InstrStage<3, [ALU]>]>,
- InstrItinData<II_LH , [InstrStage<3, [ALU]>]>,
- InstrItinData<II_LHU , [InstrStage<3, [ALU]>]>,
- InstrItinData<II_LHUE , [InstrStage<3, [ALU]>]>,
- InstrItinData<II_LW , [InstrStage<3, [ALU]>]>,
- InstrItinData<II_LWM , [InstrStage<3, [ALU]>]>,
- InstrItinData<II_LWP , [InstrStage<3, [ALU]>]>,
- InstrItinData<II_LWPC , [InstrStage<3, [ALU]>]>,
- InstrItinData<II_LWL , [InstrStage<3, [ALU]>]>,
- InstrItinData<II_LWLE , [InstrStage<3, [ALU]>]>,
- InstrItinData<II_LWR , [InstrStage<3, [ALU]>]>,
- InstrItinData<II_LWRE , [InstrStage<3, [ALU]>]>,
- InstrItinData<II_LWUPC , [InstrStage<3, [ALU]>]>,
- InstrItinData<II_LD , [InstrStage<3, [ALU]>]>,
- InstrItinData<II_LDL , [InstrStage<3, [ALU]>]>,
- InstrItinData<II_LDR , [InstrStage<3, [ALU]>]>,
- InstrItinData<II_LDPC , [InstrStage<3, [ALU]>]>,
- InstrItinData<II_LI , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_LL , [InstrStage<3, [ALU]>]>,
- InstrItinData<II_LLD , [InstrStage<3, [ALU]>]>,
- InstrItinData<II_RESTORE , [InstrStage<3, [ALU]>]>,
- InstrItinData<II_SB , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SH , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SHE , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SW , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SWM , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SWL , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SWR , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SWP , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SDL , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SDR , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SD , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SC , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SCD , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SAVE , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SELCCZ_S , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SELCCZ_D , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SEQ_SNE , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SEQI_SNEI , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SLTI_SLTIU , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SLT_SLTU , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_B , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_BALC , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_BBIT , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_BC , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_BC1F , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_BC1FL , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_BC1T , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_BC1TL , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_BC1CCZ , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_BC2CCZ , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_BCC , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_BCCC , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_BCCZ , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_BCCZAL , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_BCCZALS , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_BCCZC , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_CLASS_D , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_CLASS_S , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_IndirectBranchPseudo, [InstrStage<1, [ALU]>]>,
- InstrItinData<II_J , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_JAL , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_JALR , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_JALR_HB , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_JALRC , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_JALRS , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_JALS , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_JIC , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_JIALC , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_JR , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_JR_HB , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_JRADDIUSP , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_JRC , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_ReturnPseudo , [InstrStage<1, [ALU]>]>,
- InstrItinData<IIPseudo , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_DMUH , [InstrStage<17, [IMULDIV]>]>,
- InstrItinData<II_DMUHU , [InstrStage<17, [IMULDIV]>]>,
- InstrItinData<II_ERET , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_DERET , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_ERETNC , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_EHB , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SDBBP , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SIGRIE , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SSNOP , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SYSCALL , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_PAUSE , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_WAIT , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_EI , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_DI , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_TEQ , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_TEQI , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_TGE , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_TGEI , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_TGEIU , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_TGEU , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_TNE , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_TNEI , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_TLT , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_TLTI , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_TLTU , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_TTLTIU , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_TLBP , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_TLBR , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_TLBWI , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_TLBWR , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_TRAP , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_BREAK , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SYNC , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SYNCI , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_DMUL , [InstrStage<17, [IMULDIV]>]>,
- InstrItinData<II_DMULT , [InstrStage<17, [IMULDIV]>]>,
- InstrItinData<II_DMULTU , [InstrStage<17, [IMULDIV]>]>,
- InstrItinData<II_DMULU , [InstrStage<17, [IMULDIV]>]>,
- InstrItinData<II_MADD , [InstrStage<17, [IMULDIV]>]>,
- InstrItinData<II_MADDU , [InstrStage<17, [IMULDIV]>]>,
- InstrItinData<II_MFHI_MFLO , [InstrStage<1, [IMULDIV]>]>,
- InstrItinData<II_MAX_D , [InstrStage<4, [ALU]>]>,
- InstrItinData<II_MAX_S , [InstrStage<4, [ALU]>]>,
- InstrItinData<II_MAXA_D , [InstrStage<4, [ALU]>]>,
- InstrItinData<II_MAXA_S , [InstrStage<4, [ALU]>]>,
- InstrItinData<II_MIN_S , [InstrStage<4, [ALU]>]>,
- InstrItinData<II_MIN_D , [InstrStage<4, [ALU]>]>,
- InstrItinData<II_MINA_S , [InstrStage<4, [ALU]>]>,
- InstrItinData<II_MINA_D , [InstrStage<4, [ALU]>]>,
- InstrItinData<II_MOD , [InstrStage<38, [IMULDIV]>]>,
- InstrItinData<II_MODU , [InstrStage<38, [IMULDIV]>]>,
- InstrItinData<II_MSUB , [InstrStage<17, [IMULDIV]>]>,
- InstrItinData<II_MSUBU , [InstrStage<17, [IMULDIV]>]>,
- InstrItinData<II_MTHI_MTLO , [InstrStage<1, [IMULDIV]>]>,
- InstrItinData<II_MUH , [InstrStage<17, [IMULDIV]>]>,
- InstrItinData<II_MUHU , [InstrStage<17, [IMULDIV]>]>,
- InstrItinData<II_MUL , [InstrStage<17, [IMULDIV]>]>,
- InstrItinData<II_MULT , [InstrStage<17, [IMULDIV]>]>,
- InstrItinData<II_MULTU , [InstrStage<17, [IMULDIV]>]>,
- InstrItinData<II_MULU , [InstrStage<17, [IMULDIV]>]>,
- InstrItinData<II_MSUB , [InstrStage<17, [IMULDIV]>]>,
- InstrItinData<II_MSUBU , [InstrStage<17, [IMULDIV]>]>,
- InstrItinData<II_DIV , [InstrStage<38, [IMULDIV]>]>,
- InstrItinData<II_DIVU , [InstrStage<38, [IMULDIV]>]>,
- InstrItinData<II_DDIV , [InstrStage<38, [IMULDIV]>]>,
- InstrItinData<II_DDIVU , [InstrStage<38, [IMULDIV]>]>,
- InstrItinData<II_CEIL , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_CVT , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_ABS , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_FLOOR , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_NEG , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_ROUND , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_TRUNC , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_MOV_D , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_MOV_S , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_CFC1 , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_CTC1 , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_CFC2 , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_CTC2 , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_MOVF_D , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_MOVF_S , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_MOVT_D , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_MOVT_S , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_MOVZ_D , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_MOVZ_S , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_C_CC_S , [InstrStage<3, [ALU]>]>,
- InstrItinData<II_C_CC_D , [InstrStage<3, [ALU]>]>,
- InstrItinData<II_CMP_CC_S , [InstrStage<3, [ALU]>]>,
- InstrItinData<II_CMP_CC_D , [InstrStage<3, [ALU]>]>,
- InstrItinData<II_ADD_D , [InstrStage<4, [ALU]>]>,
- InstrItinData<II_ADD_S , [InstrStage<4, [ALU]>]>,
- InstrItinData<II_SUB_D , [InstrStage<4, [ALU]>]>,
- InstrItinData<II_SUB_S , [InstrStage<4, [ALU]>]>,
- InstrItinData<II_MUL_S , [InstrStage<7, [ALU]>]>,
- InstrItinData<II_MADD_S , [InstrStage<7, [ALU]>]>,
- InstrItinData<II_MADDF_S , [InstrStage<7, [ALU]>]>,
- InstrItinData<II_MSUB_S , [InstrStage<7, [ALU]>]>,
- InstrItinData<II_MSUBF_S , [InstrStage<7, [ALU]>]>,
- InstrItinData<II_NMADD_S , [InstrStage<7, [ALU]>]>,
- InstrItinData<II_NMSUB_S , [InstrStage<7, [ALU]>]>,
- InstrItinData<II_MUL_D , [InstrStage<8, [ALU]>]>,
- InstrItinData<II_MADD_D , [InstrStage<8, [ALU]>]>,
- InstrItinData<II_MADDF_D , [InstrStage<8, [ALU]>]>,
- InstrItinData<II_MSUB_D , [InstrStage<8, [ALU]>]>,
- InstrItinData<II_MSUBF_D , [InstrStage<8, [ALU]>]>,
- InstrItinData<II_NMADD_D , [InstrStage<8, [ALU]>]>,
- InstrItinData<II_NMSUB_D , [InstrStage<8, [ALU]>]>,
- InstrItinData<II_DIV_S , [InstrStage<23, [ALU]>]>,
- InstrItinData<II_DIV_D , [InstrStage<36, [ALU]>]>,
- InstrItinData<II_RECIP_D , [InstrStage<25, [ALU]>]>,
- InstrItinData<II_RECIP_S , [InstrStage<13, [ALU]>]>,
- InstrItinData<II_RSQRT_D , [InstrStage<29, [ALU]>]>,
- InstrItinData<II_RSQRT_S , [InstrStage<14, [ALU]>]>,
- InstrItinData<II_RINT_D , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_RINT_S , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SQRT_S , [InstrStage<54, [ALU]>]>,
- InstrItinData<II_SQRT_D , [InstrStage<12, [ALU]>]>,
- InstrItinData<II_SEL_D , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SEL_S , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_WSBH , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_LSA , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_DLSA , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_LDC1 , [InstrStage<3, [ALU]>]>,
- InstrItinData<II_LDC2 , [InstrStage<3, [ALU]>]>,
- InstrItinData<II_LDC3 , [InstrStage<3, [ALU]>]>,
- InstrItinData<II_LWC1 , [InstrStage<3, [ALU]>]>,
- InstrItinData<II_LWC2 , [InstrStage<3, [ALU]>]>,
- InstrItinData<II_LWC3 , [InstrStage<3, [ALU]>]>,
- InstrItinData<II_LDXC1 , [InstrStage<3, [ALU]>]>,
- InstrItinData<II_LWXC1 , [InstrStage<3, [ALU]>]>,
- InstrItinData<II_LUXC1 , [InstrStage<3, [ALU]>]>,
- InstrItinData<II_LWXS , [InstrStage<3, [ALU]>]>,
- InstrItinData<II_SDC1 , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SDC2 , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SDC3 , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SWC1 , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SWC2 , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SWC3 , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SDXC1 , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SWXC1 , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_SUXC1 , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_DMFC0 , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_DMFC1 , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_DMFC2 , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_DMTC0 , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_DMTC1 , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_DMTC2 , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_MFC0 , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_MFHC0 , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_MFC1 , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_MFC2 , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_MFTR , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_MTC0 , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_MTHC0 , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_MTC1 , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_MTC2 , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_MFHC1 , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_MTHC1 , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_MTTR , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_CACHE , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_PREF , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_CACHEE , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_PREFE , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_TLBINV , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_TLBINVF , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_LLE , [InstrStage<3, [ALU]>]>,
- InstrItinData<II_SCE , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_WRPGPR , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_RDPGPR , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_DVP , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_EVP , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_YIELD , [InstrStage<5, [ALU]>]>,
- InstrItinData<II_CRC32B , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_CRC32H , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_CRC32W , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_CRC32D , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_CRC32CB , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_CRC32CH , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_CRC32CW , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_CRC32CD , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_MFGC0 , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_MTGC0 , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_MFHGC0 , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_MTHGC0 , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_HYPCALL , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_TLBGINV , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_TLBGINVF , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_TLBGP , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_TLBGR , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_TLBWI , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_TLBWR , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_DMFGC0 , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_DMTGC0 , [InstrStage<2, [ALU]>]>,
- InstrItinData<II_GINVI , [InstrStage<1, [ALU]>]>,
- InstrItinData<II_GINVT , [InstrStage<1, [ALU]>]>
-]>;
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.cpp b/llvm/lib/Target/Mips/MipsSubtarget.cpp
index 75f7a6c6a1118..287a4cbbf5af4 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.cpp
+++ b/llvm/lib/Target/Mips/MipsSubtarget.cpp
@@ -260,9 +260,6 @@ MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
// Parse features string.
ParseSubtargetFeatures(CPUName, /*TuneCPU*/ CPUName, FS);
- // Initialize scheduling itinerary for the specified CPU.
- InstrItins = getInstrItineraryForCPU(CPUName);
-
if (InMips16Mode && !IsSoftFloat)
InMips16HardFloat = true;
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.h b/llvm/lib/Target/Mips/MipsSubtarget.h
index 9d2f4d3c2d458..3acfaa82965ab 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.h
+++ b/llvm/lib/Target/Mips/MipsSubtarget.h
@@ -23,7 +23,6 @@
#include "llvm/CodeGen/RegisterBankInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DataLayout.h"
-#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/Support/ErrorHandling.h"
#define GET_SUBTARGETINFO_HEADER
@@ -227,8 +226,6 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
/// The overridden stack alignment.
MaybeAlign StackAlignOverride;
- InstrItineraryData InstrItins;
-
// We can override the determination of whether we are in mips16 mode
// as from the command line
enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
@@ -423,10 +420,6 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
const MipsTargetLowering *getTargetLowering() const override {
return TLInfo.get();
}
- const InstrItineraryData *getInstrItineraryData() const override {
- return &InstrItins;
- }
-
void initLibcallLoweringInfo(LibcallLoweringInfo &Info) const override;
protected:
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