[llvm] [LV] Pre-commit test for cast IV live-out optimization. nfc (PR #195055)
Mel Chen via llvm-commits
llvm-commits at lists.llvm.org
Mon May 4 01:15:14 PDT 2026
https://github.com/Mel-Chen updated https://github.com/llvm/llvm-project/pull/195055
>From 18947c1f91dc3c224cb9168ce24d6adc66aeb99c Mon Sep 17 00:00:00 2001
From: Mel Chen <mel.chen at sifive.com>
Date: Tue, 24 Mar 2026 01:54:09 -0700
Subject: [PATCH 1/2] [LV] Pre-commit for cast iv live-out
---
.../LoopVectorize/cast-iv-outside-user.ll | 66 +++++++++++++++++++
1 file changed, 66 insertions(+)
create mode 100644 llvm/test/Transforms/LoopVectorize/cast-iv-outside-user.ll
diff --git a/llvm/test/Transforms/LoopVectorize/cast-iv-outside-user.ll b/llvm/test/Transforms/LoopVectorize/cast-iv-outside-user.ll
new file mode 100644
index 0000000000000..c5aa66080db72
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/cast-iv-outside-user.ll
@@ -0,0 +1,66 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6
+; RUN: opt < %s -S -passes=loop-vectorize -force-vector-width=4 | FileCheck %s
+
+define i32 @incremented_iv_live_out(ptr %arr, i32 %n) {
+; CHECK-LABEL: define i32 @incremented_iv_live_out(
+; CHECK-SAME: ptr [[ARR:%.*]], i32 [[N:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64
+; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP0]], i64 1)
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[UMAX]], 4
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[UMAX]], 4
+; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[UMAX]], [[N_MOD_VF]]
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[ARR]], i64 [[INDEX]]
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i8>, ptr [[TMP1]], align 1
+; CHECK-NEXT: [[TMP2:%.*]] = add <4 x i8> [[WIDE_LOAD]], splat (i8 1)
+; CHECK-NEXT: store <4 x i8> [[TMP2]], ptr [[TMP1]], align 1
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
+; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[VEC_IND]], splat (i64 4)
+; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[TMP4:%.*]] = add <4 x i64> [[VEC_IND]], splat (i64 1)
+; CHECK-NEXT: [[TMP5:%.*]] = trunc <4 x i64> [[TMP4]] to <4 x i32>
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i32> [[TMP5]], i64 3
+; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[UMAX]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[ARR]], i64 [[IV]]
+; CHECK-NEXT: [[VAL:%.*]] = load i8, ptr [[GEP]], align 1
+; CHECK-NEXT: [[VAL_INC:%.*]] = add i8 [[VAL]], 1
+; CHECK-NEXT: store i8 [[VAL_INC]], ptr [[GEP]], align 1
+; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT: [[IV_TRUNC:%.*]] = trunc i64 [[IV_NEXT]] to i32
+; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[IV_TRUNC]], [[N]]
+; CHECK-NEXT: br i1 [[COND]], label %[[LOOP]], label %[[EXIT]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: [[IV_TRUNC_LCSSA:%.*]] = phi i32 [ [[IV_TRUNC]], %[[LOOP]] ], [ [[TMP6]], %[[MIDDLE_BLOCK]] ]
+; CHECK-NEXT: ret i32 [[IV_TRUNC_LCSSA]]
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %gep = getelementptr i8, ptr %arr, i64 %iv
+ %val = load i8, ptr %gep, align 1
+ %val.inc = add i8 %val, 1
+ store i8 %val.inc, ptr %gep, align 1
+ %iv.next = add i64 %iv, 1
+ %iv.trunc = trunc i64 %iv.next to i32
+ %cond = icmp ult i32 %iv.trunc, %n
+ br i1 %cond, label %loop, label %exit
+
+exit:
+ ret i32 %iv.trunc
+}
>From a35e3b96eb4ecf37877ce1ce1ec9e539743be697 Mon Sep 17 00:00:00 2001
From: Mel Chen <mel.chen at sifive.com>
Date: Mon, 4 May 2026 01:11:29 -0700
Subject: [PATCH 2/2] move the test case
---
.../LoopVectorize/cast-iv-outside-user.ll | 66 -----------
.../LoopVectorize/iv_outside_user.ll | 111 ++++++++++++++++++
2 files changed, 111 insertions(+), 66 deletions(-)
delete mode 100644 llvm/test/Transforms/LoopVectorize/cast-iv-outside-user.ll
diff --git a/llvm/test/Transforms/LoopVectorize/cast-iv-outside-user.ll b/llvm/test/Transforms/LoopVectorize/cast-iv-outside-user.ll
deleted file mode 100644
index c5aa66080db72..0000000000000
--- a/llvm/test/Transforms/LoopVectorize/cast-iv-outside-user.ll
+++ /dev/null
@@ -1,66 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6
-; RUN: opt < %s -S -passes=loop-vectorize -force-vector-width=4 | FileCheck %s
-
-define i32 @incremented_iv_live_out(ptr %arr, i32 %n) {
-; CHECK-LABEL: define i32 @incremented_iv_live_out(
-; CHECK-SAME: ptr [[ARR:%.*]], i32 [[N:%.*]]) {
-; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64
-; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP0]], i64 1)
-; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[UMAX]], 4
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
-; CHECK: [[VECTOR_PH]]:
-; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[UMAX]], 4
-; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[UMAX]], [[N_MOD_VF]]
-; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
-; CHECK: [[VECTOR_BODY]]:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[ARR]], i64 [[INDEX]]
-; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i8>, ptr [[TMP1]], align 1
-; CHECK-NEXT: [[TMP2:%.*]] = add <4 x i8> [[WIDE_LOAD]], splat (i8 1)
-; CHECK-NEXT: store <4 x i8> [[TMP2]], ptr [[TMP1]], align 1
-; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
-; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[VEC_IND]], splat (i64 4)
-; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
-; CHECK: [[MIDDLE_BLOCK]]:
-; CHECK-NEXT: [[TMP4:%.*]] = add <4 x i64> [[VEC_IND]], splat (i64 1)
-; CHECK-NEXT: [[TMP5:%.*]] = trunc <4 x i64> [[TMP4]] to <4 x i32>
-; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i32> [[TMP5]], i64 3
-; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[UMAX]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
-; CHECK: [[SCALAR_PH]]:
-; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
-; CHECK-NEXT: br label %[[LOOP:.*]]
-; CHECK: [[LOOP]]:
-; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
-; CHECK-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[ARR]], i64 [[IV]]
-; CHECK-NEXT: [[VAL:%.*]] = load i8, ptr [[GEP]], align 1
-; CHECK-NEXT: [[VAL_INC:%.*]] = add i8 [[VAL]], 1
-; CHECK-NEXT: store i8 [[VAL_INC]], ptr [[GEP]], align 1
-; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
-; CHECK-NEXT: [[IV_TRUNC:%.*]] = trunc i64 [[IV_NEXT]] to i32
-; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[IV_TRUNC]], [[N]]
-; CHECK-NEXT: br i1 [[COND]], label %[[LOOP]], label %[[EXIT]], !llvm.loop [[LOOP3:![0-9]+]]
-; CHECK: [[EXIT]]:
-; CHECK-NEXT: [[IV_TRUNC_LCSSA:%.*]] = phi i32 [ [[IV_TRUNC]], %[[LOOP]] ], [ [[TMP6]], %[[MIDDLE_BLOCK]] ]
-; CHECK-NEXT: ret i32 [[IV_TRUNC_LCSSA]]
-;
-entry:
- br label %loop
-
-loop:
- %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
- %gep = getelementptr i8, ptr %arr, i64 %iv
- %val = load i8, ptr %gep, align 1
- %val.inc = add i8 %val, 1
- store i8 %val.inc, ptr %gep, align 1
- %iv.next = add i64 %iv, 1
- %iv.trunc = trunc i64 %iv.next to i32
- %cond = icmp ult i32 %iv.trunc, %n
- br i1 %cond, label %loop, label %exit
-
-exit:
- ret i32 %iv.trunc
-}
diff --git a/llvm/test/Transforms/LoopVectorize/iv_outside_user.ll b/llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
index 8b38091adb77f..14018e6cfb47a 100644
--- a/llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
+++ b/llvm/test/Transforms/LoopVectorize/iv_outside_user.ll
@@ -1299,3 +1299,114 @@ loop:
exit:
ret i64 %iv.1.next
}
+
+define i32 @cast_incremented_iv_live_out(ptr %arr, i32 %n) {
+; VEC-LABEL: define i32 @cast_incremented_iv_live_out(
+; VEC-SAME: ptr [[ARR:%.*]], i32 [[N:%.*]]) {
+; VEC-NEXT: [[ENTRY:.*]]:
+; VEC-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64
+; VEC-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP0]], i64 1)
+; VEC-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[UMAX]], 2
+; VEC-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; VEC: [[VECTOR_PH]]:
+; VEC-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[UMAX]], 2
+; VEC-NEXT: [[N_VEC:%.*]] = sub i64 [[UMAX]], [[N_MOD_VF]]
+; VEC-NEXT: br label %[[VECTOR_BODY:.*]]
+; VEC: [[VECTOR_BODY]]:
+; VEC-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; VEC-NEXT: [[VEC_IND:%.*]] = phi <2 x i64> [ <i64 0, i64 1>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; VEC-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[ARR]], i64 [[INDEX]]
+; VEC-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i8>, ptr [[TMP1]], align 1
+; VEC-NEXT: [[TMP2:%.*]] = add <2 x i8> [[WIDE_LOAD]], splat (i8 1)
+; VEC-NEXT: store <2 x i8> [[TMP2]], ptr [[TMP1]], align 1
+; VEC-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
+; VEC-NEXT: [[VEC_IND_NEXT]] = add <2 x i64> [[VEC_IND]], splat (i64 2)
+; VEC-NEXT: [[TMP3:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; VEC-NEXT: br i1 [[TMP3]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}}
+; VEC: [[MIDDLE_BLOCK]]:
+; VEC-NEXT: [[TMP4:%.*]] = add <2 x i64> [[VEC_IND]], splat (i64 1)
+; VEC-NEXT: [[TMP5:%.*]] = trunc <2 x i64> [[TMP4]] to <2 x i32>
+; VEC-NEXT: [[TMP6:%.*]] = extractelement <2 x i32> [[TMP5]], i64 1
+; VEC-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[UMAX]], [[N_VEC]]
+; VEC-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; VEC: [[SCALAR_PH]]:
+; VEC-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; VEC-NEXT: br label %[[LOOP:.*]]
+; VEC: [[LOOP]]:
+; VEC-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; VEC-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[ARR]], i64 [[IV]]
+; VEC-NEXT: [[VAL:%.*]] = load i8, ptr [[GEP]], align 1
+; VEC-NEXT: [[VAL_INC:%.*]] = add i8 [[VAL]], 1
+; VEC-NEXT: store i8 [[VAL_INC]], ptr [[GEP]], align 1
+; VEC-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; VEC-NEXT: [[IV_TRUNC:%.*]] = trunc i64 [[IV_NEXT]] to i32
+; VEC-NEXT: [[COND:%.*]] = icmp ult i32 [[IV_TRUNC]], [[N]]
+; VEC-NEXT: br i1 [[COND]], label %[[LOOP]], label %[[EXIT]], {{!llvm.loop ![0-9]+}}
+; VEC: [[EXIT]]:
+; VEC-NEXT: [[IV_TRUNC_LCSSA:%.*]] = phi i32 [ [[IV_TRUNC]], %[[LOOP]] ], [ [[TMP6]], %[[MIDDLE_BLOCK]] ]
+; VEC-NEXT: ret i32 [[IV_TRUNC_LCSSA]]
+;
+; INTERLEAVE-LABEL: define i32 @cast_incremented_iv_live_out(
+; INTERLEAVE-SAME: ptr [[ARR:%.*]], i32 [[N:%.*]]) {
+; INTERLEAVE-NEXT: [[ENTRY:.*]]:
+; INTERLEAVE-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64
+; INTERLEAVE-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP0]], i64 1)
+; INTERLEAVE-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[UMAX]], 2
+; INTERLEAVE-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; INTERLEAVE: [[VECTOR_PH]]:
+; INTERLEAVE-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[UMAX]], 2
+; INTERLEAVE-NEXT: [[N_VEC:%.*]] = sub i64 [[UMAX]], [[N_MOD_VF]]
+; INTERLEAVE-NEXT: br label %[[VECTOR_BODY:.*]]
+; INTERLEAVE: [[VECTOR_BODY]]:
+; INTERLEAVE-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; INTERLEAVE-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1
+; INTERLEAVE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[ARR]], i64 [[INDEX]]
+; INTERLEAVE-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[ARR]], i64 [[TMP1]]
+; INTERLEAVE-NEXT: [[TMP4:%.*]] = load i8, ptr [[TMP2]], align 1
+; INTERLEAVE-NEXT: [[TMP5:%.*]] = load i8, ptr [[TMP3]], align 1
+; INTERLEAVE-NEXT: [[TMP6:%.*]] = add i8 [[TMP4]], 1
+; INTERLEAVE-NEXT: [[TMP7:%.*]] = add i8 [[TMP5]], 1
+; INTERLEAVE-NEXT: store i8 [[TMP6]], ptr [[TMP2]], align 1
+; INTERLEAVE-NEXT: store i8 [[TMP7]], ptr [[TMP3]], align 1
+; INTERLEAVE-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
+; INTERLEAVE-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; INTERLEAVE-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], {{!llvm.loop ![0-9]+}}
+; INTERLEAVE: [[MIDDLE_BLOCK]]:
+; INTERLEAVE-NEXT: [[TMP9:%.*]] = add i64 [[TMP1]], 1
+; INTERLEAVE-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP9]] to i32
+; INTERLEAVE-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[UMAX]], [[N_VEC]]
+; INTERLEAVE-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; INTERLEAVE: [[SCALAR_PH]]:
+; INTERLEAVE-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; INTERLEAVE-NEXT: br label %[[LOOP:.*]]
+; INTERLEAVE: [[LOOP]]:
+; INTERLEAVE-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; INTERLEAVE-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[ARR]], i64 [[IV]]
+; INTERLEAVE-NEXT: [[VAL:%.*]] = load i8, ptr [[GEP]], align 1
+; INTERLEAVE-NEXT: [[VAL_INC:%.*]] = add i8 [[VAL]], 1
+; INTERLEAVE-NEXT: store i8 [[VAL_INC]], ptr [[GEP]], align 1
+; INTERLEAVE-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; INTERLEAVE-NEXT: [[IV_TRUNC:%.*]] = trunc i64 [[IV_NEXT]] to i32
+; INTERLEAVE-NEXT: [[COND:%.*]] = icmp ult i32 [[IV_TRUNC]], [[N]]
+; INTERLEAVE-NEXT: br i1 [[COND]], label %[[LOOP]], label %[[EXIT]], {{!llvm.loop ![0-9]+}}
+; INTERLEAVE: [[EXIT]]:
+; INTERLEAVE-NEXT: [[IV_TRUNC_LCSSA:%.*]] = phi i32 [ [[IV_TRUNC]], %[[LOOP]] ], [ [[TMP10]], %[[MIDDLE_BLOCK]] ]
+; INTERLEAVE-NEXT: ret i32 [[IV_TRUNC_LCSSA]]
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %gep = getelementptr i8, ptr %arr, i64 %iv
+ %val = load i8, ptr %gep, align 1
+ %val.inc = add i8 %val, 1
+ store i8 %val.inc, ptr %gep, align 1
+ %iv.next = add i64 %iv, 1
+ %iv.trunc = trunc i64 %iv.next to i32
+ %cond = icmp ult i32 %iv.trunc, %n
+ br i1 %cond, label %loop, label %exit
+
+exit:
+ ret i32 %iv.trunc
+}
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