[llvm] [Thumb] Replace AddLikeOrOp with or_disjoint (NFC) (PR #195573)
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Sun May 3 19:03:45 PDT 2026
https://github.com/LumioseSil updated https://github.com/llvm/llvm-project/pull/195573
>From 952d80af93dc8844ab3002ca375e01e637ea8169 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Sun, 3 May 2026 21:38:33 -0400
Subject: [PATCH] [Thumb] Replace AddLikeOrOp with add_like
AddLikeOrOp is redundant now that we have add_like.
---
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp | 16 ++--------------
llvm/lib/Target/ARM/ARMInstrThumb.td | 22 +++-------------------
llvm/lib/Target/ARM/ARMInstrThumb2.td | 17 +++--------------
llvm/test/CodeGen/ARM/add-like-or.ll | 4 ++--
llvm/test/CodeGen/ARM/combine-vmovdrr.ll | 6 +++---
llvm/test/CodeGen/ARM/shift-combine.ll | 16 ++++++++--------
6 files changed, 21 insertions(+), 60 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 61b679d55fb47..44f1758721a2a 100644
--- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -60,13 +60,12 @@ class ARMDAGToDAGISel : public SelectionDAGISel {
ARMDAGToDAGISel() = delete;
explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm, CodeGenOptLevel OptLevel)
- : SelectionDAGISel(tm, OptLevel) {}
+ : SelectionDAGISel(tm, OptLevel), Subtarget(nullptr) {}
bool runOnMachineFunction(MachineFunction &MF) override {
// Reset the subtarget each time through.
Subtarget = &MF.getSubtarget<ARMSubtarget>();
- SelectionDAGISel::runOnMachineFunction(MF);
- return true;
+ return SelectionDAGISel::runOnMachineFunction(MF);
}
void PreprocessISelDAG() override;
@@ -106,8 +105,6 @@ class ARMDAGToDAGISel : public SelectionDAGISel {
return SelectImmShifterOperand(N, A, B, false);
}
- bool SelectAddLikeOr(SDNode *Parent, SDValue N, SDValue &Out);
-
bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
@@ -653,15 +650,6 @@ bool ARMDAGToDAGISel::SelectRegShifterOperand(SDValue N,
return true;
}
-// Determine whether an ISD::OR's operands are suitable to turn the operation
-// into an addition, which often has more compact encodings.
-bool ARMDAGToDAGISel::SelectAddLikeOr(SDNode *Parent, SDValue N, SDValue &Out) {
- assert(Parent->getOpcode() == ISD::OR && "unexpected parent");
- Out = N;
- return CurDAG->haveNoCommonBitsSet(N, Parent->getOperand(1));
-}
-
-
bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N,
SDValue &Base,
SDValue &OffImm) {
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td
index 1e2e3c30a78f7..7b62d76652ea8 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb.td
@@ -286,11 +286,6 @@ def t_addrmode_sp : MemOperand,
let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
}
-// Inspects parent to determine whether an or instruction can be implemented as
-// an add (i.e. whether we know overflow won't occur in the add).
-let WantsParent = true in
-def AddLikeOrOp : ComplexPattern<i32, 1, "SelectAddLikeOr">;
-
// Pattern to exclude immediates from matching
def non_imm32 : PatLeaf<(i32 GPR), [{ return !isa<ConstantSDNode>(N); }]>;
@@ -988,7 +983,7 @@ let isAdd = 1, hasSideEffects = 0 in {
T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
IIC_iALUi,
"add", "\t$Rd, $Rm, $imm3",
- [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>,
+ [(set tGPR:$Rd, (add_like tGPR:$Rm, imm0_7:$imm3))]>,
Sched<[WriteALU]> {
bits<3> imm3;
let Inst{8-6} = imm3;
@@ -998,7 +993,7 @@ let isAdd = 1, hasSideEffects = 0 in {
T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn),
(ins tGPR:$Rn, imm0_255_expr:$imm8), IIC_iALUi,
"add", "\t$Rdn, $imm8",
- [(set tGPR:$Rdn, (add tGPR:$Rn, imm0_255_expr:$imm8))]>,
+ [(set tGPR:$Rdn, (add_like tGPR:$Rn, imm0_255_expr:$imm8))]>,
Sched<[WriteALU]>;
// Add register
@@ -1007,7 +1002,7 @@ let isAdd = 1, hasSideEffects = 0 in {
T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
IIC_iALUr,
"add", "\t$Rd, $Rn, $Rm",
- [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>,
+ [(set tGPR:$Rd, (add_like tGPR:$Rn, tGPR:$Rm))]>,
Sched<[WriteALU]>;
/// Similar to the above except these set the 's' bit so the
@@ -1060,24 +1055,13 @@ let isAdd = 1, hasSideEffects = 0 in {
}
}
-// Thumb has more flexible short encodings for ADD than ORR, so use those where
-// possible.
-def : T1Pat<(or AddLikeOrOp:$Rn, imm0_7:$imm), (tADDi3 $Rn, imm0_7:$imm)>;
-
-def : T1Pat<(or AddLikeOrOp:$Rn, imm8_255:$imm), (tADDi8 $Rn, imm8_255:$imm)>;
-
-def : T1Pat<(or AddLikeOrOp:$Rn, tGPR:$Rm), (tADDrr $Rn, $Rm)>;
-
-
def : tInstAlias <"add${s}${p} $Rdn, $Rm",
(tADDrr tGPR:$Rdn,s_cc_out:$s, tGPR:$Rdn, tGPR:$Rm, pred:$p)>;
-
def : tInstSubst<"sub${s}${p} $rd, $rn, $imm",
(tADDi3 tGPR:$rd, s_cc_out:$s, tGPR:$rn, mod_imm1_7_neg:$imm, pred:$p)>;
def : tInstSubst<"sub${s}${p} $rdn, $imm",
(tADDi8 tGPR:$rdn, s_cc_out:$s, mod_imm8_255_neg:$imm, pred:$p)>;
-
// AND register
let isCommutable = 1 in
def tAND : // A8.6.12
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td
index e79adb370798e..26deba0190c48 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb2.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td
@@ -919,7 +919,7 @@ multiclass T2I_rbin_s_is<SDNode opnode> {
/// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
/// patterns for a binary operation that produces a value.
-multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, SDNode opnode,
+multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, SDPatternOperator opnode,
bit Commutable = 0> {
// shifted imm
// The register-immediate version is re-materializable. This is useful
@@ -2440,7 +2440,8 @@ def : Thumb2DSPPat<(int_arm_uxtab16 rGPR:$Rn, (rotr rGPR:$Rm, rot_imm:$rot)),
//
let isAdd = 1 in
-defm t2ADD : T2I_bin_ii12rs<0b000, "add", add, 1>;
+// add_like: match ISD::add and disjoint or (or_disjoint) to t2ADD* / t2ADDS*.
+defm t2ADD : T2I_bin_ii12rs<0b000, "add", add_like, 1>;
defm t2SUB : T2I_bin_ii12rs<0b101, "sub", sub>;
// ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
@@ -3037,18 +3038,6 @@ def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm),
def : T2Pat<(t2_so_imm_not:$src),
(t2MVNi t2_so_imm_not:$src)>;
-// There are shorter Thumb encodings for ADD than ORR, so to increase
-// Thumb2SizeReduction's chances later on we select a t2ADD for an or where
-// possible.
-def : T2Pat<(or AddLikeOrOp:$Rn, t2_so_imm:$imm),
- (t2ADDri rGPR:$Rn, t2_so_imm:$imm)>;
-
-def : T2Pat<(or AddLikeOrOp:$Rn, imm0_4095:$Rm),
- (t2ADDri12 rGPR:$Rn, imm0_4095:$Rm)>;
-
-def : T2Pat<(or AddLikeOrOp:$Rn, non_imm32:$Rm),
- (t2ADDrr $Rn, $Rm)>;
-
//===----------------------------------------------------------------------===//
// Multiply Instructions.
//
diff --git a/llvm/test/CodeGen/ARM/add-like-or.ll b/llvm/test/CodeGen/ARM/add-like-or.ll
index c0ddee8388041..0889b18902e29 100644
--- a/llvm/test/CodeGen/ARM/add-like-or.ll
+++ b/llvm/test/CodeGen/ARM/add-like-or.ll
@@ -258,8 +258,8 @@ define i32 @multiuse(i32 %i, ptr %x, ptr %y) {
;
; CHECK-T2-LABEL: multiuse:
; CHECK-T2: @ %bb.0: @ %entry
-; CHECK-T2-NEXT: lsls r0, r0, #1
-; CHECK-T2-NEXT: adds r0, #1
+; CHECK-T2-NEXT: movs r2, #1
+; CHECK-T2-NEXT: add.w r0, r2, r0, lsl #1
; CHECK-T2-NEXT: ldr.w r1, [r1, r0, lsl #2]
; CHECK-T2-NEXT: add r0, r1
; CHECK-T2-NEXT: bx lr
diff --git a/llvm/test/CodeGen/ARM/combine-vmovdrr.ll b/llvm/test/CodeGen/ARM/combine-vmovdrr.ll
index 83cbd5902f210..6c51ff4cf6c1b 100644
--- a/llvm/test/CodeGen/ARM/combine-vmovdrr.ll
+++ b/llvm/test/CodeGen/ARM/combine-vmovdrr.ll
@@ -47,12 +47,12 @@ define void @dynamicIndex(ptr %addr, ptr %addr2, i32 %index) {
; CHECK-NEXT: sub.w r4, r7, #8
; CHECK-NEXT: lsls r0, r0, #2
; CHECK-NEXT: vst1.64 {d16, d17}, [r3:128], r0
-; CHECK-NEXT: lsls r0, r2, #1
-; CHECK-NEXT: adds r0, #1
+; CHECK-NEXT: movs r0, #1
+; CHECK-NEXT: add.w r0, r0, r2, lsl #1
; CHECK-NEXT: and r0, r0, #3
; CHECK-NEXT: ldr r2, [r3]
; CHECK-NEXT: vldr d18, [r1]
-; CHECK-NEXT: orr.w r0, r12, r0, lsl #2
+; CHECK-NEXT: add.w r0, r12, r0, lsl #2
; CHECK-NEXT: ldr r0, [r0]
; CHECK-NEXT: vmov d16, r2, r0
; CHECK-NEXT: vtbl.8 d16, {d16, d17}, d18
diff --git a/llvm/test/CodeGen/ARM/shift-combine.ll b/llvm/test/CodeGen/ARM/shift-combine.ll
index 6566707b23b7a..5c70b2fb7f528 100644
--- a/llvm/test/CodeGen/ARM/shift-combine.ll
+++ b/llvm/test/CodeGen/ARM/shift-combine.ll
@@ -2205,15 +2205,15 @@ define <2 x i64> @lshr_into_vsri_shift1_i64(<2 x i64> %a, <2 x i64> %b) {
; CHECK-ALIGN-NEXT: ldr.w lr, [sp, #20]
; CHECK-ALIGN-NEXT: and r2, r2, #-2147483648
; CHECK-ALIGN-NEXT: lsrs.w r12, r12, #1
-; CHECK-ALIGN-NEXT: orr.w r1, r1, r12
+; CHECK-ALIGN-NEXT: add r1, r12
; CHECK-ALIGN-NEXT: ldr.w r12, [sp, #8]
; CHECK-ALIGN-NEXT: rrx r12, r12
-; CHECK-ALIGN-NEXT: orr.w r0, r0, r12
+; CHECK-ALIGN-NEXT: add r0, r12
; CHECK-ALIGN-NEXT: ldr.w r12, [sp, #16]
; CHECK-ALIGN-NEXT: lsrs.w lr, lr, #1
-; CHECK-ALIGN-NEXT: orr.w r3, r3, lr
+; CHECK-ALIGN-NEXT: add r3, lr
; CHECK-ALIGN-NEXT: rrx r12, r12
-; CHECK-ALIGN-NEXT: orr.w r2, r2, r12
+; CHECK-ALIGN-NEXT: add r2, r12
; CHECK-ALIGN-NEXT: pop {r7, pc}
;
; CHECK-V6M-LABEL: lshr_into_vsri_shift1_i64:
@@ -2228,18 +2228,18 @@ define <2 x i64> @lshr_into_vsri_shift1_i64(<2 x i64> %a, <2 x i64> %b) {
; CHECK-V6M-NEXT: ldr r7, [sp, #24]
; CHECK-V6M-NEXT: lsrs r7, r7, #1
; CHECK-V6M-NEXT: adds r6, r7, r6
-; CHECK-V6M-NEXT: orrs r0, r6
+; CHECK-V6M-NEXT: adds r0, r6, r0
; CHECK-V6M-NEXT: ands r2, r4
; CHECK-V6M-NEXT: ldr r4, [sp, #36]
; CHECK-V6M-NEXT: lsls r6, r4, #31
; CHECK-V6M-NEXT: ldr r7, [sp, #32]
; CHECK-V6M-NEXT: lsrs r7, r7, #1
; CHECK-V6M-NEXT: adds r6, r7, r6
-; CHECK-V6M-NEXT: orrs r2, r6
+; CHECK-V6M-NEXT: adds r2, r6, r2
; CHECK-V6M-NEXT: lsrs r5, r5, #1
-; CHECK-V6M-NEXT: orrs r1, r5
+; CHECK-V6M-NEXT: adds r1, r5, r1
; CHECK-V6M-NEXT: lsrs r4, r4, #1
-; CHECK-V6M-NEXT: orrs r3, r4
+; CHECK-V6M-NEXT: adds r3, r4, r3
; CHECK-V6M-NEXT: add sp, #4
; CHECK-V6M-NEXT: pop {r4, r5, r6, r7, pc}
bb1:
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